- 02 Jan, 2018 4 commits
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Jens Korinth authored
* started with external format (JSON) * noticed a problem: without Verilog module parameters Features cannot easily add capabilities etc. * postponing the project until later
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Jens Korinth authored
git-subtree-dir: packaging git-subtree-mainline: 1846cfbe git-subtree-split: 134b2f62
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Jens Korinth authored
git-subtree-dir: axi git-subtree-mainline: bea8ec99 git-subtree-split: b8f4c554
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Jens Korinth authored
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- 29 Dec, 2017 4 commits
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Jens Korinth authored
* width would not be propagated correctly * fixed, also changed standard write test to increase by 1 from offset, making accidental correctness less likely
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Jens Korinth authored
* addresses can be larger than 32bit, thus need to use Long * in fact, having the upper-most bit 1 already gave problems * fixed and updated all dependents
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Jens Korinth authored
* while high, won't execute any actions, but reset its step counter
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Jens Korinth authored
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- 28 Dec, 2017 1 commit
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Jens Korinth authored
* if constructor argument is given, will start sequence only while io.start is high * default is false for startable
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- 27 Dec, 2017 3 commits
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Jens Korinth authored
* read returns None by default * write returns the write value by default, does nothing
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Jens Korinth authored
* behavior cannot be generated statically, because VirtualRegisters would then be unable to access values and regs of the module * behavior is now generated by RegisterFile.behavior and RegisterFile.resetBehavior instead * fixed definition of generic registerfile (no custom IO, regs, etc.)
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Jens Korinth authored
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- 20 Dec, 2017 2 commits
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Jens Korinth authored
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Jens Korinth authored
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- 14 Dec, 2017 7 commits
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Jens Korinth authored
* missing top-level import fixed * VLNVs for bus interfaces fixed * package.tcl is now written to disk, contains the script (for debugging)
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Jens Korinth authored
* missing top-level import fixed * VLNVs for bus interfaces fixed * package.tcl is now written to disk, contains the script (for debugging)
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
* needs own class to change TLM name in Verilog * added AXI interface definition
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- 13 Dec, 2017 10 commits
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Jens Korinth authored
* arbitrary configs would sometimes mandate less bits for the address than required by the register map * could be fixed in the register map generator, but I opted to fix it by permanently widening the address to 32 bits (sufficient for all cases)
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Jens Korinth authored
* manually tested with Xilinx AXI Verification IP, looks fine
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
* AXI mandates that all ready signals be low during reset * unfortunately, not only is this not the case in Queues, but they actively start working while reset is high (insane) * fixed by manually pulling the signals low on reset * tested with Xilinx AXI Verification IP, all's well
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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- 12 Dec, 2017 2 commits
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Jens Korinth authored
* entirely based on Queues now, fixed firing logic * still with workaround for problem in Queue with optional fields * simplified ProgrammableMaster * changed Registers write method to return Response instead of Boolean * switched completely to Spec testing: register files are generated ad-hoc, corresponding master program and testing steps are automatically generated
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Jens Korinth authored
* register map contained always the same instances for each kind * core problem: the new ... generators are implicitly converted to const * fixed by adding random Gen element to both generators
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- 11 Dec, 2017 5 commits
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
* replaced FSM approach with Queues; each channel has its own Queue, and all is handled using the handshakes * simple, because 1-cycle reads and writes can be guaranteed
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Jens Korinth authored
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Jens Korinth authored
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- 10 Dec, 2017 2 commits
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Jens Korinth authored
* new scheme: chisel.axi is the main package * chisel.axi.Axi4 contains the full axi defs * chisel.axi.Axi4Lite contains the lite defs * chisel.axi.axi4 contains full Axi4 impls * chisel.axi.axi4lite contains lite impls * same applies for the generators, matching structure
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Jens Korinth authored
* moved DataWidth from top axi to Axi4/Axi4Lite objects * cleaned generators, adopted new naming structure * implemented generators for arbitrary register files * master actions improved, simpler constructors * master actions can be automatically generated from register file * need to clean up the namespaces etc. - gotten really messy
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