* started with external format (JSON)
* noticed a problem: without Verilog module parameters Features cannot
  easily add capabilities etc.
* postponing the project until later

git-subtree-dir: packaging
git-subtree-mainline: 1846cfbe
git-subtree-split: 134b2f62

git-subtree-dir: axi
git-subtree-mainline: bea8ec99
git-subtree-split: b8f4c554

* width would not be propagated correctly
* fixed, also changed standard write test to increase by 1 from offset,
  making accidental correctness less likely

* addresses can be larger than 32bit, thus need to use Long
* in fact, having the upper-most bit 1 already gave problems
* fixed and updated all dependents

* while high, won't execute any actions, but reset its step counter

* if constructor argument is given, will start sequence only while
  io.start is high
* default is false for startable

* read returns None by default
* write returns the write value by default, does nothing

* behavior cannot be generated statically, because VirtualRegisters
  would then be unable to access values and regs of the module
* behavior is now generated by RegisterFile.behavior and
  RegisterFile.resetBehavior instead
* fixed definition of generic registerfile (no custom IO, regs, etc.)

* missing top-level import fixed
* VLNVs for bus interfaces fixed
* package.tcl is now written to disk, contains the script (for
  debugging)

* missing top-level import fixed
* VLNVs for bus interfaces fixed
* package.tcl is now written to disk, contains the script (for
  debugging)

* needs own class to change TLM name in Verilog
* added AXI interface definition

* arbitrary configs would sometimes mandate less bits for the address
  than required by the register map
* could be fixed in the register map generator, but I opted to fix it by
  permanently widening the address to 32 bits (sufficient for all cases)

* manually tested with Xilinx AXI Verification IP, looks fine

* AXI mandates that all ready signals be low during reset
* unfortunately, not only is this not the case in Queues, but they
  actively start working while reset is high (insane)
* fixed by manually pulling the signals low on reset
* tested with Xilinx AXI Verification IP, all's well

* entirely based on Queues now, fixed firing logic
* still with workaround for problem in Queue with optional fields
* simplified ProgrammableMaster
* changed Registers write method to return Response instead of Boolean
* switched completely to Spec testing: register files are generated
  ad-hoc, corresponding master program and testing steps are
  automatically generated

* register map contained always the same instances for each kind
* core problem: the new ... generators are implicitly converted to const
* fixed by adding random Gen element to both generators

* replaced FSM approach with Queues; each channel has its own Queue, and
  all is handled using the handshakes
* simple, because 1-cycle reads and writes can be guaranteed

* new scheme: chisel.axi is the main package
* chisel.axi.Axi4 contains the full axi defs
* chisel.axi.Axi4Lite contains the lite defs
* chisel.axi.axi4 contains full Axi4 impls
* chisel.axi.axi4lite contains lite impls
* same applies for the generators, matching structure

* moved DataWidth from top axi to Axi4/Axi4Lite objects
* cleaned generators, adopted new naming structure
* implemented generators for arbitrary register files
* master actions improved, simpler constructors
* master actions can be automatically generated from register file
* need to clean up the namespaces etc. - gotten really messy