* started with external format (JSON)
* noticed a problem: without Verilog module parameters Features cannot
  easily add capabilities etc.
* postponing the project until later

7854cfd1 Update README.md - fix dead link
b992dd73 README.md edited online with Bitbucket
f15683a7 Update README.md
fdfd1420 Update README.md
2190c490 Write README.md
4531adea Update to Chisel 3.0 (SNAPSHOT)

git-subtree-dir: packaging
git-subtree-split: 7854cfd1

* miscutils, packaging are subprojects which are depended upon
* configured correspondingly in build.sbt, removed symlinks in src
* defined metadata for build artifact (incl. version)
* updated .gitignore to ignore temp files in subprojects

git-subtree-dir: miscutils
git-subtree-split: 0fec184f

* adapter to write data from Decoupled-Fifo as AXI4 master
* base address supplied as input
* all widths configurable
* FifoAxiAdapterTest1 uses DecoupledDataSource to test with
  constant data set
* can also be used to verify against AXI BFMs

* testing utility: provides fixed data via Decoupled
* configurable with/without wrap-around
* unit tests