1. 02 Jan, 2018 1 commit
    • Jens Korinth's avatar
      Start to draft the IP core · 0ddba2f3
      Jens Korinth authored
      * started with external format (JSON)
      * noticed a problem: without Verilog module parameters Features cannot
        easily add capabilities etc.
      * postponing the project until later
      0ddba2f3
  2. 15 Jul, 2017 1 commit
  3. 07 Jul, 2017 1 commit
  4. 01 Oct, 2016 1 commit
    • Jens Korinth's avatar
      Define proper subprojects in build.sbt · b8d8f0e1
      Jens Korinth authored
      * miscutils, packaging are subprojects which are depended upon
      * configured correspondingly in build.sbt, removed symlinks in src
      * defined metadata for build artifact (incl. version)
      * updated .gitignore to ignore temp files in subprojects
      b8d8f0e1
  5. 27 Aug, 2016 1 commit
  6. 10 Jul, 2016 1 commit
    • Jens Korinth's avatar
      First draft of FifoAxiAdapter · 4443aa0c
      Jens Korinth authored
      * adapter to write data from Decoupled-Fifo as AXI4 master
      * base address supplied as input
      * all widths configurable
      * FifoAxiAdapterTest1 uses DecoupledDataSource to test with
        constant data set
      * can also be used to verify against AXI BFMs
      4443aa0c
  7. 08 Jul, 2016 1 commit
    • Jens Korinth's avatar
      DecoupledDataSource module · 5a1f9945
      Jens Korinth authored
      * testing utility: provides fixed data via Decoupled
      * configurable with/without wrap-around
      * unit tests
      5a1f9945