* latency data now contains min, max and average
* new Json format implemented in scala
* fixed several minor issues in case of errors

* added type clk to the bd pin and a frequency of 125 MHz
* added some debug output
* fixed PS parameters (from PyNQ example design)

* changed to better name reflecting composition, target and freq

* updated Doxygen configs
* added two READMEs for the test builds

* fixed occurrences, renamed the member

* fixes support for 2016.4 and 2017.1
* improved modularity by implementing shared platform::generate
* checking results of runs in Vivado, adding list of logs to check in
  case of error
* cleanup

* compare support was completely broken, a wonder that the code ever
  seemed to work at all
* comparison of the actual Composition was missing; comparing
  Compositions is a bit tricky due to many isomorphisms in the
  definition
* opted to compare area utilization instead: Unlikely that two different
  compositions in the same DSE run will ever have _exactly_ the same
  number of LUTs, FFS, etc.
* should work now, comparison order: area, h-value, frequency

* new object JobExamples contains examples and dump code
* can be used to re-generate directly from the defs
* also added a README.md to mark optional/mandatory params

* previous RE did include many other runme.logs, fixed

* added only synth_1/runme.log, impl_1/runme.log
* tracking all runme.logs just scrambled the output and generated a lot
  of CPU load
* need better way to distinguish the sources; colors?

* missing report now correctly triggers re-evaluation of the core
* moved core.description file into 'ipcore' subdirectory
* fixed problem with relative paths for import file

* was in fact not implemented; fixed

* added new message to regex
* will subsume all placer errors of the form 'ERROR: [Place...'

* changed order to: Arch/Platform/Kernels/Counts/Freq
* makes a lot of sense, easier to find bitstreams for a given target

* new pattern example: `counter__arrayinit/012_042/090.0/baseline/pynq`
* adds useful groupings: compositions with the same kernels, same
  instance counts, same frequencies
* nesting is extremely deep, but still worked in test

* changed dir pattern, example: arraysum__12___counter__1--90.0
* much better readability, also works for names ending in a number
* may be too long; but tests were so far successful

* isRunning is now returning true instead of false on error
* fixed the problem, may incur up to 15secs of additional wait time

* not removed, but made optional w/default 128
* may be yet useful in certain cases

* since PyNQ does not have a board definition file, DDR and general PS
  parameters (e.g., APU freq) have to be set manually
* overridden createZynqPS in pynq.tcl takes care of that and also
  replaces the missing board automation for DDR, FIXED_IO

* making it optional was trivial, but support in PyNQ was not
* noticed that the board part of the ZedBoard and the support files for
the ZedBoard were used, this does not work (completely different board)
* had to pull the master XDC to find the clock pin and fix that
* Platforms can implement platform::create_clock_port to generate their
own clock ports
* plugin is used to generated the constraints "post-synth"
* Zedboard and PyNQ bitstreams build, but cannot be tested

* testing correct behavior of interpolators for simple cases (2/3
  value interpolation)
* added some inline doc for Benchmark

* extended tapasco_benchmark to record latencies for runtimes between
  2^0 and 2^31 clock cycles
* extended benchmark Json to record new data
* wrote linear interpolation base class to interpolate between
  measurements for both transfer speed and latencies
* fixed unit test, supplied Arbitrary for the InterruptLatency class
* updated and pretty-printed the Json example

* would return 0 when Configuration was parsed successfully
* now returning folded result of tasks

* tested HLS and bitstream composition for 2016.2 - 2017.1

* error messages were the problem: Tcl's exec interprets any output on
  stderr as an error condition by default (not only the actual retcode)
* this insane behavior can be fixed by using -ignorestderr parameter

* scanning all targets and devices, programming the first VX690T
* improved the bit_reload.sh scripts:
   - normal option parsing
   - enabled verbose output w/o driver reload
   - disabled 'default' bitstream (I mean, WTF?)
* moved bit_reload in VC709 into standard location in module

* replaced maxThread var in trait Composer by implicit argument to
  compose method, facilitates easy pass-through
* in Tcl, tapasco_jobs global and the Vivado maxThreads setting are only
  written if maxThreads is not None (default value)
* dse.Run sets the implicit to 1

* no longer used; tpc_freq must be set in scripts

* TimingReport would report _first_ max delay path; but there can be
  many, they are ordered by clock in the report
* added RepSeqMatcher to extend SequenceMatcher for Seq[T]
* sorted paths by slack and picked the ones with minimal slack (max
  delay path) and maximal slack (min delay path)
* also fixes minDelayPath, which is pretty useless, however

* LS patched this on TPC, forward ported it to TaPaSCo:
* OOC must extract Verilog includes, but must not add them via add_files
* hard to determine what an 'include' is, but IP-XACT component.xml
  contains this information -> parsed to an exclusion set
* confirmed to work with example from LS and standard "counter"