- 19 May, 2017 3 commits
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Jens Korinth authored
* latency data now contains min, max and average * new Json format implemented in scala * fixed several minor issues in case of errors
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Jens Korinth authored
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Jens Korinth authored
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- 17 May, 2017 3 commits
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Jens Korinth authored
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Jens Korinth authored
* added type clk to the bd pin and a frequency of 125 MHz * added some debug output * fixed PS parameters (from PyNQ example design)
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Jens Korinth authored
* changed to better name reflecting composition, target and freq
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- 16 May, 2017 5 commits
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Jens Korinth authored
* updated Doxygen configs * added two READMEs for the test builds
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Jens Korinth authored
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Jens Korinth authored
* fixed occurrences, renamed the member
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Jens Korinth authored
* fixes support for 2016.4 and 2017.1 * improved modularity by implementing shared platform::generate * checking results of runs in Vivado, adding list of logs to check in case of error * cleanup
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Jens Korinth authored
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- 15 May, 2017 13 commits
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Jens Korinth authored
* compare support was completely broken, a wonder that the code ever seemed to work at all * comparison of the actual Composition was missing; comparing Compositions is a bit tricky due to many isomorphisms in the definition * opted to compare area utilization instead: Unlikely that two different compositions in the same DSE run will ever have _exactly_ the same number of LUTs, FFS, etc. * should work now, comparison order: area, h-value, frequency
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Jens Korinth authored
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Jens Korinth authored
* new object JobExamples contains examples and dump code * can be used to re-generate directly from the defs * also added a README.md to mark optional/mandatory params
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Jens Korinth authored
* previous RE did include many other runme.logs, fixed
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Jens Korinth authored
* added only synth_1/runme.log, impl_1/runme.log * tracking all runme.logs just scrambled the output and generated a lot of CPU load * need better way to distinguish the sources; colors?
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
* missing report now correctly triggers re-evaluation of the core * moved core.description file into 'ipcore' subdirectory * fixed problem with relative paths for import file
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Jens Korinth authored
* was in fact not implemented; fixed
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Jens Korinth authored
* added new message to regex * will subsume all placer errors of the form 'ERROR: [Place...'
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Jens Korinth authored
* changed order to: Arch/Platform/Kernels/Counts/Freq * makes a lot of sense, easier to find bitstreams for a given target
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Jens Korinth authored
* new pattern example: `counter__arrayinit/012_042/090.0/baseline/pynq` * adds useful groupings: compositions with the same kernels, same instance counts, same frequencies * nesting is extremely deep, but still worked in test
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Jens Korinth authored
* changed dir pattern, example: arraysum__12___counter__1--90.0 * much better readability, also works for names ending in a number * may be too long; but tests were so far successful
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- 14 May, 2017 5 commits
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Jens Korinth authored
* isRunning is now returning true instead of false on error * fixed the problem, may incur up to 15secs of additional wait time
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Jens Korinth authored
* not removed, but made optional w/default 128 * may be yet useful in certain cases
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
* since PyNQ does not have a board definition file, DDR and general PS parameters (e.g., APU freq) have to be set manually * overridden createZynqPS in pynq.tcl takes care of that and also replaces the missing board automation for DDR, FIXED_IO
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- 13 May, 2017 2 commits
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Jens Korinth authored
* making it optional was trivial, but support in PyNQ was not * noticed that the board part of the ZedBoard and the support files for the ZedBoard were used, this does not work (completely different board) * had to pull the master XDC to find the clock pin and fix that * Platforms can implement platform::create_clock_port to generate their own clock ports * plugin is used to generated the constraints "post-synth" * Zedboard and PyNQ bitstreams build, but cannot be tested
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Jens Korinth authored
* testing correct behavior of interpolators for simple cases (2/3 value interpolation) * added some inline doc for Benchmark
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- 12 May, 2017 8 commits
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Jens Korinth authored
* extended tapasco_benchmark to record latencies for runtimes between 2^0 and 2^31 clock cycles * extended benchmark Json to record new data * wrote linear interpolation base class to interpolate between measurements for both transfer speed and latencies * fixed unit test, supplied Arbitrary for the InterruptLatency class * updated and pretty-printed the Json example
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Jens Korinth authored
* would return 0 when Configuration was parsed successfully * now returning folded result of tasks
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Jens Korinth authored
* tested HLS and bitstream composition for 2016.2 - 2017.1
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Jens Korinth authored
* error messages were the problem: Tcl's exec interprets any output on stderr as an error condition by default (not only the actual retcode) * this insane behavior can be fixed by using -ignorestderr parameter
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Jens Korinth authored
* scanning all targets and devices, programming the first VX690T * improved the bit_reload.sh scripts: - normal option parsing - enabled verbose output w/o driver reload - disabled 'default' bitstream (I mean, WTF?) * moved bit_reload in VC709 into standard location in module
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Jens Korinth authored
* replaced maxThread var in trait Composer by implicit argument to compose method, facilitates easy pass-through * in Tcl, tapasco_jobs global and the Vivado maxThreads setting are only written if maxThreads is not None (default value) * dse.Run sets the implicit to 1
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Jens Korinth authored
* no longer used; tpc_freq must be set in scripts
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Jens Korinth authored
* TimingReport would report _first_ max delay path; but there can be many, they are ordered by clock in the report * added RepSeqMatcher to extend SequenceMatcher for Seq[T] * sorted paths by slack and picked the ones with minimal slack (max delay path) and maximal slack (min delay path) * also fixes minDelayPath, which is pretty useless, however
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- 11 May, 2017 1 commit
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Jens Korinth authored
* LS patched this on TPC, forward ported it to TaPaSCo: * OOC must extract Verilog includes, but must not add them via add_files * hard to determine what an 'include' is, but IP-XACT component.xml contains this information -> parsed to an exclusion set * confirmed to work with example from LS and standard "counter"
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