* implemented both hardware (runtime) logging and constructor logging
  (compile time)
* mix-in trait Logging provides methods info, warn and error (and cinfo,
  cwarn, cerror resp. for constructor logging)
* logging level is controlled by implicit Logging.Level, determined at
  each call, allows for selective logging

* chisel3 is a little finicky with peek/poke: it seems only stuff in the
  io bundle of modules is really safe
* needed to replace peeking in the internal mems, since that seems
  to crash the LoFirrtlEvaluator
* all tests functional again

* new full speed test suite failed: output may not block
* fixed by adding new special case
* achieves full speed & correctness now

* DWC only worked correctly at full speed
* delays caused lost nibbles, fixed now
* added secondary test harness to test against a slow receiver

* minor bug: valid would be asserted during reset, fixed

* previous implementation was not capable of handling a continuous
  stream of data (continuity must be preserved to avoid congestion)
* new implementation fixes this and several other minor issues
* better unit test: now using inverted pairs of DWCs
* makes testing code much simpler and data/waves easier to check
* added additional tests to specify the required timing behavior
  (i.e., preserving continuous data streams)

* separate package for SignalGenerator can be removed
* unit test included

* upsizing mode (inWidth < outWidth) implemented
* added unit test support for upsizing

* basic Decoupled-based data width converter
* currently only downsizing implemented with endianess selector
* works, but performance is lackluster yet
* unit tests cover several interesting combinations in both endianesses

* testing utility: provides fixed data via Decoupled
* configurable with/without wrap-around
* unit tests