- 10 Jul, 2017 1 commit
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Jens Korinth authored
* external Vivado/Vivado HLS processes only log to files * for debugging it would be helpful to have the stdout and stderr of the processes log directly in the console * added ProcessLogger for the outputs; trace level, should only be activated selectively
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- 07 Jul, 2017 8 commits
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
Update BlueDMA and MSIxIntrCtrl to the newest versions See merge request !5
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Jaco Hofmann authored
- PCIE Burst Length 64 - FPGA Burst Length 256 - Alignment 32 Bytes - Fixes SUPPORTS_NARROW_BURST parameters - Adds NUM_READ_OUTSTANDING and NUM_WRITE_OUTSTANDING to help interconnects decide on the DMA features
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Jaco Hofmann authored
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- 06 Jul, 2017 18 commits
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Jens Korinth authored
* memory usage estimates are based on numbers reported by the Lichtenberg cluster, but are too conservative for normal users * removed check for memory entirely
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Jens Korinth authored
Adds 'sbt assembly' as necessary step to exeute tapasco. See merge request !4
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Jens Korinth authored
Allow evaluation of kernels using primitives provides as .ngc-files; See merge request !3
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Jens Korinth authored
Ports changes of the ATS Branch of TPC to Tapasco See merge request !1
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Jaco Hofmann authored
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Jaco Hofmann authored
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Lukas Sommer authored
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Jens Korinth authored
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Jaco Hofmann authored
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Jaco Hofmann authored
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Jaco Hofmann authored
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Jaco Hofmann authored
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Jaco Hofmann authored
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Jaco Hofmann authored
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Jaco Hofmann authored
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Jaco Hofmann authored
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Jaco Hofmann authored
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Jaco Hofmann authored
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- 29 Jun, 2017 6 commits
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Jens Korinth authored
* more detailed logs for each event, easier for debugging * also provides a rough idea of current progress during bughunt
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Jens Korinth authored
* another bug appeared, fixed * cleaned code, added more verbose output to log
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Jens Korinth authored
* address map code did not work correctly, fixed
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Jens Korinth authored
* netlist-only IP cores lead to problems with the clock constraints regarding the bus interfaces: Vivado could no longer infer the clock for each AXI interface automatically, leading to broken cores * removed netlist creation; deactivation of OOC builds in 2016.4+ fixes the core problem of synthesizing the same core dozens of times
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Jens Korinth authored
* ZipUtils now has flatten option for unzip (set by default) * if not set, will recreate directory structure in target dir
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Jens Korinth authored
* evaluation was too pessimistic for many cores, leading to designs significantly slower than possible * fixed by using more aggressive synthesis options * more aggressive pnr options had no measurable effect on WNS * using new options in both evaluation and compose
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- 09 Jun, 2017 7 commits
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Jens Korinth authored
* alternatives are now checked and built, in case the alternatives dimension is activated in DSE
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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