- 10 Jan, 2018 2 commits
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Jens Korinth authored
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Jens Korinth authored
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- 09 Jan, 2018 3 commits
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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- 08 Jan, 2018 1 commit
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Jens Korinth authored
* will need to use individual pins * started to move subsystem code to subsystem.tcl
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- 05 Jan, 2018 6 commits
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Jens Korinth authored
* need to simplify Platform scripts, move more code into a common base * will generalize and unify the basic structure of the project * does not work yet, but looks promising
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Jens Korinth authored
* Vivado HLS does not have a -notrace parameter for source command
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Jens Korinth authored
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Jens Korinth authored
* common_ip.tcl will contain all basic ip VLNVs * only differences are recorded in the _20xx.tcl scripts
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Jens Korinth authored
* found a way to express in IP-XACT that the interfaces are only bridged directly; there seems to be no way of doing this via Vivado, but since Xilinx is using it themselves (e.g., System Cache) I hope it'll work * also remove interconnect_reset port, since they do not exist on the reset generators
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Jens Korinth authored
* new interface: esa.cs.tu-darmstadt.de:tapasco:tapasco_clocks_resets:1.0 * bundles host, design and mem clocks and all reset kinds for easier connection of the subsystems * each subsystem should instantiate a ClocksResetsSlaveBridge to access the ports * the clocks and resets subsystem uses a ClocksResetsMasterBridge to propagate the clocks and resets * both IPs are zero-logic direct wire thruputs; only used to allow bundling at interface leve
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- 04 Jan, 2018 17 commits
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Jens Korinth authored
* there is a subproject that is included as a subtree in common/ip/tapasco_status * subproject is standalone and can be run from Tcl * changed process in common.tcl: createTapascoStatus now generates a JSON configuration file and runs sbt in the subproject * each Composition gets its unique status core * status cores are cached in tapasco-status-cache in the main dir: when building the same composition a number of times, status cores can be reused; is removed automatically in sbt clean * required more API extensions: platform::get_address_map must be implemented by the Platform to communicate the address mapping to the status core creation * also added formal interface to capabilities in common.tcl: tapasco::add_capability_flag, tapasco::get_capability_flags and tapasco::set_capability_flags can be used by plugins to activate capability bits * whole process should be transparent to the user, everything is supposed to work as before * one exception: get_address_map is not yet implemented on VC709
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Jens Korinth authored
Merge commit 'f94b6de3' into pe-local-memories
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Jens Korinth authored
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Jens Korinth authored
* following an internal discussion, we'd rather be sure to build everything from scratch in the runner, or version hell ensues
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Jens Korinth authored
Merge commit '5a089419'
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
* empty slots did not exist at all, resulting in reads/writes causing bus errors, crash * new Slot type Empty represents an empty slot * slots in status configuration are filled with empty slots to fix the problem * should not increase the size significantly; all empty slots are represented by the same ConstantRegister
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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- 03 Jan, 2018 11 commits
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Jens Korinth authored
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Jens Korinth authored
git-subtree-dir: common/ip/tapasco_status git-subtree-mainline: 225cfa31 git-subtree-split: e209f949
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
Merge commit 'a9f329c5'
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Jens Korinth authored
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Jens Korinth authored
* zero-width io ports must be assigned, or compilation will fail * fixed RegisterFileSpec accordingly * updated to Scala 2.11.12
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Jens Korinth authored
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