1. 10 Jan, 2018 1 commit
  2. 09 Jan, 2018 3 commits
  3. 08 Jan, 2018 1 commit
  4. 05 Jan, 2018 6 commits
    • Jens Korinth's avatar
      WIP: reimagine basic Platform construction · 3cdff64a
      Jens Korinth authored
      * need to simplify Platform scripts, move more code into a common base
      * will generalize and unify the basic structure of the project
      * does not work yet, but looks promising
    • Jens Korinth's avatar
      Fix bug for Vivado HLS · d04440b0
      Jens Korinth authored
      * Vivado HLS does not have a -notrace parameter for source command
    • Jens Korinth's avatar
    • Jens Korinth's avatar
      Add common_ip.tcl as base catalog · 0c33be87
      Jens Korinth authored
      * common_ip.tcl will contain all basic ip VLNVs
      * only differences are recorded in the _20xx.tcl scripts
    • Jens Korinth's avatar
      Fix problems with clocks and resets bridges · 8a43f455
      Jens Korinth authored
      * found a way to express in IP-XACT that the interfaces are only bridged
        directly; there seems to be no way of doing this via Vivado, but since
        Xilinx is using it themselves (e.g., System Cache) I hope it'll work
      * also remove interconnect_reset port, since they do not exist on the
        reset generators
    • Jens Korinth's avatar
      Implement a bus abstraction for TaPaSCo clocks and resets · 84c35860
      Jens Korinth authored
      * new interface:
      * bundles host, design and mem clocks and all reset kinds for easier
        connection of the subsystems
      * each subsystem should instantiate a ClocksResetsSlaveBridge to access
        the ports
      * the clocks and resets subsystem uses a ClocksResetsMasterBridge to
        propagate the clocks and resets
      * both IPs are zero-logic direct wire thruputs; only used to allow
        bundling at interface leve
  5. 04 Jan, 2018 17 commits
  6. 03 Jan, 2018 12 commits