1. 29 Jun, 2017 1 commit
    • Jens Korinth's avatar
      Bugfix: Remove netlist replacement for cores · 3c810860
      Jens Korinth authored
      * netlist-only IP cores lead to problems with the clock constraints
        regarding the bus interfaces: Vivado could no longer infer the clock
        for each AXI interface automatically, leading to broken cores
      * removed netlist creation; deactivation of OOC builds in 2016.4+ fixes
        the core problem of synthesizing the same core dozens of times
      3c810860
  2. 07 Jun, 2017 1 commit
  3. 06 Jun, 2017 3 commits
    • Jens Korinth's avatar
      Produce pre-synthesized netlists in EvaluateIP · 15b9811a
      Jens Korinth authored
      * synthesis can be accelerated by dumping an EDIF netlist during IP
        evaluation and only using the netlist in the IP-XACT core
      * no need to re-synthesize IP, especially useful in case of many
        instances
      * replaced old links to original zip files by new zip that contains only
        the component.xml and the netlist
      15b9811a
    • Jens Korinth's avatar
      Implement global 'maxThreads' parameter · fb0730d9
      Jens Korinth authored
      * better control to restrict parallelism (~ memory consumption)
      * global parameter --maxThreads [NUM] controls general.maxThreads in Vivado
      * applies to both synthesis and implementation
      * removed superfluous implicit in Composer
      fb0730d9
    • Jens Korinth's avatar
      Bugfix clean() in VivadoComposer · a8f64503
      Jens Korinth authored
      * stopped working due to rename of Vivado project
      a8f64503
  4. 01 Jun, 2017 1 commit
    • Jens Korinth's avatar
      Backport bugfixes and improvements from ATS branch · 615f6dd2
      Jens Korinth authored
      * backport improved vc709.tcl
      * support for MSI-X interrupts
      * support for BlueDMA replacement for dual_dma
      * Platform API: raw read/writes
      * setup.sh automatically builds .jar
      * Compose: dumps Configuration in output directory
      * Compose: adds activated Features to last dir level
      * new Feature ATS+PRI w/Tcl support
      * new Feature BlueDMA w/Tcl support
      * some bugfixes regarding Features
      615f6dd2
  5. 31 May, 2017 1 commit
    • Jens Korinth's avatar
      Closes #53, #68, #80 - Capabilities and Status Core · 74d948f8
      Jens Korinth authored
      * backported device capability interface
      * extended status core with new registers:
        + Vivado version
        + Tapasco version
        + Timestamp (UNIX)
        + Clocks (host, mem, design)
      * added new common methods to query the frequencies and globals to set
      * used as default by create_subsystem_clocks_and_resets
      * extended Platform to contain optional frequencies
      * implemented unit tests for each new property
      * if set, they are written to Tcl in VivadoComposer
      74d948f8
  6. 30 May, 2017 1 commit
  7. 17 May, 2017 1 commit
  8. 16 May, 2017 2 commits
  9. 15 May, 2017 4 commits
  10. 14 May, 2017 1 commit
    • Jens Korinth's avatar
      PyNQ: Fix DDR parameters, PS parameters · 1ce272eb
      Jens Korinth authored
      * since PyNQ does not have a board definition file, DDR and general PS
        parameters (e.g., APU freq) have to be set manually
      * overridden createZynqPS in pynq.tcl takes care of that and also
        replaces the missing board automation for DDR, FIXED_IO
      1ce272eb
  11. 13 May, 2017 1 commit
    • Jens Korinth's avatar
      Closes #55 - Platform: Make board part optional · 5bfe0e82
      Jens Korinth authored
      * making it optional was trivial, but support in PyNQ was not
      * noticed that the board part of the ZedBoard and the support files for
      the ZedBoard were used, this does not work (completely different board)
      * had to pull the master XDC to find the clock pin and fix that
      * Platforms can implement platform::create_clock_port to generate their
      own clock ports
      * plugin is used to generated the constraints "post-synth"
      * Zedboard and PyNQ bitstreams build, but cannot be tested
      5bfe0e82
  12. 12 May, 2017 1 commit
    • Jens Korinth's avatar
      Closes #2 - Fix number of threads in Compose · 5cec7aba
      Jens Korinth authored
      * replaced maxThread var in trait Composer by implicit argument to
        compose method, facilitates easy pass-through
      * in Tcl, tapasco_jobs global and the Vivado maxThreads setting are only
        written if maxThreads is not None (default value)
      * dse.Run sets the implicit to 1
      5cec7aba
  13. 11 May, 2017 2 commits
    • Jens Korinth's avatar
      Closes #51 - Parse component.xml to exclude Verilog includes · a1dc2f2e
      Jens Korinth authored
      * LS patched this on TPC, forward ported it to TaPaSCo:
      * OOC must extract Verilog includes, but must not add them via add_files
      * hard to determine what an 'include' is, but IP-XACT component.xml
        contains this information -> parsed to an exclusion set
      * confirmed to work with example from LS and standard "counter"
      a1dc2f2e
    • Jens Korinth's avatar
      Closes #21 - OOC: Do not delete files on error · ec9f64e1
      Jens Korinth authored
      * EvaluateIP would delete files from .zip regardless of result, leaving
        the directory in non-reproducible state, fixed
      * also fixed: in case of success, the base directory would not be
        deleted due to wrong order of `deleteOnExit`s
      ec9f64e1
  14. 09 May, 2017 1 commit