* new scheme: chisel.axi is the main package
* chisel.axi.Axi4 contains the full axi defs
* chisel.axi.Axi4Lite contains the lite defs
* chisel.axi.axi4 contains full Axi4 impls
* chisel.axi.axi4lite contains lite impls
* same applies for the generators, matching structure

*  split into subpackages axi4 and axi4lite
*  moved each module into its subpackage
*  shortened names by removing Axi-prefixes wherever possible
*  moved Configs and IOs into corresponding companion object
*  replaced some printlns/printfs with Logging facilities

* muxes N AXI-MM masters to one AXI-MM slave
* read and write channels are mux'ed independently
* no interruptions during bursts, next schedule on LAST
* address valid is used to signal transfer requests
* may cost up to N-1 cycles latency