1. 18 Jan, 2018 2 commits
  2. 16 Jan, 2018 1 commit
  3. 12 Jan, 2018 4 commits
  4. 11 Jan, 2018 3 commits
    • Jens Korinth's avatar
      Fix dual_dma constraints · 8a660e3d
      Jens Korinth authored
    • Jens Korinth's avatar
      Move all IP block related code into new namespace ip · 7ffe7520
      Jens Korinth authored
      * tapasco::ip contains methods to instantiate common IP
      * common/ip.tcl automatically generates methods based on the stdcomps
        directory: every name has its own instantiation method called
        create_<name>, which takes only a name as an argument
      * specialized constructors go into common_ip.tcl and can override the
        auto-generated ones
      * removed all createXY procs in common.tcl and fixed all dependent
        scripts accordingly
      * removed ill-fated "clocks_and_resets" bundle - sad, but didn't work
        correctly in Vivado
    • Jens Korinth's avatar
      VC709: finish Platform refactoring · 8d6b2d59
      Jens Korinth authored
      * VC709 designs should build again
      * generalized address mapping, same method should be applicable to other
        Platforms like Zynq, too
      * still WIP, need to move a few bits between implementations
  5. 10 Jan, 2018 3 commits
  6. 09 Jan, 2018 3 commits
  7. 08 Jan, 2018 1 commit
  8. 05 Jan, 2018 6 commits
    • Jens Korinth's avatar
      WIP: reimagine basic Platform construction · 3cdff64a
      Jens Korinth authored
      * need to simplify Platform scripts, move more code into a common base
      * will generalize and unify the basic structure of the project
      * does not work yet, but looks promising
    • Jens Korinth's avatar
      Fix bug for Vivado HLS · d04440b0
      Jens Korinth authored
      * Vivado HLS does not have a -notrace parameter for source command
    • Jens Korinth's avatar
    • Jens Korinth's avatar
      Add common_ip.tcl as base catalog · 0c33be87
      Jens Korinth authored
      * common_ip.tcl will contain all basic ip VLNVs
      * only differences are recorded in the _20xx.tcl scripts
    • Jens Korinth's avatar
      Fix problems with clocks and resets bridges · 8a43f455
      Jens Korinth authored
      * found a way to express in IP-XACT that the interfaces are only bridged
        directly; there seems to be no way of doing this via Vivado, but since
        Xilinx is using it themselves (e.g., System Cache) I hope it'll work
      * also remove interconnect_reset port, since they do not exist on the
        reset generators
    • Jens Korinth's avatar
      Implement a bus abstraction for TaPaSCo clocks and resets · 84c35860
      Jens Korinth authored
      * new interface:
      * bundles host, design and mem clocks and all reset kinds for easier
        connection of the subsystems
      * each subsystem should instantiate a ClocksResetsSlaveBridge to access
        the ports
      * the clocks and resets subsystem uses a ClocksResetsMasterBridge to
        propagate the clocks and resets
      * both IPs are zero-logic direct wire thruputs; only used to allow
        bundling at interface leve
  9. 04 Jan, 2018 17 commits