5b218b0 Pull chisel-axi
7cecbce Squashed 'axi/' changes from 01fad68..ec8f7a2
e56e93c Pull chisel-packaging
0e3cc98 Squashed 'packaging/' changes from c22243b..e6a5a78
4e421af Add assembly fatjar packaging, increase version to 1.0
41e37e7 Squashed 'axi/' changes from b8f4c554..01fad68
3fd53e7 Pull chisel-axi
872f551 Squashed 'packaging/' changes from 134b2f62..c22243b
88624e0 Pull chisel-packaging
f94b6de3 Remove caching of ivy repo from pipeline
43c331dc Pull chisel-axiutils
5937e2aa Implement cap0 bitfield
26d61dd6 Bugfix in pipeline
1030ffe5 Cache ivy2 repo in pipeline builds
14876b2e Implement support for capability field in Status Core
2a3e6856 Fix removed '<<=' sbt operator
bccc8a73 Run sbt test in GitLab pipeline
17e1a3a7 Fix bug concerning empty slots
5a089419 Ignore compiled python scripts in .gitignore
0f0a2d84 Update packaging to GitHub-version of Chisel3
a162cfae Update miscutils to GitHub-version of Chisel3
f0265156 Remove ununsed Scalactic dep
d146b992 Rename RegisterFile saxi port to s_axi

git-subtree-dir: common/ip/tapasco_status
git-subtree-split: 5b218b00f8f27f40c6cda836ddde5462f4296d33

Merge commit 'a9f329c5'

* zero-width io ports must be assigned, or compilation will fail
* fixed RegisterFileSpec accordingly
* updated to Scala 2.11.12

* re-used generic test from RegisterFile
* status configuration is generated by spec gens

Merge commit '8d79675d'

* Builder class main uses first argument as path to JSON config file
* IP Core is generated under ip/ hierarchy: each configuration hash is
  unique and can be used to cache products
* sbt clean removes this cache
* example.json contains an example configuration

* JsonSpec checks that roundtrips to and from Json preserve all data
* generators package contains ScalaCheck generators

* Status contains complete configuration, including kernel ids, memory
  slots and some basic sanity checking
* json package contains JSON SerDes functionality

* started with external format (JSON)
* noticed a problem: without Verilog module parameters Features cannot
  easily add capabilities etc.
* postponing the project until later

git-subtree-dir: packaging
git-subtree-mainline: 1846cfbe
git-subtree-split: 134b2f62

git-subtree-dir: axi
git-subtree-mainline: bea8ec99
git-subtree-split: b8f4c554

* width would not be propagated correctly
* fixed, also changed standard write test to increase by 1 from offset,
  making accidental correctness less likely

* addresses can be larger than 32bit, thus need to use Long
* in fact, having the upper-most bit 1 already gave problems
* fixed and updated all dependents

* while high, won't execute any actions, but reset its step counter

* if constructor argument is given, will start sequence only while
  io.start is high
* default is false for startable

* read returns None by default
* write returns the write value by default, does nothing

* behavior cannot be generated statically, because VirtualRegisters
  would then be unable to access values and regs of the module
* behavior is now generated by RegisterFile.behavior and
  RegisterFile.resetBehavior instead
* fixed definition of generic registerfile (no custom IO, regs, etc.)

* missing top-level import fixed
* VLNVs for bus interfaces fixed
* package.tcl is now written to disk, contains the script (for
  debugging)

* missing top-level import fixed
* VLNVs for bus interfaces fixed
* package.tcl is now written to disk, contains the script (for
  debugging)

* needs own class to change TLM name in Verilog
* added AXI interface definition