* rebuilt PyNQ, zedboard and ZC706 without features
* expanded subsystem package: standard and custom subsystems can be
  fetched (as bd cells) and their names queried (incl. custom)
* Zynqs adapt the memory system to bypass
* need to run more tests, but looks good
* timing problems in VC709, need to investigate

* tapasco::ip contains methods to instantiate common IP
* common/ip.tcl automatically generates methods based on the stdcomps
  directory: every name has its own instantiation method called
  create_<name>, which takes only a name as an argument
* specialized constructors go into common_ip.tcl and can override the
  auto-generated ones
* removed all createXY procs in common.tcl and fixed all dependent
  scripts accordingly
* removed ill-fated "clocks_and_resets" bundle - sad, but didn't work
  correctly in Vivado

* VC709 designs should build again
* generalized address mapping, same method should be applicable to other
  Platforms like Zynq, too
* still WIP, need to move a few bits between implementations

* will need to use individual pins
* started to move subsystem code to subsystem.tcl

* need to simplify Platform scripts, move more code into a common base
* will generalize and unify the basic structure of the project
* does not work yet, but looks promising

* Vivado HLS does not have a -notrace parameter for source command

* common_ip.tcl will contain all basic ip VLNVs
* only differences are recorded in the _20xx.tcl scripts

* found a way to express in IP-XACT that the interfaces are only bridged
  directly; there seems to be no way of doing this via Vivado, but since
  Xilinx is using it themselves (e.g., System Cache) I hope it'll work
* also remove interconnect_reset port, since they do not exist on the
  reset generators

* new interface:
  esa.cs.tu-darmstadt.de:tapasco:tapasco_clocks_resets:1.0
* bundles host, design and mem clocks and all reset kinds for easier
  connection of the subsystems
* each subsystem should instantiate a ClocksResetsSlaveBridge to access
  the ports
* the clocks and resets subsystem uses a ClocksResetsMasterBridge to
  propagate the clocks and resets
* both IPs are zero-logic direct wire thruputs; only used to allow
  bundling at interface leve

* there is a subproject that is included as a subtree in
  common/ip/tapasco_status
* subproject is standalone and can be run from Tcl
* changed process in common.tcl: createTapascoStatus now generates a
  JSON configuration file and runs sbt in the subproject
* each Composition gets its unique status core
* status cores are cached in tapasco-status-cache in the main dir:
  when building the same composition a number of times, status cores can
  be reused; is removed automatically in sbt clean
* required more API extensions: platform::get_address_map must be
  implemented by the Platform to communicate the address mapping to the
  status core creation
* also added formal interface to capabilities in common.tcl:
  tapasco::add_capability_flag, tapasco::get_capability_flags and
  tapasco::set_capability_flags can be used by plugins to activate
  capability bits
* whole process should be transparent to the user, everything is
  supposed to work as before
* one exception: get_address_map is not yet implemented on VC709

Merge commit 'f94b6de3' into pe-local-memories

* following an internal discussion, we'd rather be sure to build
  everything from scratch in the runner, or version hell ensues

Merge commit '5a089419'

* empty slots did not exist at all, resulting in reads/writes causing
  bus errors, crash
* new Slot type Empty represents an empty slot
* slots in status configuration are filled with empty slots to fix the
  problem
* should not increase the size significantly; all empty slots are
  represented by the same ConstantRegister