* empty slots did not exist at all, resulting in reads/writes causing
  bus errors, crash
* new Slot type Empty represents an empty slot
* slots in status configuration are filled with empty slots to fix the
  problem
* should not increase the size significantly; all empty slots are
  represented by the same ConstantRegister

* zero-width io ports must be assigned, or compilation will fail
* fixed RegisterFileSpec accordingly
* updated to Scala 2.11.12

* re-used generic test from RegisterFile
* status configuration is generated by spec gens

* Builder class main uses first argument as path to JSON config file
* IP Core is generated under ip/ hierarchy: each configuration hash is
  unique and can be used to cache products
* sbt clean removes this cache
* example.json contains an example configuration

* JsonSpec checks that roundtrips to and from Json preserve all data
* generators package contains ScalaCheck generators

* Status contains complete configuration, including kernel ids, memory
  slots and some basic sanity checking
* json package contains JSON SerDes functionality

* started with external format (JSON)
* noticed a problem: without Verilog module parameters Features cannot
  easily add capabilities etc.
* postponing the project until later

* width would not be propagated correctly
* fixed, also changed standard write test to increase by 1 from offset,
  making accidental correctness less likely

* addresses can be larger than 32bit, thus need to use Long
* in fact, having the upper-most bit 1 already gave problems
* fixed and updated all dependents

* while high, won't execute any actions, but reset its step counter

* fixed new issues; old scalastyle problems persist
* postponed fixing old issues

* GitLab pipelines notified me of the problem, awesome

* check all Job instances for empty filters, e.g., Platforms,
  Architectures, Kernels, and issue error message accordingly
* helpful error message contains available instances
* job is not executed, if check fails

* if constructor argument is given, will start sequence only while
  io.start is high
* default is false for startable

* read returns None by default
* write returns the write value by default, does nothing

* behavior cannot be generated statically, because VirtualRegisters
  would then be unable to access values and regs of the module
* behavior is now generated by RegisterFile.behavior and
  RegisterFile.resetBehavior instead
* fixed definition of generic registerfile (no custom IO, regs, etc.)

* needs own class to change TLM name in Verilog
* added AXI interface definition

* arbitrary configs would sometimes mandate less bits for the address
  than required by the register map
* could be fixed in the register map generator, but I opted to fix it by
  permanently widening the address to 32 bits (sufficient for all cases)

* manually tested with Xilinx AXI Verification IP, looks fine

* AXI mandates that all ready signals be low during reset
* unfortunately, not only is this not the case in Queues, but they
  actively start working while reset is high (insane)
* fixed by manually pulling the signals low on reset
* tested with Xilinx AXI Verification IP, all's well