1. 27 Aug, 2016 3 commits
  2. 06 Aug, 2016 1 commit
  3. 05 Aug, 2016 2 commits
  4. 04 Aug, 2016 2 commits
  5. 01 Aug, 2016 1 commit
    • Jens Korinth's avatar
      AxiFifoAdapter: Bugfix AXI interface · fde9d942
      Jens Korinth authored
      * opposed to FifoAxiAdapter, addresses may only be supplied via the
        interface if data will be read (slave will supply data)
      * this bug led to erroneous read bursts, overflowing the buffer
      * fixed some minor condition issues
      fde9d942
  6. 31 Jul, 2016 3 commits
    • Jens Korinth's avatar
      FifoAxiAdapter: fix transaction logic · 1383a12d
      Jens Korinth authored
      * addressess in transactions should be supplied as fast as possible
      * waiting for the transaction to finish is not necessary and harms
        performance
      * not sure if this implementation is ok; there could be a large gap
        between address handshake and data - if this blocks the slave it
        must be fixed (further tests required)
      1383a12d
    • Jens Korinth's avatar
      AxiFifoAdapterSuite: replace asserts with expects · bea25fbf
      Jens Korinth authored
      * asserts cause unit test to fail w/o VCD dump
      bea25fbf
    • Jens Korinth's avatar
      Simplify AxiFifoAdapter · e70fb06c
      Jens Korinth authored
      * replaced tick-tock-buffers with single FIFO
      * burst size now independent of buffer size
      * bursts start immediately when FIFO has space for one burst
      * operation similar to FifoAxiAdapter
      * unit tests work unchanged
      e70fb06c
  7. 27 Jul, 2016 1 commit
    • Jens Korinth's avatar
      Implement configurable read and write delays · dbf972b7
      Jens Korinth authored
      * considering the significant delays for real-world rw access
        to memory, AxiSlaveModel should have optional delays to sim
        that behavior
      * extracted config to AxiSlaveModelConfiguration class
      * adapted existing unit test suites
      * bugfix in Axi2AxiSuite: afa now waits for writes to finish
      dbf972b7
  8. 26 Jul, 2016 1 commit
    • Jens Korinth's avatar
      AxiFifoAdapter: Improve switching speed · c7b36058
      Jens Korinth authored
      * condition for switching of FIFOs led to 1-cycle delay
      * now switching when either other FIFO empty, or dequeing
        in progress and exactly one element
      * conditions are the same in both states
      c7b36058
  9. 22 Jul, 2016 2 commits
    • Jens Korinth's avatar
      Add Tcl scripts for Vivado projects with AXI BFMs · 7ce43604
      Jens Korinth authored
      * two scripts to generate block designs that will use AxiFifoAdapter
        and FifoAxiAdapter with the Cadence AXI BFMs
      * server also as cross-verification of Chisel AXI slave model
      * checks are not automated, results must be verified manually
      * AxiFifoAdapter uses Zynq BFM to preload DDR memory
      * added testbench and memory preload data for AxiFifoAdapter project
      * also added source code of preload file generator
      7ce43604
    • Jens Korinth's avatar
      FifoAxiAdapter: rewrite to use ASAP bursts · 5f640c4e
      Jens Korinth authored
      * now has single FIFO of configurable size
      * burst size is configurable separately
      * burst is started as soon as burstSize is exceeded in buffer
      * decided against even more aggressive mode of starting immediately,
        since that would likely be detrimental to system performance
      * adapted and verified all unit tests
      5f640c4e
  10. 21 Jul, 2016 1 commit
  11. 20 Jul, 2016 5 commits
    • Jens Korinth's avatar
      Implement full-round trip validating test · 4f3e1b66
      Jens Korinth authored
      * new test suite: uses both FifoAxiAdapter and AxiFifoAdapter to
        validate a full roundtrip on a AxiSlaveModel
      * most comprehensive test
      4f3e1b66
    • Jens Korinth's avatar
      AxiSlaveModel: Support write bursts · 6d6556b1
      Jens Korinth authored
      * also rewrote size-related code: addrWidth and size are now
        optional parameters, but one must be specified (other is calced)
      * fixed some issues with the write address masking (addresses are
        always byte-boundary)
      * modified tests accordingly
      * removed asserts from tests, using proper expect calls instead
        (test now finish with errors, instead of aborting pre-VCD dump)
      6d6556b1
    • Jens Korinth's avatar
      FifoAxiAdapter: Bugfix size parameter · 8e521465
      Jens Korinth authored
      * did not work correctly for different dataWidths
      * also size parameter in burst address was not set correctly:
        need to specify full-width bursts
      8e521465
    • Jens Korinth's avatar
      FifoAxiAdapter: Remove read channel · 6f9d34f8
      Jens Korinth authored
      6f9d34f8
    • Jens Korinth's avatar
      AxiFifoAdapter: improve performance · fe9d7b90
      Jens Korinth authored
      * now stays in fetch mode and just flips buffers, if current FIFO
        is empty
      * empty checks more aggressive: now checks if FIFO will be empty
        in the next cycle to mask the state transition
      fe9d7b90
  12. 19 Jul, 2016 1 commit
  13. 15 Jul, 2016 2 commits
  14. 14 Jul, 2016 3 commits
  15. 13 Jul, 2016 3 commits
  16. 10 Jul, 2016 2 commits
    • Jens Korinth's avatar
      AxiSlaveModel: implement mem size parameter · 26f72705
      Jens Korinth authored
      * memory size can now be controlled independently from addrWidth
        to allow large address spaces
      26f72705
    • Jens Korinth's avatar
      First draft of FifoAxiAdapter · 4443aa0c
      Jens Korinth authored
      * adapter to write data from Decoupled-Fifo as AXI4 master
      * base address supplied as input
      * all widths configurable
      * FifoAxiAdapterTest1 uses DecoupledDataSource to test with
        constant data set
      * can also be used to verify against AXI BFMs
      4443aa0c