* moved DataWidth from top axi to Axi4/Axi4Lite objects
* cleaned generators, adopted new naming structure
* implemented generators for arbitrary register files
* master actions improved, simpler constructors
* master actions can be automatically generated from register file
* need to clean up the namespaces etc. - gotten really messy

*  basic tests implemented
*  peekAt/pokeAt do not work; took a lot of time to figure out
*  need to implement a workaround using a serial interface
*  introduces its own problems, *sigh*

*  split into subpackages axi4 and axi4lite
*  moved each module into its subpackage
*  shortened names by removing Axi-prefixes wherever possible
*  moved Configs and IOs into corresponding companion object
*  replaced some printlns/printfs with Logging facilities

* AXI4Lite interface
* flexible ControlRegister class hierarchy: constants, single values,
  virtual registers (callbacks)
* implemented unit test cases
* had to implement Axi4LiteProgrammableMaster for batch testing

* muxes N AXI-MM masters to one AXI-MM slave
* read and write channels are mux'ed independently
* no interruptions during bursts, next schedule on LAST
* address valid is used to signal transfer requests
* may cost up to N-1 cycles latency

* renameSignals on AXI bundle should support prefix and suffix in order
  to accomodate multiple instance of the interface in one module

* configurable sliding window module with AXI DMA backend
* uses AxiFifoAdapter internally to retrieve data from AXI slave
* shifts with Decoupled interface
* generic module for arbitrary bitwidths / data types

* moved config params into sealed case class
* unified constructors to use new config object
* added companion object for convenience constructors (backward
  compatible)
* changed constructor calls in unit tests accordingly

* now has single FIFO of configurable size
* burst size is configurable separately
* burst is started as soon as burstSize is exceeded in buffer
* decided against even more aggressive mode of starting immediately,
  since that would likely be detrimental to system performance
* adapted and verified all unit tests

* adapter to write data from Decoupled-Fifo as AXI4 master
* base address supplied as input
* all widths configurable
* FifoAxiAdapterTest1 uses DecoupledDataSource to test with
  constant data set
* can also be used to verify against AXI BFMs