* moved DataWidth from top axi to Axi4/Axi4Lite objects
* cleaned generators, adopted new naming structure
* implemented generators for arbitrary register files
* master actions improved, simpler constructors
* master actions can be automatically generated from register file
* need to clean up the namespaces etc. - gotten really messy

*  split into subpackages axi4 and axi4lite
*  moved each module into its subpackage
*  shortened names by removing Axi-prefixes wherever possible
*  moved Configs and IOs into corresponding companion object
*  replaced some printlns/printfs with Logging facilities

* muxes N AXI-MM masters to one AXI-MM slave
* read and write channels are mux'ed independently
* no interruptions during bursts, next schedule on LAST
* address valid is used to signal transfer requests
* may cost up to N-1 cycles latency