- Closes #48

    - Works with the new status core format
    - Correctly verify size and offset of components
    - Made the status core JSON format more concise, e.g. no more
    unrelated lists for PE info and the offsets of the PE
    - Simplified compilation and various places and reduced
    interdependencies

    - Changes in driver completed
    - Changes in toolflow completed
    - TODO: Change runtime to work with new dynamic addressmap
    - TODO: Change driver to provide information about dynamic address
    map

    - Renamed TCL to Vivado for clearer directory names
    - Improves JSON produced by Vivado flow: Capabilities with name
    instead of hard-coded, Easier Structure for Architecture addresses
    - Adds Rust tool to encode JSON as Flatbuffer binary
    - Replaces custom Tapasco status core with simple AXI BRAM
    controller

    - Uses shim layer to convert between "old" MSIx Interface and US+
    MSIx interface
    - Adding additional US+ devices should be rather simple now

    - Maintaining the DualDMA and BlueDMA codepaths is tedious
    - DualDMA did not receive any maintenance for a long time and is
    lacking features such as work queues and parallel reads/write
    - Performance was also worse overall
    - Only advantage is a somewhat smaller LUT footprint, but that seems
    unimportant on the large devices we use for PCIe right now

* PCIe devices currently apply offsets to read/write addresses
  automatically, depending on whether or not this address falls into the
  Architecture range
* will open an issue discussing whether that's useful
* for now, platform::get_user_offset is subtracted from addresses in the
  status core to provide the "correct" addresses on PCIe devices

* calculation is platform-dependent: PCIe device with MSI-X only ever
  have one interrupt controller, Zynqs one for each 32 PEs
* moved into platform function number_of_interrupt_controllers
* implemented in Zynq and PCIe bases

* second run would mess up the address map if masters are present
* fixed and made the whole thing a little bit more stable

* now uses new subsystem framework

* at the moment, status cores will no longer be cached
* reason: due to the dual pass during build for the dynamic address map,
  two versions with different hashes, but identical VLNVs, would be
  built
* which one 'wins' is more or less random
* moved status core to user_ip directory of the project
* automatically delete first version of status core and replacing with
  new one during platform create

* arch::get_address_map now also registers the PEs so that the dynamic
  address map can be populated accordingly
* improved cap setting with single-point-of-truth: platform_caps.h is
  parsed in Tcl to generate the bit values for strings, making changes
  to the value easier
* used new approach in design master template

* platform/common/addressmap.tcl gathers methods related to this in
  namespace ::platform::addressmap
* defines methods to set base addresses for PEs and platform components
* used to generate the JSON for the status core
* does not yet contain useful platform component bases
* PE slots still with fixed size

Squashed commit of the following:

commit 13fdb518
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Mar 2 22:34:38 2018 +0100

    Recognize Tcl errors in Vivado logs

commit 90b74d7c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Mar 2 15:04:11 2018 +0100

    Make ILA debug feature generic for all platforms

    * only get_debug_nets depends on the platform
    * rest moved to platform/common/plugins
    * supporting platforms implement wrapper plugin, see
      platform/zynq/plugins/debug.tcl
    * fixed several other issues, e.g., clock selection
    * closes #132 - no master compositions

commit cc8a2df2
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Mar 2 10:57:10 2018 +0100

    Bugfixes in Debug feature

    * added ILA implementation feature on VC709
    * fixed SILA implementation feature on axi4mm
    * fixed renamed pos...