* muxes N AXI-MM masters to one AXI-MM slave
* read and write channels are mux'ed independently
* no interruptions during bursts, next schedule on LAST
* address valid is used to signal transfer requests
* may cost up to N-1 cycles latency

* renameSignals on AXI bundle should support prefix and suffix in order
  to accomodate multiple instance of the interface in one module

* configurable sliding window module with AXI DMA backend
* uses AxiFifoAdapter internally to retrieve data from AXI slave
* shifts with Decoupled interface
* generic module for arbitrary bitwidths / data types

* has method to fill AxiSlaveModel with structured data for testing

* moved config params into sealed case class
* unified constructors to use new config object
* added companion object for convenience constructors (backward
  compatible)
* changed constructor calls in unit tests accordingly

* size parameter indicates automatic address wrapping
* no need for resets in between (not always feasible)
* wraps on overflow to current value of `base` input

* new methods allow getter access via address or index
* set method supports writing at address

git-subtree-dir: miscutils
git-subtree-split: 0fec184f

git-subtree-dir: packaging
git-subtree-split: d2df30ff

* addresses should only be handshaked when data is actually avaiable /
  needed; previous logic would provide addresses as fast as possible
* this fixes problems with handshaken addresses at other modules when
  adapter is being reset

* opposed to FifoAxiAdapter, addresses may only be supplied via the
  interface if data will be read (slave will supply data)
* this bug led to erroneous read bursts, overflowing the buffer
* fixed some minor condition issues

* addressess in transactions should be supplied as fast as possible
* waiting for the transaction to finish is not necessary and harms
  performance
* not sure if this implementation is ok; there could be a large gap
  between address handshake and data - if this blocks the slave it
  must be fixed (further tests required)

* asserts cause unit test to fail w/o VCD dump

* replaced tick-tock-buffers with single FIFO
* burst size now independent of buffer size
* bursts start immediately when FIFO has space for one burst
* operation similar to FifoAxiAdapter
* unit tests work unchanged

* considering the significant delays for real-world rw access
  to memory, AxiSlaveModel should have optional delays to sim
  that behavior
* extracted config to AxiSlaveModelConfiguration class
* adapted existing unit test suites
* bugfix in Axi2AxiSuite: afa now waits for writes to finish

* condition for switching of FIFOs led to 1-cycle delay
* now switching when either other FIFO empty, or dequeing
  in progress and exactly one element
* conditions are the same in both states

* two scripts to generate block designs that will use AxiFifoAdapter
  and FifoAxiAdapter with the Cadence AXI BFMs
* server also as cross-verification of Chisel AXI slave model
* checks are not automated, results must be verified manually
* AxiFifoAdapter uses Zynq BFM to preload DDR memory
* added testbench and memory preload data for AxiFifoAdapter project
* also added source code of preload file generator

* now has single FIFO of configurable size
* burst size is configurable separately
* burst is started as soon as burstSize is exceeded in buffer
* decided against even more aggressive mode of starting immediately,
  since that would likely be detrimental to system performance
* adapted and verified all unit tests

* WSTRB now correctly adapts to dataWidth (all bytes enabled)

* new test suite: uses both FifoAxiAdapter and AxiFifoAdapter to
  validate a full roundtrip on a AxiSlaveModel
* most comprehensive test

* also rewrote size-related code: addrWidth and size are now
  optional parameters, but one must be specified (other is calced)
* fixed some issues with the write address masking (addresses are
  always byte-boundary)
* modified tests accordingly
* removed asserts from tests, using proper expect calls instead
  (test now finish with errors, instead of aborting pre-VCD dump)

* did not work correctly for different dataWidths
* also size parameter in burst address was not set correctly:
  need to specify full-width bursts

* now stays in fetch mode and just flips buffers, if current FIFO
  is empty
* empty checks more aggressive: now checks if FIFO will be empty
  in the next cycle to mask the state transition

* AR_LEN can be used directly for countdown var