- For now only sbt-prepare is shared for further jobs
    - There should be further sharing between Import and Compose

This reverts commit 32047b00.
The error this commit fixes was already fixed in a new Dockerfile
version.

    For whatever reason .bashrc is not evaluated...

Merge commit '8d677bb7' into gitlab-ci

3fd53e7 Pull chisel-axi
41e37e7 Squashed 'axi/' changes from b8f4c554..01fad68
88624e0 Pull chisel-packaging
872f551 Squashed 'packaging/' changes from 134b2f62..c22243b
f94b6de3 Remove caching of ivy repo from pipeline
43c331dc Pull chisel-axiutils
5937e2aa Implement cap0 bitfield
26d61dd6 Bugfix in pipeline
1030ffe5 Cache ivy2 repo in pipeline builds
14876b2e Implement support for capability field in Status Core
2a3e6856 Fix removed '<<=' sbt operator
bccc8a73 Run sbt test in GitLab pipeline
17e1a3a7 Fix bug concerning empty slots
5a089419 Ignore compiled python scripts in .gitignore
0f0a2d84 Update packaging to GitHub-version of Chisel3
a162cfae Update miscutils to GitHub-version of Chisel3
f0265156 Remove ununsed Scalactic dep
d146b992 Rename RegisterFile saxi port to s_axi

git-subtree-dir: common/ip/tapasco_status
git-subtree-split: 3fd53e7038ab7e1ff485eee94c3516f72b9604ea

* rebuilt PyNQ, zedboard and ZC706 without features
* expanded subsystem package: standard and custom subsystems can be
  fetched (as bd cells) and their names queried (incl. custom)
* Zynqs adapt the memory system to bypass
* need to run more tests, but looks good
* timing problems in VC709, need to investigate

* tapasco::ip contains methods to instantiate common IP
* common/ip.tcl automatically generates methods based on the stdcomps
  directory: every name has its own instantiation method called
  create_<name>, which takes only a name as an argument
* specialized constructors go into common_ip.tcl and can override the
  auto-generated ones
* removed all createXY procs in common.tcl and fixed all dependent
  scripts accordingly
* removed ill-fated "clocks_and_resets" bundle - sad, but didn't work
  correctly in Vivado

* VC709 designs should build again
* generalized address mapping, same method should be applicable to other
  Platforms like Zynq, too
* still WIP, need to move a few bits between implementations