* missing top-level import fixed
* VLNVs for bus interfaces fixed
* package.tcl is now written to disk, contains the script (for
  debugging)

* needs own class to change TLM name in Verilog
* added AXI interface definition

* arbitrary configs would sometimes mandate less bits for the address
  than required by the register map
* could be fixed in the register map generator, but I opted to fix it by
  permanently widening the address to 32 bits (sufficient for all cases)

* manually tested with Xilinx AXI Verification IP, looks fine

* AXI mandates that all ready signals be low during reset
* unfortunately, not only is this not the case in Queues, but they
  actively start working while reset is high (insane)
* fixed by manually pulling the signals low on reset
* tested with Xilinx AXI Verification IP, all's well

* entirely based on Queues now, fixed firing logic
* still with workaround for problem in Queue with optional fields
* simplified ProgrammableMaster
* changed Registers write method to return Response instead of Boolean
* switched completely to Spec testing: register files are generated
  ad-hoc, corresponding master program and testing steps are
  automatically generated

* register map contained always the same instances for each kind
* core problem: the new ... generators are implicitly converted to const
* fixed by adding random Gen element to both generators

* replaced FSM approach with Queues; each channel has its own Queue, and
  all is handled using the handshakes
* simple, because 1-cycle reads and writes can be guaranteed

* new scheme: chisel.axi is the main package
* chisel.axi.Axi4 contains the full axi defs
* chisel.axi.Axi4Lite contains the lite defs
* chisel.axi.axi4 contains full Axi4 impls
* chisel.axi.axi4lite contains lite impls
* same applies for the generators, matching structure

* moved DataWidth from top axi to Axi4/Axi4Lite objects
* cleaned generators, adopted new naming structure
* implemented generators for arbitrary register files
* master actions improved, simpler constructors
* master actions can be automatically generated from register file
* need to clean up the namespaces etc. - gotten really messy

* fixed some issues in ProgrammableMaster regarding wrong types of the
  response channels (was using old approach, direct UInt)
* fixed some issues in the register file spec, regarding peek/poke of
  non-IO fields, tests are functional

Merge commit 'e9ddda06381e35f203a5692dcd6395852424cb38'

Merge commit '48f930ee8d5d702ff5b29577c8dc13aef4b5363d'

e9ddda0 Remove direct references of reset

git-subtree-dir: miscutils
git-subtree-split: e9ddda06381e35f203a5692dcd6395852424cb38

5041968 SlowQueue: remove direct reset references
bc2de4a Minimize SignalGenerator
91f6202 Minimize DecoupledDataSource
435a442 Minimize DataWidthConverter logic

git-subtree-dir: miscutils
git-subtree-split: 5041968ba66ec8c5329d7da6594b3f031437730d