1. 25 Jan, 2018 5 commits
  2. 24 Jan, 2018 4 commits
  3. 23 Jan, 2018 1 commit
  4. 22 Jan, 2018 2 commits
    • Jens Korinth's avatar
      Pull tapasco-status · ee793881
      Jens Korinth authored
      Merge commit '82ce7119' into pe-local-memories
    • Jens Korinth's avatar
      Squashed 'common/ip/tapasco_status/' changes from e209f949..5b218b0 · 82ce7119
      Jens Korinth authored
      5b218b0 Pull chisel-axi
      7cecbce Squashed 'axi/' changes from 01fad68..ec8f7a2
      e56e93c Pull chisel-packaging
      0e3cc98 Squashed 'packaging/' changes from c22243b..e6a5a78
      4e421af Add assembly fatjar packaging, increase version to 1.0
      41e37e7 Squashed 'axi/' changes from b8f4c554..01fad68
      3fd53e7 Pull chisel-axi
      872f551 Squashed 'packaging/' changes from 134b2f62..c22243b
      88624e0 Pull chisel-packaging
      f94b6de3 Remove caching of ivy repo from pipeline
      43c331dc Pull chisel-axiutils
      5937e2aa Implement cap0 bitfield
      26d61dd6 Bugfix in pipeline
      1030ffe5 Cache ivy2 repo in pipeline builds
      14876b2e Implement support for capability field in Status Core
      2a3e6856 Fix removed '<<=' sbt operator
      bccc8a73 Run sbt test in GitLab pipeline
      17e1a3a7 Fix bug concerning empty slots
      5a089419 Ignore compiled python scripts in .gitignore
      0f0a2d84 Update packaging to GitHub-version of Chisel3
      a162cfae Update miscutils to GitHub-version of Chisel3
      f0265156 Remove ununsed Scalactic dep
      d146b992 Rename RegisterFile saxi port to s_axi
      git-subtree-dir: common/ip/tapasco_status
      git-subtree-split: 5b218b00f8f27f40c6cda836ddde5462f4296d33
  5. 19 Jan, 2018 1 commit
  6. 18 Jan, 2018 5 commits
  7. 16 Jan, 2018 1 commit
  8. 12 Jan, 2018 4 commits
  9. 11 Jan, 2018 3 commits
    • Jens Korinth's avatar
      Fix dual_dma constraints · 8a660e3d
      Jens Korinth authored
    • Jens Korinth's avatar
      Move all IP block related code into new namespace ip · 7ffe7520
      Jens Korinth authored
      * tapasco::ip contains methods to instantiate common IP
      * common/ip.tcl automatically generates methods based on the stdcomps
        directory: every name has its own instantiation method called
        create_<name>, which takes only a name as an argument
      * specialized constructors go into common_ip.tcl and can override the
        auto-generated ones
      * removed all createXY procs in common.tcl and fixed all dependent
        scripts accordingly
      * removed ill-fated "clocks_and_resets" bundle - sad, but didn't work
        correctly in Vivado
    • Jens Korinth's avatar
      VC709: finish Platform refactoring · 8d6b2d59
      Jens Korinth authored
      * VC709 designs should build again
      * generalized address mapping, same method should be applicable to other
        Platforms like Zynq, too
      * still WIP, need to move a few bits between implementations
  10. 10 Jan, 2018 3 commits
  11. 09 Jan, 2018 3 commits
  12. 08 Jan, 2018 1 commit
  13. 05 Jan, 2018 6 commits
    • Jens Korinth's avatar
      WIP: reimagine basic Platform construction · 3cdff64a
      Jens Korinth authored
      * need to simplify Platform scripts, move more code into a common base
      * will generalize and unify the basic structure of the project
      * does not work yet, but looks promising
    • Jens Korinth's avatar
      Fix bug for Vivado HLS · d04440b0
      Jens Korinth authored
      * Vivado HLS does not have a -notrace parameter for source command
    • Jens Korinth's avatar
    • Jens Korinth's avatar
      Add common_ip.tcl as base catalog · 0c33be87
      Jens Korinth authored
      * common_ip.tcl will contain all basic ip VLNVs
      * only differences are recorded in the _20xx.tcl scripts
    • Jens Korinth's avatar
      Fix problems with clocks and resets bridges · 8a43f455
      Jens Korinth authored
      * found a way to express in IP-XACT that the interfaces are only bridged
        directly; there seems to be no way of doing this via Vivado, but since
        Xilinx is using it themselves (e.g., System Cache) I hope it'll work
      * also remove interconnect_reset port, since they do not exist on the
        reset generators
    • Jens Korinth's avatar
      Implement a bus abstraction for TaPaSCo clocks and resets · 84c35860
      Jens Korinth authored
      * new interface:
      * bundles host, design and mem clocks and all reset kinds for easier
        connection of the subsystems
      * each subsystem should instantiate a ClocksResetsSlaveBridge to access
        the ports
      * the clocks and resets subsystem uses a ClocksResetsMasterBridge to
        propagate the clocks and resets
      * both IPs are zero-logic direct wire thruputs; only used to allow
        bundling at interface leve
  14. 04 Jan, 2018 1 commit
    • Jens Korinth's avatar
      Implement automatic build process for new Status Core · 15f96d39
      Jens Korinth authored
      * there is a subproject that is included as a subtree in
      * subproject is standalone and can be run from Tcl
      * changed process in common.tcl: createTapascoStatus now generates a
        JSON configuration file and runs sbt in the subproject
      * each Composition gets its unique status core
      * status cores are cached in tapasco-status-cache in the main dir:
        when building the same composition a number of times, status cores can
        be reused; is removed automatically in sbt clean
      * required more API extensions: platform::get_address_map must be
        implemented by the Platform to communicate the address mapping to the
        status core creation
      * also added formal interface to capabilities in common.tcl:
        tapasco::add_capability_flag, tapasco::get_capability_flags and
        tapasco::set_capability_flags can be used by plugins to activate
        capability bits
      * whole process should be transparent to the user, everything is
        supposed to work as before
      * one exception: get_address_map is not yet implemented on VC709