- 25 Jan, 2018 5 commits
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Jens Korinth authored
* improved sys clock detection by checking available interfaces via get_board_part_interfaces, instead of trying sys_diff_clock first * also removed second warning when get_bd_pins returns nothing * removed old, unused platform code
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Jens Korinth authored
* contains the manually set top.xdc directives * identical to Pynq, except for peripheral components
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Jens Korinth authored
* Digilent has newer def of ZedBoard, using that automatically now * imported via MYVIVADO / XILINX_PATH env vars
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Jens Korinth authored
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Jens Korinth authored
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- 24 Jan, 2018 4 commits
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Jens Korinth authored
* plugin could not change VLNV for dual_dma due to new location of stdcomps
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Jens Korinth authored
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Lukas Sommer authored
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Jens Korinth authored
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- 23 Jan, 2018 1 commit
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Jens Korinth authored
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- 22 Jan, 2018 2 commits
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Jens Korinth authored
Merge commit '82ce7119' into pe-local-memories
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Jens Korinth authored
5b218b0 Pull chisel-axi 7cecbce Squashed 'axi/' changes from 01fad68..ec8f7a2 e56e93c Pull chisel-packaging 0e3cc98 Squashed 'packaging/' changes from c22243b..e6a5a78 4e421af Add assembly fatjar packaging, increase version to 1.0 41e37e7 Squashed 'axi/' changes from b8f4c554..01fad68 3fd53e7 Pull chisel-axi 872f551 Squashed 'packaging/' changes from 134b2f62..c22243b 88624e0 Pull chisel-packaging f94b6de3 Remove caching of ivy repo from pipeline 43c331dc Pull chisel-axiutils 5937e2aa Implement cap0 bitfield 26d61dd6 Bugfix in pipeline 1030ffe5 Cache ivy2 repo in pipeline builds 14876b2e Implement support for capability field in Status Core 2a3e6856 Fix removed '<<=' sbt operator bccc8a73 Run sbt test in GitLab pipeline 17e1a3a7 Fix bug concerning empty slots 5a089419 Ignore compiled python scripts in .gitignore 0f0a2d84 Update packaging to GitHub-version of Chisel3 a162cfae Update miscutils to GitHub-version of Chisel3 f0265156 Remove ununsed Scalactic dep d146b992 Rename RegisterFile saxi port to s_axi git-subtree-dir: common/ip/tapasco_status git-subtree-split: 5b218b00f8f27f40c6cda836ddde5462f4296d33
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- 19 Jan, 2018 1 commit
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Jens Korinth authored
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- 18 Jan, 2018 5 commits
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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- 16 Jan, 2018 1 commit
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Jens Korinth authored
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- 12 Jan, 2018 4 commits
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
* rebuilt PyNQ, zedboard and ZC706 without features * expanded subsystem package: standard and custom subsystems can be fetched (as bd cells) and their names queried (incl. custom) * Zynqs adapt the memory system to bypass * need to run more tests, but looks good * timing problems in VC709, need to investigate
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Jens Korinth authored
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- 11 Jan, 2018 3 commits
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Jens Korinth authored
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Jens Korinth authored
* tapasco::ip contains methods to instantiate common IP * common/ip.tcl automatically generates methods based on the stdcomps directory: every name has its own instantiation method called create_<name>, which takes only a name as an argument * specialized constructors go into common_ip.tcl and can override the auto-generated ones * removed all createXY procs in common.tcl and fixed all dependent scripts accordingly * removed ill-fated "clocks_and_resets" bundle - sad, but didn't work correctly in Vivado
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Jens Korinth authored
* VC709 designs should build again * generalized address mapping, same method should be applicable to other Platforms like Zynq, too * still WIP, need to move a few bits between implementations
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- 10 Jan, 2018 3 commits
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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- 09 Jan, 2018 3 commits
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Jens Korinth authored
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Jens Korinth authored
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Jens Korinth authored
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- 08 Jan, 2018 1 commit
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Jens Korinth authored
* will need to use individual pins * started to move subsystem code to subsystem.tcl
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- 05 Jan, 2018 6 commits
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Jens Korinth authored
* need to simplify Platform scripts, move more code into a common base * will generalize and unify the basic structure of the project * does not work yet, but looks promising
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Jens Korinth authored
* Vivado HLS does not have a -notrace parameter for source command
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Jens Korinth authored
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Jens Korinth authored
* common_ip.tcl will contain all basic ip VLNVs * only differences are recorded in the _20xx.tcl scripts
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Jens Korinth authored
* found a way to express in IP-XACT that the interfaces are only bridged directly; there seems to be no way of doing this via Vivado, but since Xilinx is using it themselves (e.g., System Cache) I hope it'll work * also remove interconnect_reset port, since they do not exist on the reset generators
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Jens Korinth authored
* new interface: esa.cs.tu-darmstadt.de:tapasco:tapasco_clocks_resets:1.0 * bundles host, design and mem clocks and all reset kinds for easier connection of the subsystems * each subsystem should instantiate a ClocksResetsSlaveBridge to access the ports * the clocks and resets subsystem uses a ClocksResetsMasterBridge to propagate the clocks and resets * both IPs are zero-logic direct wire thruputs; only used to allow bundling at interface leve
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- 04 Jan, 2018 1 commit
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Jens Korinth authored
* there is a subproject that is included as a subtree in common/ip/tapasco_status * subproject is standalone and can be run from Tcl * changed process in common.tcl: createTapascoStatus now generates a JSON configuration file and runs sbt in the subproject * each Composition gets its unique status core * status cores are cached in tapasco-status-cache in the main dir: when building the same composition a number of times, status cores can be reused; is removed automatically in sbt clean * required more API extensions: platform::get_address_map must be implemented by the Platform to communicate the address mapping to the status core creation * also added formal interface to capabilities in common.tcl: tapasco::add_capability_flag, tapasco::get_capability_flags and tapasco::set_capability_flags can be used by plugins to activate capability bits * whole process should be transparent to the user, everything is supposed to work as before * one exception: get_address_map is not yet implemented on VC709
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