1. 17 May, 2017 1 commit
  2. 16 May, 2017 5 commits
  3. 15 May, 2017 13 commits
  4. 14 May, 2017 5 commits
  5. 13 May, 2017 2 commits
    • Jens Korinth's avatar
      Closes #55 - Platform: Make board part optional · 5bfe0e82
      Jens Korinth authored
      * making it optional was trivial, but support in PyNQ was not
      * noticed that the board part of the ZedBoard and the support files for
      the ZedBoard were used, this does not work (completely different board)
      * had to pull the master XDC to find the clock pin and fix that
      * Platforms can implement platform::create_clock_port to generate their
      own clock ports
      * plugin is used to generated the constraints "post-synth"
      * Zedboard and PyNQ bitstreams build, but cannot be tested
      5bfe0e82
    • Jens Korinth's avatar
      Implement ScalaCheck properties for Benchmark interpolators · e38d3aef
      Jens Korinth authored
      * testing correct behavior of interpolators for simple cases (2/3
        value interpolation)
      * added some inline doc for Benchmark
      e38d3aef
  6. 12 May, 2017 8 commits
    • Jens Korinth's avatar
      Platform: Add latency function · 40e9463a
      Jens Korinth authored
      * extended tapasco_benchmark to record latencies for runtimes between
        2^0 and 2^31 clock cycles
      * extended benchmark Json to record new data
      * wrote linear interpolation base class to interpolate between
        measurements for both transfer speed and latencies
      * fixed unit test, supplied Arbitrary for the InterruptLatency class
      * updated and pretty-printed the Json example
      40e9463a
    • Jens Korinth's avatar
      Closes #54 - Tapasco return code is wrong · de5ccefa
      Jens Korinth authored
      * would return 0 when Configuration was parsed successfully
      * now returning folded result of tasks
      de5ccefa
    • Jens Korinth's avatar
      Closes #26 - Check Vivado Compatibility · 60d8e621
      Jens Korinth authored
      * tested HLS and bitstream composition for 2016.2 - 2017.1
      60d8e621
    • Jens Korinth's avatar
      Closes #56 - Vivado HLS 2016.4+ crashes during HLS · e5f2ad89
      Jens Korinth authored
      * error messages were the problem: Tcl's exec interprets any output on
        stderr as an error condition by default (not only the actual retcode)
      * this insane behavior can be fixed by using -ignorestderr parameter
      e5f2ad89
    • Jens Korinth's avatar
      Closes #5 - VC709: Support multiple FPGAs in JTAG chain · 310d1be1
      Jens Korinth authored
      * scanning all targets and devices, programming the first VX690T
      * improved the bit_reload.sh scripts:
         - normal option parsing
         - enabled verbose output w/o driver reload
         - disabled 'default' bitstream (I mean, WTF?)
      * moved bit_reload in VC709 into standard location in module
      310d1be1
    • Jens Korinth's avatar
      Closes #2 - Fix number of threads in Compose · 5cec7aba
      Jens Korinth authored
      * replaced maxThread var in trait Composer by implicit argument to
        compose method, facilitates easy pass-through
      * in Tcl, tapasco_jobs global and the Vivado maxThreads setting are only
        written if maxThreads is not None (default value)
      * dse.Run sets the implicit to 1
      5cec7aba
    • Jens Korinth's avatar
      Remove TAPASCO_FREQ environment variable · ce53b756
      Jens Korinth authored
      * no longer used; tpc_freq must be set in scripts
      ce53b756
    • Jens Korinth's avatar
      Closes #50 - Timing Report: Reports false max delay path · 7bb05b40
      Jens Korinth authored
      * TimingReport would report _first_ max delay path; but there can be
        many, they are ordered by clock in the report
      * added RepSeqMatcher to extend SequenceMatcher for Seq[T]
      * sorted paths by slack and picked the ones with minimal slack (max
        delay path) and maximal slack (min delay path)
      * also fixes minDelayPath, which is pretty useless, however
      7bb05b40
  7. 11 May, 2017 4 commits
    • Jens Korinth's avatar
      Closes #51 - Parse component.xml to exclude Verilog includes · a1dc2f2e
      Jens Korinth authored
      * LS patched this on TPC, forward ported it to TaPaSCo:
      * OOC must extract Verilog includes, but must not add them via add_files
      * hard to determine what an 'include' is, but IP-XACT component.xml
        contains this information -> parsed to an exclusion set
      * confirmed to work with example from LS and standard "counter"
      a1dc2f2e
    • Jens Korinth's avatar
      Closes #21 - OOC: Do not delete files on error · ec9f64e1
      Jens Korinth authored
      * EvaluateIP would delete files from .zip regardless of result, leaving
        the directory in non-reproducible state, fixed
      * also fixed: in case of success, the base directory would not be
        deleted due to wrong order of `deleteOnExit`s
      ec9f64e1
    • Jens Korinth's avatar
      Add Terminology man page · 87f0de99
      Jens Korinth authored
      87f0de99
    • Jens Korinth's avatar
      Closes #46 - Man pages · a02ac9e1
      Jens Korinth authored
      * wrote man pages for all executable in bin/
      * also wrote man pages for the basic API headers and libraries
      a02ac9e1
  8. 10 May, 2017 2 commits