* following an internal discussion, we'd rather be sure to build
  everything from scratch in the runner, or version hell ensues

Merge commit '5a089419'

* empty slots did not exist at all, resulting in reads/writes causing
  bus errors, crash
* new Slot type Empty represents an empty slot
* slots in status configuration are filled with empty slots to fix the
  problem
* should not increase the size significantly; all empty slots are
  represented by the same ConstantRegister

Merge commit 'a9f329c5'

* zero-width io ports must be assigned, or compilation will fail
* fixed RegisterFileSpec accordingly
* updated to Scala 2.11.12

* re-used generic test from RegisterFile
* status configuration is generated by spec gens

Merge commit '8d79675d'

* Builder class main uses first argument as path to JSON config file
* IP Core is generated under ip/ hierarchy: each configuration hash is
  unique and can be used to cache products
* sbt clean removes this cache
* example.json contains an example configuration

* JsonSpec checks that roundtrips to and from Json preserve all data
* generators package contains ScalaCheck generators

* Status contains complete configuration, including kernel ids, memory
  slots and some basic sanity checking
* json package contains JSON SerDes functionality

* started with external format (JSON)
* noticed a problem: without Verilog module parameters Features cannot
  easily add capabilities etc.
* postponing the project until later

git-subtree-dir: packaging
git-subtree-mainline: 1846cfbe
git-subtree-split: 134b2f62

git-subtree-dir: axi
git-subtree-mainline: bea8ec99
git-subtree-split: b8f4c554

* width would not be propagated correctly
* fixed, also changed standard write test to increase by 1 from offset,
  making accidental correctness less likely

* addresses can be larger than 32bit, thus need to use Long
* in fact, having the upper-most bit 1 already gave problems
* fixed and updated all dependents

* while high, won't execute any actions, but reset its step counter