tapasco issueshttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues2019-01-15T16:48:33Zhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/4OOC: Fix problem with multiple top-levels2019-01-15T16:48:33ZJens KorinthOOC: Fix problem with multiple top-levelsOOC has problems if top-levels in the synthesis files are ambiguous. Try to find a better inspection to find the _right_ top-level.OOC has problems if top-levels in the synthesis files are ambiguous. Try to find a better inspection to find the _right_ top-level.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/14Features as Json2017-07-31T14:30:28ZJens KorinthFeatures as JsonExternalize Features as Json; automatically derive GUI + parsers (pure Map approach).
```
{
"Name": "SomeFeature",
"Description": "...",
"Bit": 4, // use in TPC status core
"Parameters": [
{
"Name": "BoolParam",
"K...Externalize Features as Json; automatically derive GUI + parsers (pure Map approach).
```
{
"Name": "SomeFeature",
"Description": "...",
"Bit": 4, // use in TPC status core
"Parameters": [
{
"Name": "BoolParam",
"Kind": "Bool"
},
{
"Name": "StringParam",
"Kind": "String"
},
{
"Name": "IntParam",
"Kind": "Int"
},
{
"Name": "Size",
"Kind": {
"Kind": "Range",
"From": 1024,
"To": 10240
}
},
{
"Name": "Mode",
"Kind": {
"Kind": "Enum",
"Values": ["A", "B", "C"]
}
}
]
}
```Jens KorinthJens Korinthhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/34Improved "Replay" Mode for DSE log2019-01-22T12:29:10ZJens KorinthImproved "Replay" Mode for DSE log`tapasco-logviewer` can already display logs, but it would be nice to have _timeline_, allowing to iteratively play back the events.`tapasco-logviewer` can already display logs, but it would be nice to have _timeline_, allowing to iteratively play back the events.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/35Tcl: Extract Subsystems2017-05-10T10:52:49ZJens KorinthTcl: Extract SubsystemsHave subsystem Tcl packages for generic subsystems, e.g., IRQ, Memory, PCIe. Each should create a pre-wired cell.Have subsystem Tcl packages for generic subsystems, e.g., IRQ, Memory, PCIe. Each should create a pre-wired cell.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/37Architecture per ThreadUnit2017-05-10T10:56:13ZJens KorinthArchitecture per ThreadUnitExtend TPC to use one Architecture per ThreadUnit; allows to combine different Architectures in one bitstream.Extend TPC to use one Architecture per ThreadUnit; allows to combine different Architectures in one bitstream.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/38Feature: OCM Memory2017-05-10T10:56:50ZJens KorinthFeature: OCM MemoryImplement an optional `Feature` to map OCM memory into address space. Parameters: size + offsetImplement an optional `Feature` to map OCM memory into address space. Parameters: size + offsethttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/39Partial Reconfiguration: Speed up synthesis2017-05-10T11:07:13ZJens KorinthPartial Reconfiguration: Speed up synthesisSynthesis of MIG core and PCIe takes very long time, significant amount of overall time for a run. Idea: Use a pre-synthesized design, ideally even placed and routed, for the Platform, and only add the dynamic ThreadPool afterwards.
Thi...Synthesis of MIG core and PCIe takes very long time, significant amount of overall time for a run. Idea: Use a pre-synthesized design, ideally even placed and routed, for the Platform, and only add the dynamic ThreadPool afterwards.
This approach could be achieved by wiring the Platform first, defining a general address mapping. Then synthesize, place and route the entire design and remove the Threadpool cell afterwards, replacing it with a black box. This design checkpoint could then be loaded and only the Threadpool would be added.
Since Design Checkpoints (DCPs) are specific to each Vivado version, there should be a command to initialize the DCPs once for each Platform.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/47LKM: man pages2019-01-22T15:53:04ZJens KorinthLKM: man pagesWrite `man` pages for device driver files.Write `man` pages for device driver files.Jens KorinthJens Korinthhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/49Tcl: Plugins passing arguments can lead to errors2018-07-01T15:07:35ZJens KorinthTcl: Plugins passing arguments can lead to errorsCheck what the arguments passing mechanism is good for; depending on the plugin order it can lead to problems in consecutive calls.Check what the arguments passing mechanism is good for; depending on the plugin order it can lead to problems in consecutive calls.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/83Boot: Replace Xilinx Root FS2019-01-22T15:57:40ZJens KorinthBoot: Replace Xilinx Root FSThe rootfs is currently repurposed from the official PyNQ image (publicly available). This has been convenient, but in the long term it would be preferable to build a custom rootfs from scratch with less baggage. Replace it with an Ubunt...The rootfs is currently repurposed from the official PyNQ image (publicly available). This has been convenient, but in the long term it would be preferable to build a custom rootfs from scratch with less baggage. Replace it with an Ubuntu rootfs, or buildroot.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/144Support PE-local memories in HLS2019-01-22T16:12:26ZJens KorinthSupport PE-local memories in HLSUse new PE-local memory support to enable a new kind of HLS port pattern: `localmem`. A Tcl script should automatically wrap the PE with BRAM and also make the BRAM accessible via secondary S-AXI. Using the new PE-local memories, it shou...Use new PE-local memory support to enable a new kind of HLS port pattern: `localmem`. A Tcl script should automatically wrap the PE with BRAM and also make the BRAM accessible via secondary S-AXI. Using the new PE-local memories, it should be possible to use BRAMs for HLS-based kernels, e.g., AES.Jens KorinthJens Korinthhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/163Implement tapasco_load_bitstream* functions2019-01-22T16:25:12ZJens KorinthImplement tapasco_load_bitstream* functionsSince its inception, the TaPaSCo/TPC API had two functions to load a new bitstream at runtime. This is meant to support complex use cases where an application switches between multiple bitstreams optimized for the specific stage of compu...Since its inception, the TaPaSCo/TPC API had two functions to load a new bitstream at runtime. This is meant to support complex use cases where an application switches between multiple bitstreams optimized for the specific stage of computation. This is arguably a useful thing and reasonably simple to implement on Zynq (given appropriate permissions on `/dev/xdevcfg`).
Is there a way to implement similar support on PCIe devices with reasonable effort? I suppose it would involve an ICAP as a platform component; however, I'm not sure if this works with non-partial bitstreams.