tapasco issueshttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues2019-01-22T16:15:25Zhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/154Allow direct view of the device memory on PCIe2019-01-22T16:15:25ZJaco HofmannAllow direct view of the device memory on PCIeThis can be implemented by using a sliding window and a second BAR. The Xilinx Core does not support this feature directly, though. Will use a little Bluespec Module that has one configuration register for the address offset which forwar...This can be implemented by using a sliding window and a second BAR. The Xilinx Core does not support this feature directly, though. Will use a little Bluespec Module that has one configuration register for the address offset which forwards the requests accordingly.Jaco HofmannJaco Hofmannhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/166Add PE to interrupt mapping in Status Core2019-01-22T16:27:20ZJaco HofmannAdd PE to interrupt mapping in Status CoreInterrupts are currently mapped iterative to the corresponding interrupt line. To increase flexibility the status core can store the mapping used.
Advantages are flexible mappings that enable the use of more than one interrupt per PE.Interrupts are currently mapped iterative to the corresponding interrupt line. To increase flexibility the status core can store the mapping used.
Advantages are flexible mappings that enable the use of more than one interrupt per PE.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/163Implement tapasco_load_bitstream* functions2019-01-22T16:25:12ZJens KorinthImplement tapasco_load_bitstream* functionsSince its inception, the TaPaSCo/TPC API had two functions to load a new bitstream at runtime. This is meant to support complex use cases where an application switches between multiple bitstreams optimized for the specific stage of compu...Since its inception, the TaPaSCo/TPC API had two functions to load a new bitstream at runtime. This is meant to support complex use cases where an application switches between multiple bitstreams optimized for the specific stage of computation. This is arguably a useful thing and reasonably simple to implement on Zynq (given appropriate permissions on `/dev/xdevcfg`).
Is there a way to implement similar support on PCIe devices with reasonable effort? I suppose it would involve an ICAP as a platform component; however, I'm not sure if this works with non-partial bitstreams.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/144Support PE-local memories in HLS2019-01-22T16:12:26ZJens KorinthSupport PE-local memories in HLSUse new PE-local memory support to enable a new kind of HLS port pattern: `localmem`. A Tcl script should automatically wrap the PE with BRAM and also make the BRAM accessible via secondary S-AXI. Using the new PE-local memories, it shou...Use new PE-local memory support to enable a new kind of HLS port pattern: `localmem`. A Tcl script should automatically wrap the PE with BRAM and also make the BRAM accessible via secondary S-AXI. Using the new PE-local memories, it should be possible to use BRAMs for HLS-based kernels, e.g., AES.Jens KorinthJens Korinthhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/103Make synthesis and implementation effort configurable2019-01-22T16:05:11ZJaco HofmannMake synthesis and implementation effort configurableThe default settings used at the moment are AlternateRoutability + Retiming for Synthesis and Explore + PHYS_OPT_DESIGN for Implementation. These settings could be considered to be very high effort. A switch could be added to let the use...The default settings used at the moment are AlternateRoutability + Retiming for Synthesis and Explore + PHYS_OPT_DESIGN for Implementation. These settings could be considered to be very high effort. A switch could be added to let the user decide between different "effort levels". For most synthesis runs it is not necessary to go with very high effort and the user might be happy about the much lower run-time.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/98Core Import: Add Synthesis and PnR parameters2019-01-22T16:00:31ZJens KorinthCore Import: Add Synthesis and PnR parametersIt would be useful to be able to control the parameters of synthesis and implementation directly from TaPaSCo. Maybe we should define modes, e.g.,
* **fastest** - lowest effort, minimal runtime
* **fast** - slightly slower, but stil...It would be useful to be able to control the parameters of synthesis and implementation directly from TaPaSCo. Maybe we should define modes, e.g.,
* **fastest** - lowest effort, minimal runtime
* **fast** - slightly slower, but still short runtime
* **normal** - default options
* **optimal** - slower, get as close to _real_ values as possible
* **aggressive_performance** - maximal optimization to performance
* **aggressive_area** - maximal optimization areahttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/93BlueDMA support in ZC7062019-06-26T06:28:06ZJens KorinthBlueDMA support in ZC706ZC706 could benefit from an DMA engine feature, which allows to use the on-board DDR banks. Port BlueDMA to Zynq and implement a Platform `Feature` for it.ZC706 could benefit from an DMA engine feature, which allows to use the on-board DDR banks. Port BlueDMA to Zynq and implement a Platform `Feature` for it.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/84Automate installation2017-06-01T12:20:38ZJens KorinthAutomate installationPlatform requires some additional bring-up, e.g., customization and installation of udev rules. Should have a script that automates the process and can be run once as `sudo`.Platform requires some additional bring-up, e.g., customization and installation of udev rules. Should have a script that automates the process and can be run once as `sudo`.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/66Improve LogTrackingPanel2019-01-22T15:56:36ZJens KorinthImprove LogTrackingPanelThe `LogTrackingPanel` is not yet as useful as it could be. Ideas:
* [ ] highlight lines from different files in different colors
* [ ] prepend logfile name (probably unreadable)
* [ ] implement search field for free text / regex search...The `LogTrackingPanel` is not yet as useful as it could be. Ideas:
* [ ] highlight lines from different files in different colors
* [ ] prepend logfile name (probably unreadable)
* [ ] implement search field for free text / regex searching
* [ ] enable quick filters: ERROR, CRITICAL, WARNINGhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/64DSE: Abort runs after PlacerErrors2019-01-22T15:54:09ZJens KorinthDSE: Abort runs after PlacerErrorsWhen a run results in a `PlacerError` it is extremely unlikely that any run with the same (or a larger) `Composition` will succeed. Runs are already pruned after the batch finishes, but it could be useful to be even more aggressive and a...When a run results in a `PlacerError` it is extremely unlikely that any run with the same (or a larger) `Composition` will succeed. Runs are already pruned after the batch finishes, but it could be useful to be even more aggressive and abort runs in the current batch, if they would be pruned. This could speed up batches and increase convergence speed.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/40Feature: BRAM2019-01-22T15:51:13ZJens KorinthFeature: BRAMImplement a `Feature` to generate a chunk of BRAM and map it into address space for small allocations. Parameters: size + offsetImplement a `Feature` to generate a chunk of BRAM and map it into address space for small allocations. Parameters: size + offsethttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/38Feature: OCM Memory2017-05-10T10:56:50ZJens KorinthFeature: OCM MemoryImplement an optional `Feature` to map OCM memory into address space. Parameters: size + offsetImplement an optional `Feature` to map OCM memory into address space. Parameters: size + offsethttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/37Architecture per ThreadUnit2017-05-10T10:56:13ZJens KorinthArchitecture per ThreadUnitExtend TPC to use one Architecture per ThreadUnit; allows to combine different Architectures in one bitstream.Extend TPC to use one Architecture per ThreadUnit; allows to combine different Architectures in one bitstream.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/36Infrastructure: Tapasco Status Core2019-01-22T15:51:46ZJens KorinthInfrastructure: Tapasco Status CoreUpgrade TPC Status Core to incorporate performance counters. Extend libtpc to gather statistics after the run, possibly writing to a file using a environment variable.
* [x] Version Register: Vivado
* [x] Version Register: TaPaSCo
* [ ]...Upgrade TPC Status Core to incorporate performance counters. Extend libtpc to gather statistics after the run, possibly writing to a file using a environment variable.
* [x] Version Register: Vivado
* [x] Version Register: TaPaSCo
* [ ] PerfCounter: # of IRQs/slot
* [ ] PerfCounter: busy cycles/slot
* [ ] PerfCounter: IRQ cycles (waiting for ACK)/slothttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/34Improved "Replay" Mode for DSE log2019-01-22T12:29:10ZJens KorinthImproved "Replay" Mode for DSE log`tapasco-logviewer` can already display logs, but it would be nice to have _timeline_, allowing to iteratively play back the events.`tapasco-logviewer` can already display logs, but it would be nice to have _timeline_, allowing to iteratively play back the events.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/33Add "keep all runs" to `DesignSpaceExplorationJob`2019-01-22T12:27:35ZJens KorinthAdd "keep all runs" to `DesignSpaceExplorationJob`Might be useful for debugging.Might be useful for debugging.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/31Implement lock-free hash table in libtpc/libplatform2019-01-15T16:55:01ZJens KorinthImplement lock-free hash table in libtpc/libplatformhttps://github.com/mintomic/samples
Could be used to remove fixed number of slots in overall `Architecture`.https://github.com/mintomic/samples
Could be used to remove fixed number of slots in overall `Architecture`.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/29Tcl: Writes[T]2019-01-15T16:53:41ZJens KorinthTcl: Writes[T]Implement Tcl serialization support like Json: Define package `tcl` with `Writes[T]`. Default types should include `Writes[(String, Int)]` (which writes `set name 42`) and similar.
_Interface_
```
trait Writes[T] {
def writes(t: T): ...Implement Tcl serialization support like Json: Define package `tcl` with `Writes[T]`. Default types should include `Writes[(String, Int)]` (which writes `set name 42`) and similar.
_Interface_
```
trait Writes[T] {
def writes(t: T): String
}
object Tcl {
def toTcl[T](t: T)(implicit w: Writes[T]): String = w.writes(t)
}
```https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/28Asynchronous Memory Transfers2019-01-15T16:51:39ZJens KorinthAsynchronous Memory TransfersSimilar to asynchronous job launches: Check if asynchronous memory transfers could be useful. I guess probably not so much, because we need to wait for the transfers to finish, before we can launch the job in anycase - worst/ideal case w...Similar to asynchronous job launches: Check if asynchronous memory transfers could be useful. I guess probably not so much, because we need to wait for the transfers to finish, before we can launch the job in anycase - worst/ideal case would be that the job starts immediately and data must be available. It would be possible to add mem barriers based on the job struct, but I do not think this would be worth the effort.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/14Features as Json2017-07-31T14:30:28ZJens KorinthFeatures as JsonExternalize Features as Json; automatically derive GUI + parsers (pure Map approach).
```
{
"Name": "SomeFeature",
"Description": "...",
"Bit": 4, // use in TPC status core
"Parameters": [
{
"Name": "BoolParam",
"K...Externalize Features as Json; automatically derive GUI + parsers (pure Map approach).
```
{
"Name": "SomeFeature",
"Description": "...",
"Bit": 4, // use in TPC status core
"Parameters": [
{
"Name": "BoolParam",
"Kind": "Bool"
},
{
"Name": "StringParam",
"Kind": "String"
},
{
"Name": "IntParam",
"Kind": "Int"
},
{
"Name": "Size",
"Kind": {
"Kind": "Range",
"From": 1024,
"To": 10240
}
},
{
"Name": "Mode",
"Kind": {
"Kind": "Enum",
"Values": ["A", "B", "C"]
}
}
]
}
```Jens KorinthJens Korinth