tapasco issueshttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues2017-05-10T10:56:50Zhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/38Feature: OCM Memory2017-05-10T10:56:50ZJens KorinthFeature: OCM MemoryImplement an optional `Feature` to map OCM memory into address space. Parameters: size + offsetImplement an optional `Feature` to map OCM memory into address space. Parameters: size + offsethttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/14Features as Json2017-07-31T14:30:28ZJens KorinthFeatures as JsonExternalize Features as Json; automatically derive GUI + parsers (pure Map approach).
```
{
"Name": "SomeFeature",
"Description": "...",
"Bit": 4, // use in TPC status core
"Parameters": [
{
"Name": "BoolParam",
"K...Externalize Features as Json; automatically derive GUI + parsers (pure Map approach).
```
{
"Name": "SomeFeature",
"Description": "...",
"Bit": 4, // use in TPC status core
"Parameters": [
{
"Name": "BoolParam",
"Kind": "Bool"
},
{
"Name": "StringParam",
"Kind": "String"
},
{
"Name": "IntParam",
"Kind": "Int"
},
{
"Name": "Size",
"Kind": {
"Kind": "Range",
"From": 1024,
"To": 10240
}
},
{
"Name": "Mode",
"Kind": {
"Kind": "Enum",
"Values": ["A", "B", "C"]
}
}
]
}
```Jens KorinthJens Korinthhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/41Fix FlexLM status queries2019-01-22T15:51:30ZJens KorinthFix FlexLM status queries* [ ] Fix/check licence requirements of `Task` instances
* [ ] Fix/check `lmstat` support* [ ] Fix/check licence requirements of `Task` instances
* [ ] Fix/check `lmstat` supporthttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/15HLS: Move Synthesizer Implementation into kernel description2017-05-10T09:12:06ZJens KorinthHLS: Move Synthesizer Implementation into kernel descriptionThe `kernel.description` / `kernel.json` should contain the HLS implementation; the source files determine which `HighLevelSynthesizer` must be used.The `kernel.description` / `kernel.json` should contain the HLS implementation; the source files determine which `HighLevelSynthesizer` must be used.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/30Implement HLS kernels2017-05-10T10:45:22ZJens KorinthImplement HLS kernels* [x] Countdown / Timer
* [x] arrayinit
* [x] arrayadd
* [x] arrayupdate
* [ ] varrayinit
* [ ] varrayadd
* [ ] varraysum
* [ ] vectoradddot
* [ ] sobel
* [ ] mandelbrot
* [ ] sudoku
* [x] rot13
* [ ] warraw (dep collision check)
* [ ] f...* [x] Countdown / Timer
* [x] arrayinit
* [x] arrayadd
* [x] arrayupdate
* [ ] varrayinit
* [ ] varrayadd
* [ ] varraysum
* [ ] vectoradddot
* [ ] sobel
* [ ] mandelbrot
* [ ] sudoku
* [x] rot13
* [ ] warraw (dep collision check)
* [ ] fir
* [ ] n-queenshttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/31Implement lock-free hash table in libtpc/libplatform2019-01-15T16:55:01ZJens KorinthImplement lock-free hash table in libtpc/libplatformhttps://github.com/mintomic/samples
Could be used to remove fixed number of slots in overall `Architecture`.https://github.com/mintomic/samples
Could be used to remove fixed number of slots in overall `Architecture`.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/11Implement Software Environment singleton2017-12-28T14:43:21ZJens KorinthImplement Software Environment singletonNeed a central place for all external software tools and versions. E.g., Vivado, Vivado HLS, FlexLM, etc.
Implement methods to report software environment (and compute versions only once at start).Need a central place for all external software tools and versions. E.g., Vivado, Vivado HLS, FlexLM, etc.
Implement methods to report software environment (and compute versions only once at start).Jens KorinthJens Korinthhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/163Implement tapasco_load_bitstream* functions2019-01-22T16:25:12ZJens KorinthImplement tapasco_load_bitstream* functionsSince its inception, the TaPaSCo/TPC API had two functions to load a new bitstream at runtime. This is meant to support complex use cases where an application switches between multiple bitstreams optimized for the specific stage of compu...Since its inception, the TaPaSCo/TPC API had two functions to load a new bitstream at runtime. This is meant to support complex use cases where an application switches between multiple bitstreams optimized for the specific stage of computation. This is arguably a useful thing and reasonably simple to implement on Zynq (given appropriate permissions on `/dev/xdevcfg`).
Is there a way to implement similar support on PCIe devices with reasonable effort? I suppose it would involve an ICAP as a platform component; however, I'm not sure if this works with non-partial bitstreams.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/66Improve LogTrackingPanel2019-01-22T15:56:36ZJens KorinthImprove LogTrackingPanelThe `LogTrackingPanel` is not yet as useful as it could be. Ideas:
* [ ] highlight lines from different files in different colors
* [ ] prepend logfile name (probably unreadable)
* [ ] implement search field for free text / regex search...The `LogTrackingPanel` is not yet as useful as it could be. Ideas:
* [ ] highlight lines from different files in different colors
* [ ] prepend logfile name (probably unreadable)
* [ ] implement search field for free text / regex searching
* [ ] enable quick filters: ERROR, CRITICAL, WARNINGhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/97Improve SLURM job names2019-01-22T15:59:24ZJens KorinthImprove SLURM job namesSLURM compose jobs currently have names like `compose-0xd4c6a941-axi4mm-pynq-180.00`. Use new naming scheme instead to show full configuration. Possibly also change the comment to the working directory.SLURM compose jobs currently have names like `compose-0xd4c6a941-axi4mm-pynq-180.00`. Use new naming scheme instead to show full configuration. Possibly also change the comment to the working directory.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/34Improved "Replay" Mode for DSE log2019-01-22T12:29:10ZJens KorinthImproved "Replay" Mode for DSE log`tapasco-logviewer` can already display logs, but it would be nice to have _timeline_, allowing to iteratively play back the events.`tapasco-logviewer` can already display logs, but it would be nice to have _timeline_, allowing to iteratively play back the events.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/36Infrastructure: Tapasco Status Core2019-01-22T15:51:46ZJens KorinthInfrastructure: Tapasco Status CoreUpgrade TPC Status Core to incorporate performance counters. Extend libtpc to gather statistics after the run, possibly writing to a file using a environment variable.
* [x] Version Register: Vivado
* [x] Version Register: TaPaSCo
* [ ]...Upgrade TPC Status Core to incorporate performance counters. Extend libtpc to gather statistics after the run, possibly writing to a file using a environment variable.
* [x] Version Register: Vivado
* [x] Version Register: TaPaSCo
* [ ] PerfCounter: # of IRQs/slot
* [ ] PerfCounter: busy cycles/slot
* [ ] PerfCounter: IRQ cycles (waiting for ACK)/slothttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/167Interrupts go missing sometimes2020-04-03T11:43:05ZJaco HofmannInterrupts go missing sometimesThe PCIe MSIx interrupts coming from the DMA engine are received properly by the interrupt controller. The interrupt controller properly issues a AXI write request to the correct address in host memory. The PCIe AXI bridge does ACK the t...The PCIe MSIx interrupts coming from the DMA engine are received properly by the interrupt controller. The interrupt controller properly issues a AXI write request to the correct address in host memory. The PCIe AXI bridge does ACK the transfer and Bresp is OKAY. However, sometimes the interrupts do not reach the host for some reason. This can be confirmed checking /proc/interrupt.
This might be related to the interrupt controller taking too long. However, the DMA interrupt simply increases a value and schedules the userspace. This should not take too long.
Another alternative is that the PCIe bridge looses data when it is under heavy pressure.
For now as a quick fix I will try to disable a certain interrupt whenever the interrupt has just fired and see if that fixes the problem at the cost of latency. If that doesn't help maybe there is some possibility to remove protocol converters in between the interrupt handler and the PCIe bridge to avoid problems with those.
Overall no clear indication to what might go wrong as long as we don't have the hardware to debug right on the PCIe bus.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/169Investigate Logic Utilization reports2020-04-03T12:24:05ZCarsten HeinzInvestigate Logic Utilization reportsIt seems that the utilization report does not make sense for BRAM in the user logic. Sometimes utilization for user logic is higher than for the complete system logic.It seems that the utilization report does not make sense for BRAM in the user logic. Sometimes utilization for user logic is higher than for the complete system logic.Carsten HeinzCarsten Heinzhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/162LED feature on VC709 crashes Vivado2020-03-04T22:47:08ZJens KorinthLED feature on VC709 crashes VivadoEnabling the LED feature on VC709 compositions reproducibly crashes Vivado. While this is certainly a Vivado bug, we should investigate a workaround.Enabling the LED feature on VC709 compositions reproducibly crashes Vivado. While this is certainly a Vivado bug, we should investigate a workaround.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/47LKM: man pages2019-01-22T15:53:04ZJens KorinthLKM: man pagesWrite `man` pages for device driver files.Write `man` pages for device driver files.Jens KorinthJens Korinthhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/160Local memory slots not considered in area estimation, causing DSE to fail2019-12-18T09:54:11ZJens KorinthLocal memory slots not considered in area estimation, causing DSE to failIf a PE has local memories (or more than one slave interface, for that matter), DSE will still try to build more instances than will fit in the current 128 slots limit. There are several possible solutions:
1. Have separate enumerati...If a PE has local memories (or more than one slave interface, for that matter), DSE will still try to build more instances than will fit in the current 128 slots limit. There are several possible solutions:
1. Have separate enumeration for memory slots (affects status core, `platform_info` and potentially requires a more sophisticated way to determine accessibility for each PE).
2. Fix the algorithms to account for each slave interface instead of just assuming one.
Need to think about it some more; I guess, each PE will always have exactly _one_ control slave interface. We could require a naming convention to identify it if more than one candidate is present on a PE, e.g., `S_AXI_CTRL` or similar. All other slave interfaces could be assigned a base address from a different pool, e.g., using the upper 64 base addresses already reserved for platform addresses. But we'd have to come up with some O(k) or at least O(n) scheme to find the base addresses of all slaves on a PE. :thinking:2018.2https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/7Make new tutorial video series2017-12-28T14:41:30ZJens KorinthMake new tutorial video seriesStart new video tutorials: Overview, Installation, Example, Detail How-Tos.
Ideas for series:
* [ ] Overview
* [ ] APIs
* [ ] HLS C/C++ Kernel (rot13?)
* [ ] Compose
* [ ] Design Space Exploration
* [ ] Multi-Platform Support
...Start new video tutorials: Overview, Installation, Example, Detail How-Tos.
Ideas for series:
* [ ] Overview
* [ ] APIs
* [ ] HLS C/C++ Kernel (rot13?)
* [ ] Compose
* [ ] Design Space Exploration
* [ ] Multi-Platform Support
* [ ] VC709
* [ ] ZC706
* [ ] ZedBoard
* [ ] PyNQ
* [ ] Command Line
* [ ] Helper ToolsJens KorinthJens Korinthhttps://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/103Make synthesis and implementation effort configurable2019-01-22T16:05:11ZJaco HofmannMake synthesis and implementation effort configurableThe default settings used at the moment are AlternateRoutability + Retiming for Synthesis and Explore + PHYS_OPT_DESIGN for Implementation. These settings could be considered to be very high effort. A switch could be added to let the use...The default settings used at the moment are AlternateRoutability + Retiming for Synthesis and Explore + PHYS_OPT_DESIGN for Implementation. These settings could be considered to be very high effort. A switch could be added to let the user decide between different "effort levels". For most synthesis runs it is not necessary to go with very high effort and the user might be happy about the much lower run-time.https://git.esa.informatik.tu-darmstadt.de/tapasco/tapasco/-/issues/4OOC: Fix problem with multiple top-levels2019-01-15T16:48:33ZJens KorinthOOC: Fix problem with multiple top-levelsOOC has problems if top-levels in the synthesis files are ambiguous. Try to find a better inspection to find the _right_ top-level.OOC has problems if top-levels in the synthesis files are ambiguous. Try to find a better inspection to find the _right_ top-level.