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Zedboard Synthesis fails for 2017.3 and 2017.4

Job #808 failed for c830c899:

[[32m10:39:24 <Thread-75: VivadoComposer>[0;39m [34mINFO[0;39m] WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'NUM_OUT_CLKS' from '1' to '3' has been ignored for IP 'clocks_and_resets/clk_wiz'
[[32m10:39:24 <Thread-75: VivadoComposer>[0;39m [34mINFO[0;39m] ERROR: [IP_Flow 19-3461] Value 'sys_diff_clock' is out of the range for parameter 'CLK IN1 BOARD INTERFACE(CLK_IN1_BOARD_INTERFACE)' for BD Cell 'clocks_and_resets/clk_wiz' . Valid values are - Custom, sys_clock
[[32m10:39:24 <Thread-75: VivadoComposer>[0;39m [34mINFO[0;39m] ERROR: [BD 41-245] set_property error - Value 'sys_diff_clock' is out of the range for parameter 'CLK IN1 BOARD INTERFACE(CLK_IN1_BOARD_INTERFACE)' for BD Cell 'clocks_and_resets/clk_wiz' . Valid values are - Custom, sys_clock
[[32m10:39:24 <Thread-75: VivadoComposer>[0;39m [34mINFO[0;39m] Customization errors found on 'clocks_and_resets/clk_wiz'. Restoring to previous valid configuration.
[[32m10:39:24 <Thread-75: VivadoComposer>[0;39m [34mINFO[0;39m] 
[[32m10:39:24 <Thread-75: VivadoComposer>[0;39m [34mINFO[0;39m]   sys_diff_clock is not supported, trying sys_clock instead
[[32m10:39:24 <Thread-75: VivadoComposer>[0;39m [34mINFO[0;39m] WARNING: [BD 5-236] No ports matched 'get_bd_ports /sys_clock'
[[32m10:39:24 <Thread-75: VivadoComposer>[0;39m [34mINFO[0;39m]   clk_wiz: /clocks_and_resets/clk_wiz, cport: /clocks_and_resets/clk_wiz/clk_in1