diff --git a/common/ip/BlueDMA/component.xml b/common/ip/BlueDMA/component.xml index 26eb269e35cc8041586c501684605c5fb67154a6..6199652011683e86963299c8b380d2f2cbafd9d0 100644 --- a/common/ip/BlueDMA/component.xml +++ b/common/ip/BlueDMA/component.xml @@ -528,6 +528,20 @@ + + + SUPPORTS_NARROW_BURST + 0 + + + NUM_READ_OUTSTANDING + 8 + + + NUM_WRITE_OUTSTANDING + 8 + + m64_axi @@ -890,6 +904,20 @@ + + + SUPPORTS_NARROW_BURST + 0 + + + NUM_READ_OUTSTANDING + 8 + + + NUM_WRITE_OUTSTANDING + 8 + + s_axi_aresetn @@ -1096,7 +1124,7 @@ viewChecksum - ded3be7f + 6dca3063 @@ -1112,7 +1140,7 @@ viewChecksum - ded3be7f + 6dca3063 @@ -2983,7 +3011,7 @@ src/mkBlueDMAVivado.v verilogSource - CHECKSUM_578878b6 + CHECKSUM_031e6e27 @@ -3055,17 +3083,17 @@ BlueDMA package_project 1 - 2017-07-06T11:01:37Z + 2017-07-07T08:39:29Z 2016.4 - + - + diff --git a/common/ip/BlueDMA/src/mkBlueDMA.v b/common/ip/BlueDMA/src/mkBlueDMA.v index 10271478610bdb16ff7098374d74d040c64255bb..880a2d49cfc49d06c0e79007d168a900f815ed5a 100644 --- a/common/ip/BlueDMA/src/mkBlueDMA.v +++ b/common/ip/BlueDMA/src/mkBlueDMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07) // -// On Thu Jul 6 13:00:48 CEST 2017 +// On Fri Jul 7 10:38:49 CEST 2017 // // // Ports: @@ -26,7 +26,7 @@ // pcie_rd_arqos O 4 // pcie_rd_arregion O 4 // pcie_rd_aruser O 1 -// pcie_rd_rready O 1 +// pcie_rd_rready O 1 reg // pcie_wr_awvalid O 1 reg // pcie_wr_awid O 1 // pcie_wr_awaddr O 64 @@ -39,7 +39,7 @@ // pcie_wr_awqos O 4 // pcie_wr_awregion O 4 // pcie_wr_awuser O 1 -// pcie_wr_wvalid O 1 +// pcie_wr_wvalid O 1 reg // pcie_wr_wdata O 256 // pcie_wr_wstrb O 32 // pcie_wr_wlast O 1 @@ -57,7 +57,7 @@ // fpga_rd_arqos O 4 // fpga_rd_arregion O 4 // fpga_rd_aruser O 1 -// fpga_rd_rready O 1 +// fpga_rd_rready O 1 reg // fpga_wr_awvalid O 1 reg // fpga_wr_awid O 1 // fpga_wr_awaddr O 64 @@ -70,7 +70,7 @@ // fpga_wr_awqos O 4 // fpga_wr_awregion O 4 // fpga_wr_awuser O 1 -// fpga_wr_wvalid O 1 +// fpga_wr_wvalid O 1 reg // fpga_wr_wdata O 512 // fpga_wr_wstrb O 64 // fpga_wr_wlast O 1 @@ -96,11 +96,11 @@ // S_AXI_bready I 1 // pcie_rd_arready I 1 // pcie_rd_rvalid I 1 -// pcie_rd_rid I 1 -// pcie_rd_rdata I 256 -// pcie_rd_rresp I 2 -// pcie_rd_rlast I 1 -// pcie_rd_ruser I 1 +// pcie_rd_rid I 1 reg +// pcie_rd_rdata I 256 reg +// pcie_rd_rresp I 2 reg +// pcie_rd_rlast I 1 reg +// pcie_rd_ruser I 1 reg // pcie_wr_awready I 1 // pcie_wr_wready I 1 // pcie_wr_bvalid I 1 @@ -109,11 +109,11 @@ // pcie_wr_buser I 1 reg // fpga_rd_arready I 1 // fpga_rd_rvalid I 1 -// fpga_rd_rid I 1 -// fpga_rd_rdata I 512 -// fpga_rd_rresp I 2 -// fpga_rd_rlast I 1 -// fpga_rd_ruser I 1 +// fpga_rd_rid I 1 reg +// fpga_rd_rdata I 512 reg +// fpga_rd_rresp I 2 reg +// fpga_rd_rlast I 1 reg +// fpga_rd_ruser I 1 reg // fpga_wr_awready I 1 // fpga_wr_wready I 1 // fpga_wr_bvalid I 1 @@ -730,22 +730,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_master_wr_wawcache$wget, m_pcie_rd_master_rd_warcache$wget, m_pcie_wr_master_wr_wawcache$wget; - wire [578 : 0] m_fpga_wr_master_wr_in_data_1_rv$port1__read, - m_fpga_wr_master_wr_in_data_1_rv$port1__write_1, - m_fpga_wr_master_wr_in_data_1_rv$port2__read; - wire [517 : 0] m_fpga_rd_master_rd_out_1_rv$port1__read, - m_fpga_rd_master_rd_out_1_rv$port1__write_1, - m_fpga_rd_master_rd_out_1_rv$port2__read; wire [516 : 0] m_fpga_rd_master_rd_rinpkg$wget; - wire [512 : 0] m_fpga_rd_outgoingBuffer_rv$port1__read, - m_fpga_rd_outgoingBuffer_rv$port1__write_1, - m_fpga_rd_outgoingBuffer_rv$port2__read, - m_fpga_wr_incomingBuffer_rv$port1__read, - m_fpga_wr_incomingBuffer_rv$port1__write_1, - m_fpga_wr_incomingBuffer_rv$port2__read, - writeConverter_dataSync_rv$port1__read, - writeConverter_dataSync_rv$port1__write_1, - writeConverter_dataSync_rv$port2__read; wire [511 : 0] byteAlignerReader_buffer$port0__write_1, byteAlignerReader_buffer$port1__read, byteAlignerReader_buffer$port1__write_1, @@ -754,25 +739,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_buffer$port1__read, byteAlignerWriter_buffer$port1__write_1, byteAlignerWriter_buffer$port2__read; - wire [290 : 0] m_pcie_wr_master_wr_in_data_1_rv$port1__read, - m_pcie_wr_master_wr_in_data_1_rv$port1__write_1, - m_pcie_wr_master_wr_in_data_1_rv$port2__read; - wire [261 : 0] m_pcie_rd_master_rd_out_1_rv$port1__read, - m_pcie_rd_master_rd_out_1_rv$port1__write_1, - m_pcie_rd_master_rd_out_1_rv$port2__read; wire [260 : 0] m_pcie_rd_master_rd_rinpkg$wget; - wire [256 : 0] byteAlignerReader_incoming_rv$port1__read, - byteAlignerReader_outgoing_rv$port1__write_1, - byteAlignerReader_outgoing_rv$port2__read, - byteAlignerWriter_incoming_rv$port1__read, - byteAlignerWriter_outgoing_rv$port1__write_1, - byteAlignerWriter_outgoing_rv$port2__read, - m_pcie_rd_outgoingBuffer_rv$port1__read, - m_pcie_rd_outgoingBuffer_rv$port1__write_1, - m_pcie_rd_outgoingBuffer_rv$port2__read, - m_pcie_wr_incomingBuffer_rv$port1__read, - m_pcie_wr_incomingBuffer_rv$port1__write_1, - m_pcie_wr_incomingBuffer_rv$port2__read; wire [192 : 0] readIn_rv$port1__read, readIn_rv$port1__write_1, readIn_rv$port2__read, @@ -795,23 +762,13 @@ module mkBlueDMA(CLK_m32_axi_aclk, wire byteAlignerReader_buffer$EN_port0__write, byteAlignerReader_bytes_left_in_buffer$EN_port0__write, byteAlignerReader_fetchedDatum$EN_port0__write, - byteAlignerReader_fetchedDatum$EN_port1__write, byteAlignerReader_fetchedDatum$port1__read, byteAlignerReader_fetchedDatum$port2__read, - byteAlignerReader_outgoing_rv$EN_port1__write, byteAlignerWriter_buffer$EN_port0__write, byteAlignerWriter_bytes_left_in_buffer$EN_port0__write, byteAlignerWriter_fetchedDatum$EN_port0__write, - byteAlignerWriter_fetchedDatum$EN_port1__write, byteAlignerWriter_fetchedDatum$port1__read, byteAlignerWriter_fetchedDatum$port2__read, - byteAlignerWriter_outgoing_rv$EN_port1__write, - m_fpga_rd_master_rd_out_1_rv$EN_port1__write, - m_fpga_rd_outgoingBuffer_rv$EN_port0__write, - m_fpga_wr_incomingBuffer_rv$EN_port1__write, - m_fpga_wr_master_wr_in_data_1_rv$EN_port0__write, - m_pcie_rd_master_rd_out_1_rv$EN_port1__write, - m_pcie_wr_master_wr_in_data_1_rv$EN_port0__write, readConverter_bufferEmpty$EN_port0__write, readConverter_bufferEmpty$EN_port1__write, readConverter_bufferEmpty$port1__read, @@ -823,8 +780,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, s_config_writeSlave_addrIn_rv$EN_port1__write, s_config_writeSlave_dataIn_rv$EN_port0__write, s_config_writeSlave_dataIn_rv$EN_port1__write, - writeConverter_dataSync_rv$EN_port0__write, - writeConverter_dataSync_rv$EN_port1__write, writeIn_rv$EN_port1__write; // register byteAlignerReader_buffer @@ -861,16 +816,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, reg byteAlignerReader_fetchedDatum; wire byteAlignerReader_fetchedDatum$D_IN, byteAlignerReader_fetchedDatum$EN; - // register byteAlignerReader_incoming_rv - reg [256 : 0] byteAlignerReader_incoming_rv; - wire [256 : 0] byteAlignerReader_incoming_rv$D_IN; - wire byteAlignerReader_incoming_rv$EN; - - // register byteAlignerReader_outgoing_rv - reg [256 : 0] byteAlignerReader_outgoing_rv; - wire [256 : 0] byteAlignerReader_outgoing_rv$D_IN; - wire byteAlignerReader_outgoing_rv$EN; - // register byteAlignerWriter_buffer reg [511 : 0] byteAlignerWriter_buffer; wire [511 : 0] byteAlignerWriter_buffer$D_IN; @@ -905,16 +850,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, reg byteAlignerWriter_fetchedDatum; wire byteAlignerWriter_fetchedDatum$D_IN, byteAlignerWriter_fetchedDatum$EN; - // register byteAlignerWriter_incoming_rv - reg [256 : 0] byteAlignerWriter_incoming_rv; - wire [256 : 0] byteAlignerWriter_incoming_rv$D_IN; - wire byteAlignerWriter_incoming_rv$EN; - - // register byteAlignerWriter_outgoing_rv - reg [256 : 0] byteAlignerWriter_outgoing_rv; - wire [256 : 0] byteAlignerWriter_outgoing_rv$D_IN; - wire byteAlignerWriter_outgoing_rv$EN; - // register doneInterruptReg reg doneInterruptReg; wire doneInterruptReg$D_IN, doneInterruptReg$EN; @@ -958,16 +893,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, wire [31 : 0] m_fpga_rd_lastPut$D_IN; wire m_fpga_rd_lastPut$EN; - // register m_fpga_rd_master_rd_out_1_rv - reg [517 : 0] m_fpga_rd_master_rd_out_1_rv; - wire [517 : 0] m_fpga_rd_master_rd_out_1_rv$D_IN; - wire m_fpga_rd_master_rd_out_1_rv$EN; - - // register m_fpga_rd_outgoingBuffer_rv - reg [512 : 0] m_fpga_rd_outgoingBuffer_rv; - wire [512 : 0] m_fpga_rd_outgoingBuffer_rv$D_IN; - wire m_fpga_rd_outgoingBuffer_rv$EN; - // register m_fpga_rd_putDelay reg [31 : 0] m_fpga_rd_putDelay; wire [31 : 0] m_fpga_rd_putDelay$D_IN; @@ -998,21 +923,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, wire [31 : 0] m_fpga_wr_clkCntr$D_IN; wire m_fpga_wr_clkCntr$EN; - // register m_fpga_wr_incomingBuffer_rv - reg [512 : 0] m_fpga_wr_incomingBuffer_rv; - wire [512 : 0] m_fpga_wr_incomingBuffer_rv$D_IN; - wire m_fpga_wr_incomingBuffer_rv$EN; - // register m_fpga_wr_lastPut reg [31 : 0] m_fpga_wr_lastPut; wire [31 : 0] m_fpga_wr_lastPut$D_IN; wire m_fpga_wr_lastPut$EN; - // register m_fpga_wr_master_wr_in_data_1_rv - reg [578 : 0] m_fpga_wr_master_wr_in_data_1_rv; - wire [578 : 0] m_fpga_wr_master_wr_in_data_1_rv$D_IN; - wire m_fpga_wr_master_wr_in_data_1_rv$EN; - // register m_fpga_wr_putDelay reg [31 : 0] m_fpga_wr_putDelay; wire [31 : 0] m_fpga_wr_putDelay$D_IN; @@ -1043,16 +958,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, wire [31 : 0] m_pcie_rd_lastPut$D_IN; wire m_pcie_rd_lastPut$EN; - // register m_pcie_rd_master_rd_out_1_rv - reg [261 : 0] m_pcie_rd_master_rd_out_1_rv; - wire [261 : 0] m_pcie_rd_master_rd_out_1_rv$D_IN; - wire m_pcie_rd_master_rd_out_1_rv$EN; - - // register m_pcie_rd_outgoingBuffer_rv - reg [256 : 0] m_pcie_rd_outgoingBuffer_rv; - wire [256 : 0] m_pcie_rd_outgoingBuffer_rv$D_IN; - wire m_pcie_rd_outgoingBuffer_rv$EN; - // register m_pcie_rd_putDelay reg [31 : 0] m_pcie_rd_putDelay; wire [31 : 0] m_pcie_rd_putDelay$D_IN; @@ -1083,21 +988,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, wire [31 : 0] m_pcie_wr_clkCntr$D_IN; wire m_pcie_wr_clkCntr$EN; - // register m_pcie_wr_incomingBuffer_rv - reg [256 : 0] m_pcie_wr_incomingBuffer_rv; - wire [256 : 0] m_pcie_wr_incomingBuffer_rv$D_IN; - wire m_pcie_wr_incomingBuffer_rv$EN; - // register m_pcie_wr_lastPut reg [31 : 0] m_pcie_wr_lastPut; wire [31 : 0] m_pcie_wr_lastPut$D_IN; wire m_pcie_wr_lastPut$EN; - // register m_pcie_wr_master_wr_in_data_1_rv - reg [290 : 0] m_pcie_wr_master_wr_in_data_1_rv; - wire [290 : 0] m_pcie_wr_master_wr_in_data_1_rv$D_IN; - wire m_pcie_wr_master_wr_in_data_1_rv$EN; - // register m_pcie_wr_putDelay reg [31 : 0] m_pcie_wr_putDelay; wire [31 : 0] m_pcie_wr_putDelay$D_IN; @@ -1188,11 +1083,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, wire [63 : 0] writeConverter_byteCntr$D_IN; wire writeConverter_byteCntr$EN; - // register writeConverter_dataSync_rv - reg [512 : 0] writeConverter_dataSync_rv; - wire [512 : 0] writeConverter_dataSync_rv$D_IN; - wire writeConverter_dataSync_rv$EN; - // register writeConverter_wordInCntr reg [1 : 0] writeConverter_wordInCntr; wire [1 : 0] writeConverter_wordInCntr$D_IN; @@ -1220,6 +1110,21 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerReader_addr_ff$dEMPTY_N, byteAlignerReader_addr_ff$sENQ; + // ports of submodule byteAlignerReader_incoming + wire [255 : 0] byteAlignerReader_incoming$D_IN, + byteAlignerReader_incoming$D_OUT; + wire byteAlignerReader_incoming$CLR, + byteAlignerReader_incoming$DEQ, + byteAlignerReader_incoming$EMPTY_N, + byteAlignerReader_incoming$ENQ; + + // ports of submodule byteAlignerReader_outgoing + wire [255 : 0] byteAlignerReader_outgoing$D_IN; + wire byteAlignerReader_outgoing$CLR, + byteAlignerReader_outgoing$DEQ, + byteAlignerReader_outgoing$ENQ, + byteAlignerReader_outgoing$FULL_N; + // ports of submodule byteAlignerWriter_addr_ff wire [191 : 0] byteAlignerWriter_addr_ff$dD_OUT, byteAlignerWriter_addr_ff$sD_IN; @@ -1227,6 +1132,21 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_addr_ff$dEMPTY_N, byteAlignerWriter_addr_ff$sENQ; + // ports of submodule byteAlignerWriter_incoming + wire [255 : 0] byteAlignerWriter_incoming$D_IN, + byteAlignerWriter_incoming$D_OUT; + wire byteAlignerWriter_incoming$CLR, + byteAlignerWriter_incoming$DEQ, + byteAlignerWriter_incoming$EMPTY_N, + byteAlignerWriter_incoming$ENQ; + + // ports of submodule byteAlignerWriter_outgoing + wire [255 : 0] byteAlignerWriter_outgoing$D_IN; + wire byteAlignerWriter_outgoing$CLR, + byteAlignerWriter_outgoing$DEQ, + byteAlignerWriter_outgoing$ENQ, + byteAlignerWriter_outgoing$FULL_N; + // ports of submodule cmdsIn wire cmdsIn$CLR, cmdsIn$DEQ, @@ -1287,10 +1207,21 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_rd_master_rd_in$FULL_N; // ports of submodule m_fpga_rd_master_rd_out - wire [516 : 0] m_fpga_rd_master_rd_out$D_IN; + wire [516 : 0] m_fpga_rd_master_rd_out$D_IN, m_fpga_rd_master_rd_out$D_OUT; wire m_fpga_rd_master_rd_out$CLR, m_fpga_rd_master_rd_out$DEQ, - m_fpga_rd_master_rd_out$ENQ; + m_fpga_rd_master_rd_out$EMPTY_N, + m_fpga_rd_master_rd_out$ENQ, + m_fpga_rd_master_rd_out$FULL_N; + + // ports of submodule m_fpga_rd_outgoingBuffer + wire [511 : 0] m_fpga_rd_outgoingBuffer$D_IN, + m_fpga_rd_outgoingBuffer$D_OUT; + wire m_fpga_rd_outgoingBuffer$CLR, + m_fpga_rd_outgoingBuffer$DEQ, + m_fpga_rd_outgoingBuffer$EMPTY_N, + m_fpga_rd_outgoingBuffer$ENQ, + m_fpga_rd_outgoingBuffer$FULL_N; // ports of submodule m_fpga_rd_reqGen_incomingBuffer wire [131 : 0] m_fpga_rd_reqGen_incomingBuffer$D_IN, @@ -1337,6 +1268,15 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_beatsPerRequestFIFO$ENQ, m_fpga_wr_beatsPerRequestFIFO$FULL_N; + // ports of submodule m_fpga_wr_incomingBuffer + wire [511 : 0] m_fpga_wr_incomingBuffer$D_IN, + m_fpga_wr_incomingBuffer$D_OUT; + wire m_fpga_wr_incomingBuffer$CLR, + m_fpga_wr_incomingBuffer$DEQ, + m_fpga_wr_incomingBuffer$EMPTY_N, + m_fpga_wr_incomingBuffer$ENQ, + m_fpga_wr_incomingBuffer$FULL_N; + // ports of submodule m_fpga_wr_master_wr_in_addr wire [94 : 0] m_fpga_wr_master_wr_in_addr$D_IN, m_fpga_wr_master_wr_in_addr$D_OUT; @@ -1347,10 +1287,13 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_master_wr_in_addr$FULL_N; // ports of submodule m_fpga_wr_master_wr_in_data - wire [577 : 0] m_fpga_wr_master_wr_in_data$D_IN; + wire [577 : 0] m_fpga_wr_master_wr_in_data$D_IN, + m_fpga_wr_master_wr_in_data$D_OUT; wire m_fpga_wr_master_wr_in_data$CLR, m_fpga_wr_master_wr_in_data$DEQ, - m_fpga_wr_master_wr_in_data$ENQ; + m_fpga_wr_master_wr_in_data$EMPTY_N, + m_fpga_wr_master_wr_in_data$ENQ, + m_fpga_wr_master_wr_in_data$FULL_N; // ports of submodule m_fpga_wr_master_wr_out wire [3 : 0] m_fpga_wr_master_wr_out$D_IN; @@ -1405,10 +1348,21 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_rd_master_rd_in$FULL_N; // ports of submodule m_pcie_rd_master_rd_out - wire [260 : 0] m_pcie_rd_master_rd_out$D_IN; + wire [260 : 0] m_pcie_rd_master_rd_out$D_IN, m_pcie_rd_master_rd_out$D_OUT; wire m_pcie_rd_master_rd_out$CLR, m_pcie_rd_master_rd_out$DEQ, - m_pcie_rd_master_rd_out$ENQ; + m_pcie_rd_master_rd_out$EMPTY_N, + m_pcie_rd_master_rd_out$ENQ, + m_pcie_rd_master_rd_out$FULL_N; + + // ports of submodule m_pcie_rd_outgoingBuffer + wire [255 : 0] m_pcie_rd_outgoingBuffer$D_IN, + m_pcie_rd_outgoingBuffer$D_OUT; + wire m_pcie_rd_outgoingBuffer$CLR, + m_pcie_rd_outgoingBuffer$DEQ, + m_pcie_rd_outgoingBuffer$EMPTY_N, + m_pcie_rd_outgoingBuffer$ENQ, + m_pcie_rd_outgoingBuffer$FULL_N; // ports of submodule m_pcie_rd_reqGen_incomingBuffer wire [131 : 0] m_pcie_rd_reqGen_incomingBuffer$D_IN, @@ -1455,6 +1409,15 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_wr_beatsPerRequestFIFO$ENQ, m_pcie_wr_beatsPerRequestFIFO$FULL_N; + // ports of submodule m_pcie_wr_incomingBuffer + reg [255 : 0] m_pcie_wr_incomingBuffer$D_IN; + wire [255 : 0] m_pcie_wr_incomingBuffer$D_OUT; + wire m_pcie_wr_incomingBuffer$CLR, + m_pcie_wr_incomingBuffer$DEQ, + m_pcie_wr_incomingBuffer$EMPTY_N, + m_pcie_wr_incomingBuffer$ENQ, + m_pcie_wr_incomingBuffer$FULL_N; + // ports of submodule m_pcie_wr_master_wr_in_addr wire [94 : 0] m_pcie_wr_master_wr_in_addr$D_IN, m_pcie_wr_master_wr_in_addr$D_OUT; @@ -1465,10 +1428,13 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_wr_master_wr_in_addr$FULL_N; // ports of submodule m_pcie_wr_master_wr_in_data - wire [289 : 0] m_pcie_wr_master_wr_in_data$D_IN; + wire [289 : 0] m_pcie_wr_master_wr_in_data$D_IN, + m_pcie_wr_master_wr_in_data$D_OUT; wire m_pcie_wr_master_wr_in_data$CLR, m_pcie_wr_master_wr_in_data$DEQ, - m_pcie_wr_master_wr_in_data$ENQ; + m_pcie_wr_master_wr_in_data$EMPTY_N, + m_pcie_wr_master_wr_in_data$ENQ, + m_pcie_wr_master_wr_in_data$FULL_N; // ports of submodule m_pcie_wr_master_wr_out wire [3 : 0] m_pcie_wr_master_wr_out$D_IN; @@ -1612,6 +1578,14 @@ module mkBlueDMA(CLK_m32_axi_aclk, writeConvBTT_ff$sENQ, writeConvBTT_ff$sFULL_N; + // ports of submodule writeConverter_dataSync + wire [511 : 0] writeConverter_dataSync$D_IN, writeConverter_dataSync$D_OUT; + wire writeConverter_dataSync$CLR, + writeConverter_dataSync$DEQ, + writeConverter_dataSync$EMPTY_N, + writeConverter_dataSync$ENQ, + writeConverter_dataSync$FULL_N; + // rule scheduling signals wire CAN_FIRE_RL_byteAlignerReader_forwardOutputLast, CAN_FIRE_RL_byteAlignerWriter_forwardOutputLast, @@ -1691,10 +1665,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, // inputs to muxes for submodule ports wire [511 : 0] MUX_byteAlignerReader_buffer$port0__write_1__VAL_1, MUX_byteAlignerWriter_buffer$port0__write_1__VAL_1; - wire [256 : 0] MUX_byteAlignerReader_outgoing_rv$port1__write_1__VAL_1, - MUX_byteAlignerReader_outgoing_rv$port1__write_1__VAL_2, - MUX_byteAlignerWriter_outgoing_rv$port1__write_1__VAL_1, - MUX_byteAlignerWriter_outgoing_rv$port1__write_1__VAL_2; wire [134 : 0] MUX_m_pcie_rd_task_data_requests_reg$write_1__VAL_1, MUX_m_pcie_wr_task_data_requests_reg$write_1__VAL_1; wire [133 : 0] MUX_m_fpga_rd_task_data_requests_reg$write_1__VAL_1, @@ -1740,132 +1710,131 @@ module mkBlueDMA(CLK_m32_axi_aclk, wire MUX_opInProgress$write_1__SEL_2; // remaining internal signals - reg [255 : 0] CASE_readConverter_wordInCntr_0_readConverter__ETC__q2; - reg [3 : 0] CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q6, - CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q5, - CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q4, - CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q3; + reg [3 : 0] CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q5, + CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q4, + CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q3, + CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q2; wire [63 : 0] _theResult____h24288, _theResult____h24472, - _theResult____h34798, - _theResult____h34982, - _theResult____h39240, - _theResult____h39424, - _theResult____h55143, - _theResult____h55327, - btt__h103430, - btt__h147854, + _theResult____h34242, + _theResult____h34426, + _theResult____h38131, + _theResult____h38315, + _theResult____h53478, + _theResult____h53662, + btt__h100105, + btt__h143147, bytes_first___1__h24323, - bytes_first___1__h34833, - bytes_first___1__h39275, - bytes_first___1__h55178, + bytes_first___1__h34277, + bytes_first___1__h38166, + bytes_first___1__h53513, bytes_first__h24287, - bytes_first__h34797, - bytes_first__h39239, - bytes_first__h55142, - m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7, - m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8, - m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9, - m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q10, + bytes_first__h34241, + bytes_first__h38130, + bytes_first__h53477, + m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6, + m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7, + m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8, + m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9, request_data_address__h24612, - request_data_address__h35122, - request_data_address__h39564, - request_data_address__h55467, + request_data_address__h34566, + request_data_address__h38455, + request_data_address__h53802, transfers_total___1__h24480, - transfers_total___1__h34990, - transfers_total___1__h39432, - transfers_total___1__h55335, + transfers_total___1__h34434, + transfers_total___1__h38323, + transfers_total___1__h53670, transfers_total__h24471, transfers_total__h24477, - transfers_total__h34981, - transfers_total__h34987, - transfers_total__h39423, - transfers_total__h39429, - transfers_total__h55326, - transfers_total__h55332, + transfers_total__h34425, + transfers_total__h34431, + transfers_total__h38314, + transfers_total__h38320, + transfers_total__h53661, + transfers_total__h53667, x__h24293, x__h24474, x__h24500, - x__h34803, - x__h34984, - x__h35010, - x__h39245, - x__h39426, - x__h39452, - x__h55148, - x__h55329, - x__h55355, - x_address__h27994, - x_address__h37519, - x_address__h42931, - x_address__h57861, - x_strb__h43525, - y__h103467, - y__h147882, + x__h34247, + x__h34428, + x__h34454, + x__h38136, + x__h38317, + x__h38343, + x__h53483, + x__h53664, + x__h53690, + x_address__h27534, + x_address__h36691, + x_address__h41362, + x_address__h55924, + x_strb__h41878, + y__h100142, + y__h143175, y__h24367, y__h24501, y__h24503, - y__h34877, - y__h35011, - y__h35013, - y__h39319, - y__h39453, - y__h39455, - y__h55222, - y__h55356, - y__h55358; + y__h34321, + y__h34455, + y__h34457, + y__h38210, + y__h38344, + y__h38346, + y__h53557, + y__h53691, + y__h53693; wire [58 : 0] request_data_requests_total__h24611, - request_data_requests_total__h35121, + request_data_requests_total__h34565, requests_total___1__h24637, - requests_total___1__h35147, + requests_total___1__h34591, requests_total__h24575, - requests_total__h35085, - x_requests_total__h27993, - x_requests_total__h37518, - x_transfers_total__h34115, - x_transfers_total__h38179; - wire [57 : 0] request_data_requests_total__h39563, - request_data_requests_total__h55466, - requests_total___1__h39589, - requests_total___1__h55492, - requests_total__h39527, - requests_total__h55430, - x_requests_total__h42930, - x_requests_total__h57860, - x_transfers_total__h54460, - x_transfers_total__h58521; - wire [31 : 0] x_strb__h28588; - wire [7 : 0] _theResult____h27888, - _theResult____h42825, - beatsThisRequestCntrT__h28413, - beatsThisRequestCntrT__h43350, - beatsThisRequest___1__h27936, - beatsThisRequest___1__h37490, - beatsThisRequest___1__h42873, - beatsThisRequest___1__h57832, + requests_total__h34529, + x_requests_total__h27533, + x_requests_total__h36690, + x_transfers_total__h33560, + x_transfers_total__h37140; + wire [57 : 0] request_data_requests_total__h38454, + request_data_requests_total__h53801, + requests_total___1__h38480, + requests_total___1__h53827, + requests_total__h38418, + requests_total__h53765, + x_requests_total__h41361, + x_requests_total__h55923, + x_transfers_total__h52796, + x_transfers_total__h56373; + wire [31 : 0] x_strb__h28050; + wire [7 : 0] _theResult____h27428, + _theResult____h41256, + beatsThisRequestCntrT__h27936, + beatsThisRequestCntrT__h41764, + beatsThisRequest___1__h27476, + beatsThisRequest___1__h36662, + beatsThisRequest___1__h41304, + beatsThisRequest___1__h55895, requests_last__h24574, - requests_last__h35084; - wire [6 : 0] IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945, - endByte___1__h46449, - endByte___1__h46475, - startByte___1__h46448, - x__h46435; - wire [5 : 0] IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453, - b__h117504, - b__h73043, - endByte___1__h30104, - endByte___1__h30130, - startByte___1__h30103, - x__h30090; + requests_last__h34528; + wire [6 : 0] IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936, + endByte___1__h44787, + endByte___1__h44813, + startByte___1__h44786, + x__h44773; + wire [5 : 0] IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451, + b__h113489, + b__h70410, + endByte___1__h29551, + endByte___1__h29577, + startByte___1__h29550, + x__h29537; wire [1 : 0] IF_0_CONCAT_readConverter_wordInCntr_EQ_1_OR_r_ETC__q1; - wire byteAlignerReader_bytes_in_453_ULT_byteAligner_ETC___d1455, - byteAlignerReader_bytes_left_in_buffer_port1___ETC___d1472, - byteAlignerWriter_bytes_in_582_ULT_byteAligner_ETC___d1584, - byteAlignerWriter_bytes_left_in_buffer_port1___ETC___d1601, - fpgaLastCycle_703_AND_m_fpga_rd_task_data_outp_ETC___d1705, - m_fpga_wr_beatsThisRequestCntr_22_EQ_m_fpga_wr_ETC___d924, - m_pcie_wr_beatsThisRequestCntr_30_EQ_m_pcie_wr_ETC___d432, - pcieLastCycle_696_AND_m_pcie_rd_task_data_outp_ETC___d1698; + wire byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440, + byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455, + byteAlignerWriter_bytes_in_559_ULT_byteAligner_ETC___d1561, + byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1576, + fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672, + m_fpga_wr_beatsThisRequestCntr_13_EQ_m_fpga_wr_ETC___d915, + m_pcie_wr_beatsThisRequestCntr_28_EQ_m_pcie_wr_ETC___d430, + pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665; // value method s_rd_arready assign S_AXI_arready = s_config_readSlave_in$FULL_N ; @@ -1942,7 +1911,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, (!m_pcie_rd_master_rd_in$EMPTY_N || m_pcie_rd_master_rd_warcache$wget == 4'd0) ? 4'd0 : - CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q4 ; + CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q3 ; // value method pcie_rd_arprot assign pcie_rd_arprot = @@ -1968,7 +1937,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_rd_master_rd_in$D_OUT[0] ; // value method pcie_rd_rready - assign pcie_rd_rready = !m_pcie_rd_master_rd_out_1_rv$port1__read[261] ; + assign pcie_rd_rready = m_pcie_rd_master_rd_out$FULL_N ; // value method pcie_wr_awvalid assign pcie_wr_awvalid = m_pcie_wr_master_wr_in_addr$EMPTY_N ; @@ -2012,7 +1981,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, (!m_pcie_wr_master_wr_in_addr$EMPTY_N || m_pcie_wr_master_wr_wawcache$wget == 4'd0) ? 4'd0 : - CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q3 ; + CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q2 ; // value method pcie_wr_awprot assign pcie_wr_awprot = @@ -2038,29 +2007,29 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_wr_master_wr_in_addr$D_OUT[0] ; // value method pcie_wr_wvalid - assign pcie_wr_wvalid = m_pcie_wr_master_wr_in_data_1_rv[290] ; + assign pcie_wr_wvalid = m_pcie_wr_master_wr_in_data$EMPTY_N ; // value method pcie_wr_wdata assign pcie_wr_wdata = - m_pcie_wr_master_wr_in_data_1_rv[290] ? - m_pcie_wr_master_wr_in_data_1_rv[289:34] : + m_pcie_wr_master_wr_in_data$EMPTY_N ? + m_pcie_wr_master_wr_in_data$D_OUT[289:34] : 256'd0 ; // value method pcie_wr_wstrb assign pcie_wr_wstrb = - m_pcie_wr_master_wr_in_data_1_rv[290] ? - m_pcie_wr_master_wr_in_data_1_rv[33:2] : + m_pcie_wr_master_wr_in_data$EMPTY_N ? + m_pcie_wr_master_wr_in_data$D_OUT[33:2] : 32'd0 ; // value method pcie_wr_wlast assign pcie_wr_wlast = - m_pcie_wr_master_wr_in_data_1_rv[290] && - m_pcie_wr_master_wr_in_data_1_rv[1] ; + m_pcie_wr_master_wr_in_data$EMPTY_N && + m_pcie_wr_master_wr_in_data$D_OUT[1] ; // value method pcie_wr_wuser assign pcie_wr_wuser = - m_pcie_wr_master_wr_in_data_1_rv[290] && - m_pcie_wr_master_wr_in_data_1_rv[0] ; + m_pcie_wr_master_wr_in_data$EMPTY_N && + m_pcie_wr_master_wr_in_data$D_OUT[0] ; // value method pcie_wr_bready assign pcie_wr_bready = m_pcie_wr_master_wr_out$FULL_N ; @@ -2107,7 +2076,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, (!m_fpga_rd_master_rd_in$EMPTY_N || m_fpga_rd_master_rd_warcache$wget == 4'd0) ? 4'd0 : - CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q6 ; + CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q5 ; // value method fpga_rd_arprot assign fpga_rd_arprot = @@ -2133,7 +2102,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_rd_master_rd_in$D_OUT[0] ; // value method fpga_rd_rready - assign fpga_rd_rready = !m_fpga_rd_master_rd_out_1_rv$port1__read[517] ; + assign fpga_rd_rready = m_fpga_rd_master_rd_out$FULL_N ; // value method fpga_wr_awvalid assign fpga_wr_awvalid = m_fpga_wr_master_wr_in_addr$EMPTY_N ; @@ -2177,7 +2146,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, (!m_fpga_wr_master_wr_in_addr$EMPTY_N || m_fpga_wr_master_wr_wawcache$wget == 4'd0) ? 4'd0 : - CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q5 ; + CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q4 ; // value method fpga_wr_awprot assign fpga_wr_awprot = @@ -2203,29 +2172,29 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_master_wr_in_addr$D_OUT[0] ; // value method fpga_wr_wvalid - assign fpga_wr_wvalid = m_fpga_wr_master_wr_in_data_1_rv[578] ; + assign fpga_wr_wvalid = m_fpga_wr_master_wr_in_data$EMPTY_N ; // value method fpga_wr_wdata assign fpga_wr_wdata = - m_fpga_wr_master_wr_in_data_1_rv[578] ? - m_fpga_wr_master_wr_in_data_1_rv[577:66] : + m_fpga_wr_master_wr_in_data$EMPTY_N ? + m_fpga_wr_master_wr_in_data$D_OUT[577:66] : 512'd0 ; // value method fpga_wr_wstrb assign fpga_wr_wstrb = - m_fpga_wr_master_wr_in_data_1_rv[578] ? - m_fpga_wr_master_wr_in_data_1_rv[65:2] : + m_fpga_wr_master_wr_in_data$EMPTY_N ? + m_fpga_wr_master_wr_in_data$D_OUT[65:2] : 64'd0 ; // value method fpga_wr_wlast assign fpga_wr_wlast = - m_fpga_wr_master_wr_in_data_1_rv[578] && - m_fpga_wr_master_wr_in_data_1_rv[1] ; + m_fpga_wr_master_wr_in_data$EMPTY_N && + m_fpga_wr_master_wr_in_data$D_OUT[1] ; // value method fpga_wr_wuser assign fpga_wr_wuser = - m_fpga_wr_master_wr_in_data_1_rv[578] && - m_fpga_wr_master_wr_in_data_1_rv[0] ; + m_fpga_wr_master_wr_in_data$EMPTY_N && + m_fpga_wr_master_wr_in_data$D_OUT[0] ; // value method fpga_wr_bready assign fpga_wr_bready = m_fpga_wr_master_wr_out$FULL_N ; @@ -2244,6 +2213,30 @@ module mkBlueDMA(CLK_m32_axi_aclk, .dEMPTY_N(byteAlignerReader_addr_ff$dEMPTY_N), .dD_OUT(byteAlignerReader_addr_ff$dD_OUT)); + // submodule byteAlignerReader_incoming + FIFO2 #(.width(32'd256), + .guarded(32'd1)) byteAlignerReader_incoming(.RST(RST_N_m64_axi_arestn), + .CLK(CLK_m64_axi_aclk), + .D_IN(byteAlignerReader_incoming$D_IN), + .ENQ(byteAlignerReader_incoming$ENQ), + .DEQ(byteAlignerReader_incoming$DEQ), + .CLR(byteAlignerReader_incoming$CLR), + .D_OUT(byteAlignerReader_incoming$D_OUT), + .FULL_N(), + .EMPTY_N(byteAlignerReader_incoming$EMPTY_N)); + + // submodule byteAlignerReader_outgoing + FIFO2 #(.width(32'd256), + .guarded(32'd1)) byteAlignerReader_outgoing(.RST(RST_N_m64_axi_arestn), + .CLK(CLK_m64_axi_aclk), + .D_IN(byteAlignerReader_outgoing$D_IN), + .ENQ(byteAlignerReader_outgoing$ENQ), + .DEQ(byteAlignerReader_outgoing$DEQ), + .CLR(byteAlignerReader_outgoing$CLR), + .D_OUT(), + .FULL_N(byteAlignerReader_outgoing$FULL_N), + .EMPTY_N()); + // submodule byteAlignerWriter_addr_ff SyncFIFO1 #(.dataWidth(32'd192)) byteAlignerWriter_addr_ff(.sCLK(CLK), .dCLK(CLK_m64_axi_aclk), @@ -2255,6 +2248,30 @@ module mkBlueDMA(CLK_m32_axi_aclk, .dEMPTY_N(byteAlignerWriter_addr_ff$dEMPTY_N), .dD_OUT(byteAlignerWriter_addr_ff$dD_OUT)); + // submodule byteAlignerWriter_incoming + FIFO2 #(.width(32'd256), + .guarded(32'd1)) byteAlignerWriter_incoming(.RST(RST_N_m64_axi_arestn), + .CLK(CLK_m64_axi_aclk), + .D_IN(byteAlignerWriter_incoming$D_IN), + .ENQ(byteAlignerWriter_incoming$ENQ), + .DEQ(byteAlignerWriter_incoming$DEQ), + .CLR(byteAlignerWriter_incoming$CLR), + .D_OUT(byteAlignerWriter_incoming$D_OUT), + .FULL_N(), + .EMPTY_N(byteAlignerWriter_incoming$EMPTY_N)); + + // submodule byteAlignerWriter_outgoing + FIFO2 #(.width(32'd256), + .guarded(32'd1)) byteAlignerWriter_outgoing(.RST(RST_N_m64_axi_arestn), + .CLK(CLK_m64_axi_aclk), + .D_IN(byteAlignerWriter_outgoing$D_IN), + .ENQ(byteAlignerWriter_outgoing$ENQ), + .DEQ(byteAlignerWriter_outgoing$DEQ), + .CLR(byteAlignerWriter_outgoing$CLR), + .D_OUT(), + .FULL_N(byteAlignerWriter_outgoing$FULL_N), + .EMPTY_N()); + // submodule cmdsIn FIFO2 #(.width(32'd1), .guarded(32'd1)) cmdsIn(.RST(RST_N), .CLK(CLK), @@ -2368,16 +2385,28 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_fpga_rd_master_rd_in$EMPTY_N)); // submodule m_fpga_rd_master_rd_out - FIFO1 #(.width(32'd517), + FIFO2 #(.width(32'd517), .guarded(32'd1)) m_fpga_rd_master_rd_out(.RST(RST_N_m32_axi_arestn), .CLK(CLK_m32_axi_aclk), .D_IN(m_fpga_rd_master_rd_out$D_IN), .ENQ(m_fpga_rd_master_rd_out$ENQ), .DEQ(m_fpga_rd_master_rd_out$DEQ), .CLR(m_fpga_rd_master_rd_out$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N()); + .D_OUT(m_fpga_rd_master_rd_out$D_OUT), + .FULL_N(m_fpga_rd_master_rd_out$FULL_N), + .EMPTY_N(m_fpga_rd_master_rd_out$EMPTY_N)); + + // submodule m_fpga_rd_outgoingBuffer + FIFO2 #(.width(32'd512), + .guarded(32'd1)) m_fpga_rd_outgoingBuffer(.RST(RST_N_m32_axi_arestn), + .CLK(CLK_m32_axi_aclk), + .D_IN(m_fpga_rd_outgoingBuffer$D_IN), + .ENQ(m_fpga_rd_outgoingBuffer$ENQ), + .DEQ(m_fpga_rd_outgoingBuffer$DEQ), + .CLR(m_fpga_rd_outgoingBuffer$CLR), + .D_OUT(m_fpga_rd_outgoingBuffer$D_OUT), + .FULL_N(m_fpga_rd_outgoingBuffer$FULL_N), + .EMPTY_N(m_fpga_rd_outgoingBuffer$EMPTY_N)); // submodule m_fpga_rd_reqGen_incomingBuffer FIFO2 #(.width(32'd132), @@ -2441,6 +2470,18 @@ module mkBlueDMA(CLK_m32_axi_aclk, .FULL_N(m_fpga_wr_beatsPerRequestFIFO$FULL_N), .EMPTY_N(m_fpga_wr_beatsPerRequestFIFO$EMPTY_N)); + // submodule m_fpga_wr_incomingBuffer + FIFO2 #(.width(32'd512), + .guarded(32'd1)) m_fpga_wr_incomingBuffer(.RST(RST_N_m32_axi_arestn), + .CLK(CLK_m32_axi_aclk), + .D_IN(m_fpga_wr_incomingBuffer$D_IN), + .ENQ(m_fpga_wr_incomingBuffer$ENQ), + .DEQ(m_fpga_wr_incomingBuffer$DEQ), + .CLR(m_fpga_wr_incomingBuffer$CLR), + .D_OUT(m_fpga_wr_incomingBuffer$D_OUT), + .FULL_N(m_fpga_wr_incomingBuffer$FULL_N), + .EMPTY_N(m_fpga_wr_incomingBuffer$EMPTY_N)); + // submodule m_fpga_wr_master_wr_in_addr SizedFIFO #(.p1width(32'd95), .p2depth(32'd8), @@ -2456,16 +2497,16 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_fpga_wr_master_wr_in_addr$EMPTY_N)); // submodule m_fpga_wr_master_wr_in_data - FIFO1 #(.width(32'd578), + FIFO2 #(.width(32'd578), .guarded(32'd1)) m_fpga_wr_master_wr_in_data(.RST(RST_N_m32_axi_arestn), .CLK(CLK_m32_axi_aclk), .D_IN(m_fpga_wr_master_wr_in_data$D_IN), .ENQ(m_fpga_wr_master_wr_in_data$ENQ), .DEQ(m_fpga_wr_master_wr_in_data$DEQ), .CLR(m_fpga_wr_master_wr_in_data$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N()); + .D_OUT(m_fpga_wr_master_wr_in_data$D_OUT), + .FULL_N(m_fpga_wr_master_wr_in_data$FULL_N), + .EMPTY_N(m_fpga_wr_master_wr_in_data$EMPTY_N)); // submodule m_fpga_wr_master_wr_out FIFO2 #(.width(32'd4), @@ -2529,8 +2570,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_master_rd_in SizedFIFO #(.p1width(32'd95), - .p2depth(32'd32), - .p3cntr_width(32'd5), + .p2depth(32'd8), + .p3cntr_width(32'd3), .guarded(32'd1)) m_pcie_rd_master_rd_in(.RST(RST_N_m64_axi_arestn), .CLK(CLK_m64_axi_aclk), .D_IN(m_pcie_rd_master_rd_in$D_IN), @@ -2542,16 +2583,28 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_pcie_rd_master_rd_in$EMPTY_N)); // submodule m_pcie_rd_master_rd_out - FIFO1 #(.width(32'd261), + FIFO2 #(.width(32'd261), .guarded(32'd1)) m_pcie_rd_master_rd_out(.RST(RST_N_m64_axi_arestn), .CLK(CLK_m64_axi_aclk), .D_IN(m_pcie_rd_master_rd_out$D_IN), .ENQ(m_pcie_rd_master_rd_out$ENQ), .DEQ(m_pcie_rd_master_rd_out$DEQ), .CLR(m_pcie_rd_master_rd_out$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N()); + .D_OUT(m_pcie_rd_master_rd_out$D_OUT), + .FULL_N(m_pcie_rd_master_rd_out$FULL_N), + .EMPTY_N(m_pcie_rd_master_rd_out$EMPTY_N)); + + // submodule m_pcie_rd_outgoingBuffer + FIFO2 #(.width(32'd256), + .guarded(32'd1)) m_pcie_rd_outgoingBuffer(.RST(RST_N_m64_axi_arestn), + .CLK(CLK_m64_axi_aclk), + .D_IN(m_pcie_rd_outgoingBuffer$D_IN), + .ENQ(m_pcie_rd_outgoingBuffer$ENQ), + .DEQ(m_pcie_rd_outgoingBuffer$DEQ), + .CLR(m_pcie_rd_outgoingBuffer$CLR), + .D_OUT(m_pcie_rd_outgoingBuffer$D_OUT), + .FULL_N(m_pcie_rd_outgoingBuffer$FULL_N), + .EMPTY_N(m_pcie_rd_outgoingBuffer$EMPTY_N)); // submodule m_pcie_rd_reqGen_incomingBuffer FIFO2 #(.width(32'd132), @@ -2615,6 +2668,18 @@ module mkBlueDMA(CLK_m32_axi_aclk, .FULL_N(m_pcie_wr_beatsPerRequestFIFO$FULL_N), .EMPTY_N(m_pcie_wr_beatsPerRequestFIFO$EMPTY_N)); + // submodule m_pcie_wr_incomingBuffer + FIFO2 #(.width(32'd256), + .guarded(32'd1)) m_pcie_wr_incomingBuffer(.RST(RST_N_m64_axi_arestn), + .CLK(CLK_m64_axi_aclk), + .D_IN(m_pcie_wr_incomingBuffer$D_IN), + .ENQ(m_pcie_wr_incomingBuffer$ENQ), + .DEQ(m_pcie_wr_incomingBuffer$DEQ), + .CLR(m_pcie_wr_incomingBuffer$CLR), + .D_OUT(m_pcie_wr_incomingBuffer$D_OUT), + .FULL_N(m_pcie_wr_incomingBuffer$FULL_N), + .EMPTY_N(m_pcie_wr_incomingBuffer$EMPTY_N)); + // submodule m_pcie_wr_master_wr_in_addr SizedFIFO #(.p1width(32'd95), .p2depth(32'd8), @@ -2630,16 +2695,16 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_pcie_wr_master_wr_in_addr$EMPTY_N)); // submodule m_pcie_wr_master_wr_in_data - FIFO1 #(.width(32'd290), + FIFO2 #(.width(32'd290), .guarded(32'd1)) m_pcie_wr_master_wr_in_data(.RST(RST_N_m64_axi_arestn), .CLK(CLK_m64_axi_aclk), .D_IN(m_pcie_wr_master_wr_in_data$D_IN), .ENQ(m_pcie_wr_master_wr_in_data$ENQ), .DEQ(m_pcie_wr_master_wr_in_data$DEQ), .CLR(m_pcie_wr_master_wr_in_data$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N()); + .D_OUT(m_pcie_wr_master_wr_in_data$D_OUT), + .FULL_N(m_pcie_wr_master_wr_in_data$FULL_N), + .EMPTY_N(m_pcie_wr_master_wr_in_data$EMPTY_N)); // submodule m_pcie_wr_master_wr_out FIFO2 #(.width(32'd4), @@ -2853,6 +2918,18 @@ module mkBlueDMA(CLK_m32_axi_aclk, .dEMPTY_N(writeConvBTT_ff$dEMPTY_N), .dD_OUT(writeConvBTT_ff$dD_OUT)); + // submodule writeConverter_dataSync + FIFO2 #(.width(32'd512), + .guarded(32'd1)) writeConverter_dataSync(.RST(RST_N_m64_axi_arestn), + .CLK(CLK_m64_axi_aclk), + .D_IN(writeConverter_dataSync$D_IN), + .ENQ(writeConverter_dataSync$ENQ), + .DEQ(writeConverter_dataSync$DEQ), + .CLR(writeConverter_dataSync$CLR), + .D_OUT(writeConverter_dataSync$D_OUT), + .FULL_N(writeConverter_dataSync$FULL_N), + .EMPTY_N(writeConverter_dataSync$EMPTY_N)); + // rule RL_setInterrupt assign WILL_FIRE_RL_setInterrupt = pcieDone$dEMPTY_N && fpgaDone$dEMPTY_N && opInProgress ; @@ -2971,18 +3048,18 @@ module mkBlueDMA(CLK_m32_axi_aclk, s_config_readSlave_in$D_OUT[10:6] == 5'd9 && !s_config_readBusy ; - // rule RL_s_config_axiReadSpecial_7 - assign WILL_FIRE_RL_s_config_axiReadSpecial_7 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd10 && - !s_config_readBusy ; - // rule RL_s_config_axiReadSpecial_8 assign WILL_FIRE_RL_s_config_axiReadSpecial_8 = s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && s_config_readSlave_in$D_OUT[10:6] == 5'd11 && !s_config_readBusy ; + // rule RL_s_config_axiReadSpecial_7 + assign WILL_FIRE_RL_s_config_axiReadSpecial_7 = + s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && + s_config_readSlave_in$D_OUT[10:6] == 5'd10 && + !s_config_readBusy ; + // rule RL_s_config_axiReadSpecial_9 assign WILL_FIRE_RL_s_config_axiReadSpecial_9 = s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && @@ -3132,13 +3209,13 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_wr_master_wr_in_addr$FULL_N && m_pcie_wr_beatsPerRequestFIFO$FULL_N && m_pcie_wr_task_data_requests_reg[126:68] != 59'd0 && - m_pcie_wr_incomingBuffer_rv[256] ; + m_pcie_wr_incomingBuffer$EMPTY_N ; // rule RL_m_pcie_wr_forwardData assign WILL_FIRE_RL_m_pcie_wr_forwardData = - m_pcie_wr_incomingBuffer_rv[256] && + m_pcie_wr_incomingBuffer$EMPTY_N && m_pcie_wr_beatsPerRequestFIFO$EMPTY_N && - !m_pcie_wr_master_wr_in_data_1_rv$port1__read[290] && + m_pcie_wr_master_wr_in_data$FULL_N && m_pcie_wr_task_data_output_reg[64:6] != 59'd0 ; // rule RL_m_pcie_rd_fillBuffer @@ -3157,6 +3234,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_rd_master_rd_in$FULL_N && m_pcie_rd_task_data_requests_reg[126:68] != 59'd0 ; + // rule RL_m_pcie_rd_forwardData + assign WILL_FIRE_RL_m_pcie_rd_forwardData = + m_pcie_rd_master_rd_out$EMPTY_N && + m_pcie_rd_outgoingBuffer$FULL_N && + m_pcie_rd_task_data_output_reg[64:6] != 59'd0 ; + // rule RL_m_fpga_wr_fillBuffer assign WILL_FIRE_RL_m_fpga_wr_fillBuffer = m_fpga_wr_reqGen_outgoingBuffer$EMPTY_N && @@ -3173,21 +3256,15 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_master_wr_in_addr$FULL_N && m_fpga_wr_beatsPerRequestFIFO$FULL_N && m_fpga_wr_task_data_requests_reg[125:68] != 58'd0 && - m_fpga_wr_incomingBuffer_rv[512] ; + m_fpga_wr_incomingBuffer$EMPTY_N ; // rule RL_m_fpga_wr_forwardData assign WILL_FIRE_RL_m_fpga_wr_forwardData = - m_fpga_wr_incomingBuffer_rv[512] && + m_fpga_wr_incomingBuffer$EMPTY_N && m_fpga_wr_beatsPerRequestFIFO$EMPTY_N && - !m_fpga_wr_master_wr_in_data_1_rv$port1__read[578] && + m_fpga_wr_master_wr_in_data$FULL_N && m_fpga_wr_task_data_output_reg[64:7] != 58'd0 ; - // rule RL_m_fpga_rd_forwardData - assign WILL_FIRE_RL_m_fpga_rd_forwardData = - m_fpga_rd_master_rd_out_1_rv[517] && - !m_fpga_rd_outgoingBuffer_rv$port1__read[512] && - m_fpga_rd_task_data_output_reg[64:7] != 58'd0 ; - // rule RL_m_fpga_rd_fillBuffer assign WILL_FIRE_RL_m_fpga_rd_fillBuffer = m_fpga_rd_reqGen_outgoingBuffer$EMPTY_N && @@ -3204,10 +3281,16 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_rd_master_rd_in$FULL_N && m_fpga_rd_task_data_requests_reg[125:68] != 58'd0 ; + // rule RL_m_fpga_rd_forwardData + assign WILL_FIRE_RL_m_fpga_rd_forwardData = + m_fpga_rd_master_rd_out$EMPTY_N && + m_fpga_rd_outgoingBuffer$FULL_N && + m_fpga_rd_task_data_output_reg[64:7] != 58'd0 ; + // rule RL_mkConnectionGetPut_2 assign WILL_FIRE_RL_mkConnectionGetPut_2 = !readConvBTT_ff$dEMPTY_N && !readConverter_bufferEmpty && - !m_pcie_wr_incomingBuffer_rv$port1__read[256] && + m_pcie_wr_incomingBuffer$FULL_N && !readConvBTT_ff$dEMPTY_N ; // rule RL_mkConnectionGetPut_1 @@ -3217,28 +3300,28 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_response_converter$dEMPTY_N && !readConvBTT_ff$dEMPTY_N ; - // rule RL_byteAlignerReader_fetchNewData - assign WILL_FIRE_RL_byteAlignerReader_fetchNewData = - byteAlignerReader_incoming_rv[256] && + // rule RL_byteAlignerReader_forwardOutput + assign WILL_FIRE_RL_byteAlignerReader_forwardOutput = + byteAlignerReader_outgoing$FULL_N && !byteAlignerReader_addr_ff$dEMPTY_N && - !byteAlignerReader_fetchedDatum && - byteAlignerReader_bytes_in_453_ULT_byteAligner_ETC___d1455 && + byteAlignerReader_fetchedDatum && + !byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 && !byteAlignerReader_addr_ff$dEMPTY_N ; - // rule RL_byteAlignerReader_forwardOutput - assign WILL_FIRE_RL_byteAlignerReader_forwardOutput = - !byteAlignerReader_outgoing_rv[256] && + // rule RL_byteAlignerReader_fetchNewData + assign WILL_FIRE_RL_byteAlignerReader_fetchNewData = + byteAlignerReader_incoming$EMPTY_N && !byteAlignerReader_addr_ff$dEMPTY_N && - byteAlignerReader_fetchedDatum$port1__read && - !byteAlignerReader_bytes_left_in_buffer_port1___ETC___d1472 && + !byteAlignerReader_fetchedDatum$port1__read && + byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 && !byteAlignerReader_addr_ff$dEMPTY_N ; // rule RL_byteAlignerReader_forwardOutputLast assign CAN_FIRE_RL_byteAlignerReader_forwardOutputLast = - !byteAlignerReader_outgoing_rv[256] && + byteAlignerReader_outgoing$FULL_N && !byteAlignerReader_addr_ff$dEMPTY_N && !byteAlignerReader_fetchedDatum && - !byteAlignerReader_bytes_in_453_ULT_byteAligner_ETC___d1455 && + !byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 && byteAlignerReader_bytes_out < byteAlignerReader_bytes_total ; assign WILL_FIRE_RL_byteAlignerReader_forwardOutputLast = CAN_FIRE_RL_byteAlignerReader_forwardOutputLast && @@ -3246,38 +3329,32 @@ module mkBlueDMA(CLK_m32_axi_aclk, // rule RL_mkConnectionGetPut_3 assign WILL_FIRE_RL_mkConnectionGetPut_3 = - !writeConvBTT_ff$dEMPTY_N && m_pcie_rd_outgoingBuffer_rv[256] && - !writeConverter_dataSync_rv$port1__read[512] && + !writeConvBTT_ff$dEMPTY_N && m_pcie_rd_outgoingBuffer$EMPTY_N && + writeConverter_dataSync$FULL_N && !writeConvBTT_ff$dEMPTY_N ; - // rule RL_m_pcie_rd_forwardData - assign WILL_FIRE_RL_m_pcie_rd_forwardData = - m_pcie_rd_master_rd_out_1_rv[261] && - !m_pcie_rd_outgoingBuffer_rv$port1__read[256] && - m_pcie_rd_task_data_output_reg[64:6] != 59'd0 ; - - // rule RL_byteAlignerWriter_fetchNewData - assign WILL_FIRE_RL_byteAlignerWriter_fetchNewData = - byteAlignerWriter_incoming_rv[256] && + // rule RL_byteAlignerWriter_forwardOutput + assign WILL_FIRE_RL_byteAlignerWriter_forwardOutput = + byteAlignerWriter_outgoing$FULL_N && !byteAlignerWriter_addr_ff$dEMPTY_N && - !byteAlignerWriter_fetchedDatum && - byteAlignerWriter_bytes_in_582_ULT_byteAligner_ETC___d1584 && + byteAlignerWriter_fetchedDatum && + !byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1576 && !byteAlignerWriter_addr_ff$dEMPTY_N ; - // rule RL_byteAlignerWriter_forwardOutput - assign WILL_FIRE_RL_byteAlignerWriter_forwardOutput = - !byteAlignerWriter_outgoing_rv[256] && + // rule RL_byteAlignerWriter_fetchNewData + assign WILL_FIRE_RL_byteAlignerWriter_fetchNewData = + byteAlignerWriter_incoming$EMPTY_N && !byteAlignerWriter_addr_ff$dEMPTY_N && - byteAlignerWriter_fetchedDatum$port1__read && - !byteAlignerWriter_bytes_left_in_buffer_port1___ETC___d1601 && + !byteAlignerWriter_fetchedDatum$port1__read && + byteAlignerWriter_bytes_in_559_ULT_byteAligner_ETC___d1561 && !byteAlignerWriter_addr_ff$dEMPTY_N ; // rule RL_byteAlignerWriter_forwardOutputLast assign CAN_FIRE_RL_byteAlignerWriter_forwardOutputLast = - !byteAlignerWriter_outgoing_rv[256] && + byteAlignerWriter_outgoing$FULL_N && !byteAlignerWriter_addr_ff$dEMPTY_N && !byteAlignerWriter_fetchedDatum && - !byteAlignerWriter_bytes_in_582_ULT_byteAligner_ETC___d1584 && + !byteAlignerWriter_bytes_in_559_ULT_byteAligner_ETC___d1561 && byteAlignerWriter_bytes_out < byteAlignerWriter_bytes_total ; assign WILL_FIRE_RL_byteAlignerWriter_forwardOutputLast = CAN_FIRE_RL_byteAlignerWriter_forwardOutputLast && @@ -3287,12 +3364,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign MUX_opInProgress$write_1__SEL_2 = WILL_FIRE_RL_handleRead || WILL_FIRE_RL_handleWrite ; assign MUX_byteAlignerReader_buffer$port0__write_1__VAL_1 = - { byteAlignerReader_buffer[511:256], - byteAlignerReader_incoming_rv[255:0] } ; + { 256'd0, byteAlignerReader_buffer[511:256] } ; assign MUX_byteAlignerReader_bytes_in$write_1__VAL_1 = byteAlignerReader_bytes_in + 64'd32 ; assign MUX_byteAlignerReader_bytes_left_in_buffer$port0__write_1__VAL_1 = - byteAlignerReader_bytes_left_in_buffer + 6'd32 ; + byteAlignerReader_bytes_left_in_buffer - + byteAlignerReader_bytes_out_needed ; assign MUX_byteAlignerReader_bytes_out$write_1__VAL_1 = byteAlignerReader_bytes_out + { 58'd0, byteAlignerReader_bytes_out_needed } ; @@ -3300,17 +3377,13 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerReader_bytes_out + 64'd256 ; assign MUX_byteAlignerReader_bytes_out_needed$write_1__VAL_1 = 6'd32 - { 1'd0, byteAlignerReader_addr_ff$dD_OUT[68:64] } ; - assign MUX_byteAlignerReader_outgoing_rv$port1__write_1__VAL_1 = - { 1'd1, byteAlignerReader_buffer$port1__read[255:0] } ; - assign MUX_byteAlignerReader_outgoing_rv$port1__write_1__VAL_2 = - { 1'd1, byteAlignerReader_buffer[255:0] } ; assign MUX_byteAlignerWriter_buffer$port0__write_1__VAL_1 = - { byteAlignerWriter_buffer[511:256], - byteAlignerWriter_incoming_rv[255:0] } ; + { 256'd0, byteAlignerWriter_buffer[511:256] } ; assign MUX_byteAlignerWriter_bytes_in$write_1__VAL_1 = byteAlignerWriter_bytes_in + 64'd32 ; assign MUX_byteAlignerWriter_bytes_left_in_buffer$port0__write_1__VAL_1 = - byteAlignerWriter_bytes_left_in_buffer + 6'd32 ; + byteAlignerWriter_bytes_left_in_buffer - + byteAlignerWriter_bytes_out_needed ; assign MUX_byteAlignerWriter_bytes_out$write_1__VAL_1 = byteAlignerWriter_bytes_out + { 58'd0, byteAlignerWriter_bytes_out_needed } ; @@ -3318,55 +3391,51 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_bytes_out + 64'd256 ; assign MUX_byteAlignerWriter_bytes_out_needed$write_1__VAL_1 = 6'd32 - { 1'd0, byteAlignerWriter_addr_ff$dD_OUT[68:64] } ; - assign MUX_byteAlignerWriter_outgoing_rv$port1__write_1__VAL_1 = - { 1'd1, byteAlignerWriter_buffer$port1__read[255:0] } ; - assign MUX_byteAlignerWriter_outgoing_rv$port1__write_1__VAL_2 = - { 1'd1, byteAlignerWriter_buffer[255:0] } ; assign MUX_m_fpga_rd_task_data_output_reg$write_1__VAL_1 = { m_fpga_rd_task_data_output_reg[76:65], - x_transfers_total__h58521, + x_transfers_total__h56373, m_fpga_rd_task_data_output_reg[6:0] } ; assign MUX_m_fpga_rd_task_data_requests_reg$write_1__VAL_1 = { m_fpga_rd_task_data_requests_reg[133:126], - x_requests_total__h57860, - x_address__h57861, + x_requests_total__h55923, + x_address__h55924, m_fpga_rd_task_data_requests_reg[3:0] } ; assign MUX_m_fpga_wr_beatsThisRequestCntr$write_1__VAL_1 = - m_fpga_wr_beatsThisRequestCntr_22_EQ_m_fpga_wr_ETC___d924 ? + m_fpga_wr_beatsThisRequestCntr_13_EQ_m_fpga_wr_ETC___d915 ? 8'd0 : - beatsThisRequestCntrT__h43350 ; + beatsThisRequestCntrT__h41764 ; assign MUX_m_fpga_wr_task_data_output_reg$write_1__VAL_1 = { m_fpga_wr_task_data_output_reg[76:65], - x_transfers_total__h54460, + x_transfers_total__h52796, m_fpga_wr_task_data_output_reg[6:1], 1'd0 } ; assign MUX_m_fpga_wr_task_data_requests_reg$write_1__VAL_1 = { m_fpga_wr_task_data_requests_reg[133:126], - x_requests_total__h42930, - x_address__h42931, + x_requests_total__h41361, + x_address__h41362, m_fpga_wr_task_data_requests_reg[3:0] } ; assign MUX_m_pcie_rd_task_data_output_reg$write_1__VAL_1 = { m_pcie_rd_task_data_output_reg[74:65], - x_transfers_total__h38179, + x_transfers_total__h37140, m_pcie_rd_task_data_output_reg[5:0] } ; assign MUX_m_pcie_rd_task_data_requests_reg$write_1__VAL_1 = { m_pcie_rd_task_data_requests_reg[134:127], - x_requests_total__h37518, - x_address__h37519, + x_requests_total__h36690, + x_address__h36691, m_pcie_rd_task_data_requests_reg[3:0] } ; assign MUX_m_pcie_wr_beatsThisRequestCntr$write_1__VAL_1 = - m_pcie_wr_beatsThisRequestCntr_30_EQ_m_pcie_wr_ETC___d432 ? + m_pcie_wr_beatsThisRequestCntr_28_EQ_m_pcie_wr_ETC___d430 ? 8'd0 : - beatsThisRequestCntrT__h28413 ; + beatsThisRequestCntrT__h27936 ; assign MUX_m_pcie_wr_task_data_output_reg$write_1__VAL_1 = { m_pcie_wr_task_data_output_reg[74:65], - x_transfers_total__h34115, + x_transfers_total__h33560, m_pcie_wr_task_data_output_reg[5:1], 1'd0 } ; assign MUX_m_pcie_wr_task_data_requests_reg$write_1__VAL_1 = { m_pcie_wr_task_data_requests_reg[134:127], - x_requests_total__h27993, - x_address__h27994, + x_requests_total__h27533, + x_address__h27534, m_pcie_wr_task_data_requests_reg[3:0] } ; assign MUX_readConverter_byteCntr$write_1__VAL_2 = readConverter_byteCntr - 64'd32 ; @@ -3517,111 +3586,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, s_config_writeSlave_dataIn_rv$EN_port1__write ? 73'h0AAAAAAAAAAAAAAAAAA : s_config_writeSlave_dataIn_rv$port1__read ; - assign m_pcie_wr_master_wr_in_data_1_rv$EN_port0__write = - m_pcie_wr_master_wr_in_data_1_rv[290] && pcie_wr_wready ; - assign m_pcie_wr_master_wr_in_data_1_rv$port1__read = - m_pcie_wr_master_wr_in_data_1_rv$EN_port0__write ? - 291'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - m_pcie_wr_master_wr_in_data_1_rv ; - assign m_pcie_wr_master_wr_in_data_1_rv$port1__write_1 = - { 1'd1, - m_pcie_wr_incomingBuffer_rv[255:0], - x_strb__h28588, - m_pcie_wr_beatsThisRequestCntr_30_EQ_m_pcie_wr_ETC___d432, - 1'd0 } ; - assign m_pcie_wr_master_wr_in_data_1_rv$port2__read = - WILL_FIRE_RL_m_pcie_wr_forwardData ? - m_pcie_wr_master_wr_in_data_1_rv$port1__write_1 : - m_pcie_wr_master_wr_in_data_1_rv$port1__read ; - assign m_pcie_wr_incomingBuffer_rv$port1__read = - WILL_FIRE_RL_m_pcie_wr_forwardData ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - m_pcie_wr_incomingBuffer_rv ; - assign m_pcie_wr_incomingBuffer_rv$port1__write_1 = - { 1'd1, - CASE_readConverter_wordInCntr_0_readConverter__ETC__q2 } ; - assign m_pcie_wr_incomingBuffer_rv$port2__read = - WILL_FIRE_RL_mkConnectionGetPut_2 ? - m_pcie_wr_incomingBuffer_rv$port1__write_1 : - m_pcie_wr_incomingBuffer_rv$port1__read ; - assign m_pcie_rd_master_rd_out_1_rv$port1__read = - WILL_FIRE_RL_m_pcie_rd_forwardData ? - 262'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - m_pcie_rd_master_rd_out_1_rv ; - assign m_pcie_rd_master_rd_out_1_rv$EN_port1__write = - !m_pcie_rd_master_rd_out_1_rv$port1__read[261] && - pcie_rd_rvalid ; - assign m_pcie_rd_master_rd_out_1_rv$port1__write_1 = - { 1'd1, m_pcie_rd_master_rd_rinpkg$wget } ; - assign m_pcie_rd_master_rd_out_1_rv$port2__read = - m_pcie_rd_master_rd_out_1_rv$EN_port1__write ? - m_pcie_rd_master_rd_out_1_rv$port1__write_1 : - m_pcie_rd_master_rd_out_1_rv$port1__read ; - assign m_pcie_rd_outgoingBuffer_rv$port1__read = - WILL_FIRE_RL_mkConnectionGetPut_3 ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - m_pcie_rd_outgoingBuffer_rv ; - assign m_pcie_rd_outgoingBuffer_rv$port1__write_1 = - { 1'd1, m_pcie_rd_master_rd_out_1_rv[259:4] } ; - assign m_pcie_rd_outgoingBuffer_rv$port2__read = - WILL_FIRE_RL_m_pcie_rd_forwardData ? - m_pcie_rd_outgoingBuffer_rv$port1__write_1 : - m_pcie_rd_outgoingBuffer_rv$port1__read ; - assign m_fpga_wr_master_wr_in_data_1_rv$EN_port0__write = - m_fpga_wr_master_wr_in_data_1_rv[578] && fpga_wr_wready ; - assign m_fpga_wr_master_wr_in_data_1_rv$port1__read = - m_fpga_wr_master_wr_in_data_1_rv$EN_port0__write ? - 579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - m_fpga_wr_master_wr_in_data_1_rv ; - assign m_fpga_wr_master_wr_in_data_1_rv$port1__write_1 = - { 1'd1, - m_fpga_wr_incomingBuffer_rv[511:0], - x_strb__h43525, - m_fpga_wr_beatsThisRequestCntr_22_EQ_m_fpga_wr_ETC___d924, - 1'd0 } ; - assign m_fpga_wr_master_wr_in_data_1_rv$port2__read = - WILL_FIRE_RL_m_fpga_wr_forwardData ? - m_fpga_wr_master_wr_in_data_1_rv$port1__write_1 : - m_fpga_wr_master_wr_in_data_1_rv$port1__read ; - assign m_fpga_wr_incomingBuffer_rv$port1__read = - WILL_FIRE_RL_m_fpga_wr_forwardData ? - 513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - m_fpga_wr_incomingBuffer_rv ; - assign m_fpga_wr_incomingBuffer_rv$EN_port1__write = - fpga_request_converter$dEMPTY_N && - !m_fpga_wr_incomingBuffer_rv$port1__read[512] ; - assign m_fpga_wr_incomingBuffer_rv$port1__write_1 = - { 1'd1, fpga_request_converter$dD_OUT } ; - assign m_fpga_wr_incomingBuffer_rv$port2__read = - m_fpga_wr_incomingBuffer_rv$EN_port1__write ? - m_fpga_wr_incomingBuffer_rv$port1__write_1 : - m_fpga_wr_incomingBuffer_rv$port1__read ; - assign m_fpga_rd_master_rd_out_1_rv$port1__read = - WILL_FIRE_RL_m_fpga_rd_forwardData ? - 518'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - m_fpga_rd_master_rd_out_1_rv ; - assign m_fpga_rd_master_rd_out_1_rv$EN_port1__write = - !m_fpga_rd_master_rd_out_1_rv$port1__read[517] && - fpga_rd_rvalid ; - assign m_fpga_rd_master_rd_out_1_rv$port1__write_1 = - { 1'd1, m_fpga_rd_master_rd_rinpkg$wget } ; - assign m_fpga_rd_master_rd_out_1_rv$port2__read = - m_fpga_rd_master_rd_out_1_rv$EN_port1__write ? - m_fpga_rd_master_rd_out_1_rv$port1__write_1 : - m_fpga_rd_master_rd_out_1_rv$port1__read ; - assign m_fpga_rd_outgoingBuffer_rv$EN_port0__write = - m_fpga_rd_outgoingBuffer_rv[512] && - fpga_response_converter$sFULL_N ; - assign m_fpga_rd_outgoingBuffer_rv$port1__read = - m_fpga_rd_outgoingBuffer_rv$EN_port0__write ? - 513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - m_fpga_rd_outgoingBuffer_rv ; - assign m_fpga_rd_outgoingBuffer_rv$port1__write_1 = - { 1'd1, m_fpga_rd_master_rd_out_1_rv[515:4] } ; - assign m_fpga_rd_outgoingBuffer_rv$port2__read = - WILL_FIRE_RL_m_fpga_rd_forwardData ? - m_fpga_rd_outgoingBuffer_rv$port1__write_1 : - m_fpga_rd_outgoingBuffer_rv$port1__read ; assign readIn_rv$port1__read = WILL_FIRE_RL_handleRead ? 193'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : @@ -3657,26 +3621,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, readConverter_bufferEmpty$EN_port1__write ? !WILL_FIRE_RL_mkConnectionGetPut_1 : readConverter_bufferEmpty$port1__read ; - assign byteAlignerReader_incoming_rv$port1__read = - WILL_FIRE_RL_byteAlignerReader_fetchNewData ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - byteAlignerReader_incoming_rv ; - assign byteAlignerReader_outgoing_rv$EN_port1__write = - WILL_FIRE_RL_byteAlignerReader_forwardOutput || - WILL_FIRE_RL_byteAlignerReader_forwardOutputLast ; - assign byteAlignerReader_outgoing_rv$port1__write_1 = - WILL_FIRE_RL_byteAlignerReader_forwardOutput ? - MUX_byteAlignerReader_outgoing_rv$port1__write_1__VAL_1 : - MUX_byteAlignerReader_outgoing_rv$port1__write_1__VAL_2 ; - assign byteAlignerReader_outgoing_rv$port2__read = - byteAlignerReader_outgoing_rv$EN_port1__write ? - byteAlignerReader_outgoing_rv$port1__write_1 : - byteAlignerReader_outgoing_rv ; assign byteAlignerReader_buffer$EN_port0__write = - WILL_FIRE_RL_byteAlignerReader_fetchNewData || + WILL_FIRE_RL_byteAlignerReader_forwardOutput || byteAlignerReader_addr_ff$dEMPTY_N ; assign byteAlignerReader_buffer$port0__write_1 = - WILL_FIRE_RL_byteAlignerReader_fetchNewData ? + WILL_FIRE_RL_byteAlignerReader_forwardOutput ? MUX_byteAlignerReader_buffer$port0__write_1__VAL_1 : 512'd0 ; assign byteAlignerReader_buffer$port1__read = @@ -3684,82 +3633,42 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerReader_buffer$port0__write_1 : byteAlignerReader_buffer ; assign byteAlignerReader_buffer$port1__write_1 = - { 256'd0, byteAlignerReader_buffer$port1__read[511:256] } ; + { byteAlignerReader_buffer$port1__read[511:256], + byteAlignerReader_incoming$D_OUT } ; assign byteAlignerReader_buffer$port2__read = - WILL_FIRE_RL_byteAlignerReader_forwardOutput ? + WILL_FIRE_RL_byteAlignerReader_fetchNewData ? byteAlignerReader_buffer$port1__write_1 : byteAlignerReader_buffer$port1__read ; assign byteAlignerReader_bytes_left_in_buffer$EN_port0__write = - WILL_FIRE_RL_byteAlignerReader_fetchNewData || + WILL_FIRE_RL_byteAlignerReader_forwardOutput || byteAlignerReader_addr_ff$dEMPTY_N ; assign byteAlignerReader_bytes_left_in_buffer$port0__write_1 = - WILL_FIRE_RL_byteAlignerReader_fetchNewData ? + WILL_FIRE_RL_byteAlignerReader_forwardOutput ? MUX_byteAlignerReader_bytes_left_in_buffer$port0__write_1__VAL_1 : 6'd0 ; assign byteAlignerReader_bytes_left_in_buffer$port1__write_1 = - b__h73043 - byteAlignerReader_bytes_out_needed ; + b__h70410 + 6'd32 ; assign byteAlignerReader_bytes_left_in_buffer$port2__read = - WILL_FIRE_RL_byteAlignerReader_forwardOutput ? + WILL_FIRE_RL_byteAlignerReader_fetchNewData ? byteAlignerReader_bytes_left_in_buffer$port1__write_1 : - b__h73043 ; + b__h70410 ; assign byteAlignerReader_fetchedDatum$EN_port0__write = byteAlignerReader_addr_ff$dEMPTY_N || - WILL_FIRE_RL_byteAlignerReader_fetchNewData ; - assign byteAlignerReader_fetchedDatum$port1__read = - byteAlignerReader_fetchedDatum$EN_port0__write ? - !byteAlignerReader_addr_ff$dEMPTY_N : - byteAlignerReader_fetchedDatum ; - assign byteAlignerReader_fetchedDatum$EN_port1__write = !byteAlignerReader_addr_ff$dEMPTY_N && - byteAlignerReader_fetchedDatum$port1__read && - byteAlignerReader_bytes_left_in_buffer_port1___ETC___d1472 || + byteAlignerReader_fetchedDatum && + byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 || WILL_FIRE_RL_byteAlignerReader_forwardOutput ; + assign byteAlignerReader_fetchedDatum$port1__read = + !byteAlignerReader_fetchedDatum$EN_port0__write && + byteAlignerReader_fetchedDatum ; assign byteAlignerReader_fetchedDatum$port2__read = - !byteAlignerReader_fetchedDatum$EN_port1__write && + WILL_FIRE_RL_byteAlignerReader_fetchNewData || byteAlignerReader_fetchedDatum$port1__read ; - assign writeConverter_dataSync_rv$EN_port0__write = - writeConverter_dataSync_rv[512] && - fpga_request_converter$sFULL_N ; - assign writeConverter_dataSync_rv$port1__read = - writeConverter_dataSync_rv$EN_port0__write ? - 513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - writeConverter_dataSync_rv ; - assign writeConverter_dataSync_rv$EN_port1__write = - WILL_FIRE_RL_mkConnectionGetPut_3 && - (writeConverter_wordInCntr == 2'd1 || - writeConverter_byteCntr <= 64'd32) ; - assign writeConverter_dataSync_rv$port1__write_1 = - { 1'd1, - (writeConverter_wordInCntr == 2'd1) ? - m_pcie_rd_outgoingBuffer_rv[255:0] : - 256'd0, - (writeConverter_wordInCntr == 2'd0) ? - m_pcie_rd_outgoingBuffer_rv[255:0] : - writeConverter_buffer_0 } ; - assign writeConverter_dataSync_rv$port2__read = - writeConverter_dataSync_rv$EN_port1__write ? - writeConverter_dataSync_rv$port1__write_1 : - writeConverter_dataSync_rv$port1__read ; - assign byteAlignerWriter_incoming_rv$port1__read = - WILL_FIRE_RL_byteAlignerWriter_fetchNewData ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - byteAlignerWriter_incoming_rv ; - assign byteAlignerWriter_outgoing_rv$EN_port1__write = - WILL_FIRE_RL_byteAlignerWriter_forwardOutput || - WILL_FIRE_RL_byteAlignerWriter_forwardOutputLast ; - assign byteAlignerWriter_outgoing_rv$port1__write_1 = - WILL_FIRE_RL_byteAlignerWriter_forwardOutput ? - MUX_byteAlignerWriter_outgoing_rv$port1__write_1__VAL_1 : - MUX_byteAlignerWriter_outgoing_rv$port1__write_1__VAL_2 ; - assign byteAlignerWriter_outgoing_rv$port2__read = - byteAlignerWriter_outgoing_rv$EN_port1__write ? - byteAlignerWriter_outgoing_rv$port1__write_1 : - byteAlignerWriter_outgoing_rv ; assign byteAlignerWriter_buffer$EN_port0__write = - WILL_FIRE_RL_byteAlignerWriter_fetchNewData || + WILL_FIRE_RL_byteAlignerWriter_forwardOutput || byteAlignerWriter_addr_ff$dEMPTY_N ; assign byteAlignerWriter_buffer$port0__write_1 = - WILL_FIRE_RL_byteAlignerWriter_fetchNewData ? + WILL_FIRE_RL_byteAlignerWriter_forwardOutput ? MUX_byteAlignerWriter_buffer$port0__write_1__VAL_1 : 512'd0 ; assign byteAlignerWriter_buffer$port1__read = @@ -3767,38 +3676,36 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_buffer$port0__write_1 : byteAlignerWriter_buffer ; assign byteAlignerWriter_buffer$port1__write_1 = - { 256'd0, byteAlignerWriter_buffer$port1__read[511:256] } ; + { byteAlignerWriter_buffer$port1__read[511:256], + byteAlignerWriter_incoming$D_OUT } ; assign byteAlignerWriter_buffer$port2__read = - WILL_FIRE_RL_byteAlignerWriter_forwardOutput ? + WILL_FIRE_RL_byteAlignerWriter_fetchNewData ? byteAlignerWriter_buffer$port1__write_1 : byteAlignerWriter_buffer$port1__read ; assign byteAlignerWriter_bytes_left_in_buffer$EN_port0__write = - WILL_FIRE_RL_byteAlignerWriter_fetchNewData || + WILL_FIRE_RL_byteAlignerWriter_forwardOutput || byteAlignerWriter_addr_ff$dEMPTY_N ; assign byteAlignerWriter_bytes_left_in_buffer$port0__write_1 = - WILL_FIRE_RL_byteAlignerWriter_fetchNewData ? + WILL_FIRE_RL_byteAlignerWriter_forwardOutput ? MUX_byteAlignerWriter_bytes_left_in_buffer$port0__write_1__VAL_1 : 6'd0 ; assign byteAlignerWriter_bytes_left_in_buffer$port1__write_1 = - b__h117504 - byteAlignerWriter_bytes_out_needed ; + b__h113489 + 6'd32 ; assign byteAlignerWriter_bytes_left_in_buffer$port2__read = - WILL_FIRE_RL_byteAlignerWriter_forwardOutput ? + WILL_FIRE_RL_byteAlignerWriter_fetchNewData ? byteAlignerWriter_bytes_left_in_buffer$port1__write_1 : - b__h117504 ; + b__h113489 ; assign byteAlignerWriter_fetchedDatum$EN_port0__write = byteAlignerWriter_addr_ff$dEMPTY_N || - WILL_FIRE_RL_byteAlignerWriter_fetchNewData ; - assign byteAlignerWriter_fetchedDatum$port1__read = - byteAlignerWriter_fetchedDatum$EN_port0__write ? - !byteAlignerWriter_addr_ff$dEMPTY_N : - byteAlignerWriter_fetchedDatum ; - assign byteAlignerWriter_fetchedDatum$EN_port1__write = !byteAlignerWriter_addr_ff$dEMPTY_N && - byteAlignerWriter_fetchedDatum$port1__read && - byteAlignerWriter_bytes_left_in_buffer_port1___ETC___d1601 || + byteAlignerWriter_fetchedDatum && + byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1576 || WILL_FIRE_RL_byteAlignerWriter_forwardOutput ; + assign byteAlignerWriter_fetchedDatum$port1__read = + !byteAlignerWriter_fetchedDatum$EN_port0__write && + byteAlignerWriter_fetchedDatum ; assign byteAlignerWriter_fetchedDatum$port2__read = - !byteAlignerWriter_fetchedDatum$EN_port1__write && + WILL_FIRE_RL_byteAlignerWriter_fetchNewData || byteAlignerWriter_fetchedDatum$port1__read ; // register byteAlignerReader_buffer @@ -3865,16 +3772,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerReader_fetchedDatum$port2__read ; assign byteAlignerReader_fetchedDatum$EN = 1'b1 ; - // register byteAlignerReader_incoming_rv - assign byteAlignerReader_incoming_rv$D_IN = - byteAlignerReader_incoming_rv$port1__read ; - assign byteAlignerReader_incoming_rv$EN = 1'b1 ; - - // register byteAlignerReader_outgoing_rv - assign byteAlignerReader_outgoing_rv$D_IN = - byteAlignerReader_outgoing_rv$port2__read ; - assign byteAlignerReader_outgoing_rv$EN = 1'b1 ; - // register byteAlignerWriter_buffer assign byteAlignerWriter_buffer$D_IN = byteAlignerWriter_buffer$port2__read ; @@ -3939,16 +3836,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_fetchedDatum$port2__read ; assign byteAlignerWriter_fetchedDatum$EN = 1'b1 ; - // register byteAlignerWriter_incoming_rv - assign byteAlignerWriter_incoming_rv$D_IN = - byteAlignerWriter_incoming_rv$port1__read ; - assign byteAlignerWriter_incoming_rv$EN = 1'b1 ; - - // register byteAlignerWriter_outgoing_rv - assign byteAlignerWriter_outgoing_rv$D_IN = - byteAlignerWriter_outgoing_rv$port2__read ; - assign byteAlignerWriter_outgoing_rv$EN = 1'b1 ; - // register doneInterruptReg assign doneInterruptReg$D_IN = WILL_FIRE_RL_setInterrupt ; assign doneInterruptReg$EN = 1'd1 ; @@ -4043,16 +3930,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_fpga_rd_lastPut$D_IN = 32'h0 ; assign m_fpga_rd_lastPut$EN = 1'b0 ; - // register m_fpga_rd_master_rd_out_1_rv - assign m_fpga_rd_master_rd_out_1_rv$D_IN = - m_fpga_rd_master_rd_out_1_rv$port2__read ; - assign m_fpga_rd_master_rd_out_1_rv$EN = 1'b1 ; - - // register m_fpga_rd_outgoingBuffer_rv - assign m_fpga_rd_outgoingBuffer_rv$D_IN = - m_fpga_rd_outgoingBuffer_rv$port2__read ; - assign m_fpga_rd_outgoingBuffer_rv$EN = 1'b1 ; - // register m_fpga_rd_putDelay assign m_fpga_rd_putDelay$D_IN = 32'h0 ; assign m_fpga_rd_putDelay$EN = 1'b0 ; @@ -4092,20 +3969,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_fpga_wr_clkCntr$D_IN = m_fpga_wr_clkCntr + 32'd1 ; assign m_fpga_wr_clkCntr$EN = 1'd1 ; - // register m_fpga_wr_incomingBuffer_rv - assign m_fpga_wr_incomingBuffer_rv$D_IN = - m_fpga_wr_incomingBuffer_rv$port2__read ; - assign m_fpga_wr_incomingBuffer_rv$EN = 1'b1 ; - // register m_fpga_wr_lastPut assign m_fpga_wr_lastPut$D_IN = 32'h0 ; assign m_fpga_wr_lastPut$EN = 1'b0 ; - // register m_fpga_wr_master_wr_in_data_1_rv - assign m_fpga_wr_master_wr_in_data_1_rv$D_IN = - m_fpga_wr_master_wr_in_data_1_rv$port2__read ; - assign m_fpga_wr_master_wr_in_data_1_rv$EN = 1'b1 ; - // register m_fpga_wr_putDelay assign m_fpga_wr_putDelay$D_IN = 32'h0 ; assign m_fpga_wr_putDelay$EN = 1'b0 ; @@ -4140,16 +4007,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_pcie_rd_lastPut$D_IN = 32'h0 ; assign m_pcie_rd_lastPut$EN = 1'b0 ; - // register m_pcie_rd_master_rd_out_1_rv - assign m_pcie_rd_master_rd_out_1_rv$D_IN = - m_pcie_rd_master_rd_out_1_rv$port2__read ; - assign m_pcie_rd_master_rd_out_1_rv$EN = 1'b1 ; - - // register m_pcie_rd_outgoingBuffer_rv - assign m_pcie_rd_outgoingBuffer_rv$D_IN = - m_pcie_rd_outgoingBuffer_rv$port2__read ; - assign m_pcie_rd_outgoingBuffer_rv$EN = 1'b1 ; - // register m_pcie_rd_putDelay assign m_pcie_rd_putDelay$D_IN = 32'h0 ; assign m_pcie_rd_putDelay$EN = 1'b0 ; @@ -4189,20 +4046,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_pcie_wr_clkCntr$D_IN = m_pcie_wr_clkCntr + 32'd1 ; assign m_pcie_wr_clkCntr$EN = 1'd1 ; - // register m_pcie_wr_incomingBuffer_rv - assign m_pcie_wr_incomingBuffer_rv$D_IN = - m_pcie_wr_incomingBuffer_rv$port2__read ; - assign m_pcie_wr_incomingBuffer_rv$EN = 1'b1 ; - // register m_pcie_wr_lastPut assign m_pcie_wr_lastPut$D_IN = 32'h0 ; assign m_pcie_wr_lastPut$EN = 1'b0 ; - // register m_pcie_wr_master_wr_in_data_1_rv - assign m_pcie_wr_master_wr_in_data_1_rv$D_IN = - m_pcie_wr_master_wr_in_data_1_rv$port2__read ; - assign m_pcie_wr_master_wr_in_data_1_rv$EN = 1'b1 ; - // register m_pcie_wr_putDelay assign m_pcie_wr_putDelay$D_IN = 32'h0 ; assign m_pcie_wr_putDelay$EN = 1'b0 ; @@ -4323,7 +4170,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign transfer_length$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 ; // register writeConverter_buffer_0 - assign writeConverter_buffer_0$D_IN = m_pcie_rd_outgoingBuffer_rv[255:0] ; + assign writeConverter_buffer_0$D_IN = m_pcie_rd_outgoingBuffer$D_OUT ; assign writeConverter_buffer_0$EN = WILL_FIRE_RL_mkConnectionGetPut_3 && writeConverter_wordInCntr == 2'd0 ; @@ -4336,11 +4183,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign writeConverter_byteCntr$EN = writeConvBTT_ff$dEMPTY_N || WILL_FIRE_RL_mkConnectionGetPut_3 ; - // register writeConverter_dataSync_rv - assign writeConverter_dataSync_rv$D_IN = - writeConverter_dataSync_rv$port2__read ; - assign writeConverter_dataSync_rv$EN = 1'b1 ; - // register writeConverter_wordInCntr assign writeConverter_wordInCntr$D_IN = writeConvBTT_ff$dEMPTY_N ? @@ -4366,11 +4208,41 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign byteAlignerReader_addr_ff$sENQ = 1'b0 ; assign byteAlignerReader_addr_ff$dDEQ = byteAlignerReader_addr_ff$dEMPTY_N ; + // submodule byteAlignerReader_incoming + assign byteAlignerReader_incoming$D_IN = 256'h0 ; + assign byteAlignerReader_incoming$ENQ = 1'b0 ; + assign byteAlignerReader_incoming$DEQ = + WILL_FIRE_RL_byteAlignerReader_fetchNewData ; + assign byteAlignerReader_incoming$CLR = 1'b0 ; + + // submodule byteAlignerReader_outgoing + assign byteAlignerReader_outgoing$D_IN = byteAlignerReader_buffer[255:0] ; + assign byteAlignerReader_outgoing$ENQ = + WILL_FIRE_RL_byteAlignerReader_forwardOutputLast || + WILL_FIRE_RL_byteAlignerReader_forwardOutput ; + assign byteAlignerReader_outgoing$DEQ = 1'b0 ; + assign byteAlignerReader_outgoing$CLR = 1'b0 ; + // submodule byteAlignerWriter_addr_ff assign byteAlignerWriter_addr_ff$sD_IN = 192'h0 ; assign byteAlignerWriter_addr_ff$sENQ = 1'b0 ; assign byteAlignerWriter_addr_ff$dDEQ = byteAlignerWriter_addr_ff$dEMPTY_N ; + // submodule byteAlignerWriter_incoming + assign byteAlignerWriter_incoming$D_IN = 256'h0 ; + assign byteAlignerWriter_incoming$ENQ = 1'b0 ; + assign byteAlignerWriter_incoming$DEQ = + WILL_FIRE_RL_byteAlignerWriter_fetchNewData ; + assign byteAlignerWriter_incoming$CLR = 1'b0 ; + + // submodule byteAlignerWriter_outgoing + assign byteAlignerWriter_outgoing$D_IN = byteAlignerWriter_buffer[255:0] ; + assign byteAlignerWriter_outgoing$ENQ = + WILL_FIRE_RL_byteAlignerWriter_forwardOutputLast || + WILL_FIRE_RL_byteAlignerWriter_forwardOutput ; + assign byteAlignerWriter_outgoing$DEQ = 1'b0 ; + assign byteAlignerWriter_outgoing$CLR = 1'b0 ; + // submodule cmdsIn assign cmdsIn$D_IN = s_config_writeSlave_in$D_OUT[74:11] != 64'h0000000010001000 ; @@ -4387,7 +4259,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign fpgaDone$sD_IN = 1'd1 ; assign fpgaDone$sENQ = fpgaDone$sFULL_N && - fpgaLastCycle_703_AND_m_fpga_rd_task_data_outp_ETC___d1705 ; + fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672 ; assign fpgaDone$dDEQ = WILL_FIRE_RL_setInterrupt ; // submodule fpga_get_delay @@ -4399,19 +4271,19 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign fpga_read_4kbarriers$sEN = fpga_read_4kbarriers$sRDY ; // submodule fpga_request_converter - assign fpga_request_converter$sD_IN = writeConverter_dataSync_rv[511:0] ; + assign fpga_request_converter$sD_IN = writeConverter_dataSync$D_OUT ; assign fpga_request_converter$sENQ = - writeConverter_dataSync_rv[512] && - fpga_request_converter$sFULL_N ; + fpga_request_converter$sFULL_N && + writeConverter_dataSync$EMPTY_N ; assign fpga_request_converter$dDEQ = fpga_request_converter$dEMPTY_N && - !m_fpga_wr_incomingBuffer_rv$port1__read[512] ; + m_fpga_wr_incomingBuffer$FULL_N ; // submodule fpga_response_converter - assign fpga_response_converter$sD_IN = m_fpga_rd_outgoingBuffer_rv[511:0] ; + assign fpga_response_converter$sD_IN = m_fpga_rd_outgoingBuffer$D_OUT ; assign fpga_response_converter$sENQ = - m_fpga_rd_outgoingBuffer_rv[512] && - fpga_response_converter$sFULL_N ; + fpga_response_converter$sFULL_N && + m_fpga_rd_outgoingBuffer$EMPTY_N ; assign fpga_response_converter$dDEQ = WILL_FIRE_RL_mkConnectionGetPut_1 ; // submodule fpga_write_4kbarriers @@ -4432,7 +4304,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_rd_task_data_requests_reg[67:4], (m_fpga_rd_task_data_requests_reg[125:68] == 58'd1 && m_fpga_rd_task_data_requests_reg[133:126] != 8'd0) ? - beatsThisRequest___1__h57832 : + beatsThisRequest___1__h55895 : 8'd255, 17'd102784, m_fpga_rd_task_data_requests_reg[3:0], @@ -4443,11 +4315,21 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_fpga_rd_master_rd_in$CLR = 1'b0 ; // submodule m_fpga_rd_master_rd_out - assign m_fpga_rd_master_rd_out$D_IN = 517'h0 ; - assign m_fpga_rd_master_rd_out$ENQ = 1'b0 ; - assign m_fpga_rd_master_rd_out$DEQ = 1'b0 ; + assign m_fpga_rd_master_rd_out$D_IN = m_fpga_rd_master_rd_rinpkg$wget ; + assign m_fpga_rd_master_rd_out$ENQ = + m_fpga_rd_master_rd_out$FULL_N && fpga_rd_rvalid ; + assign m_fpga_rd_master_rd_out$DEQ = WILL_FIRE_RL_m_fpga_rd_forwardData ; assign m_fpga_rd_master_rd_out$CLR = 1'b0 ; + // submodule m_fpga_rd_outgoingBuffer + assign m_fpga_rd_outgoingBuffer$D_IN = + m_fpga_rd_master_rd_out$D_OUT[515:4] ; + assign m_fpga_rd_outgoingBuffer$ENQ = WILL_FIRE_RL_m_fpga_rd_forwardData ; + assign m_fpga_rd_outgoingBuffer$DEQ = + fpga_response_converter$sFULL_N && + m_fpga_rd_outgoingBuffer$EMPTY_N ; + assign m_fpga_rd_outgoingBuffer$CLR = 1'b0 ; + // submodule m_fpga_rd_reqGen_incomingBuffer assign m_fpga_rd_reqGen_incomingBuffer$D_IN = mclk_m_fpga_put_req_rd_ff$dD_OUT ; @@ -4461,8 +4343,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_rd_reqGen_intermediateBuffer assign m_fpga_rd_reqGen_intermediateBuffer$D_IN = - { x__h55148[5:0], - m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7[5:0], + { x__h53483[5:0], + m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6[5:0], m_fpga_rd_reqGen_incomingBuffer$D_OUT } ; assign m_fpga_rd_reqGen_intermediateBuffer$ENQ = m_fpga_rd_reqGen_incomingBuffer$EMPTY_N && @@ -4475,7 +4357,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_rd_reqGen_intermediateBuffer2 assign m_fpga_rd_reqGen_intermediateBuffer2$D_IN = { m_fpga_rd_reqGen_intermediateBuffer$D_OUT[143:132], - x__h55329[57:0], + x__h53664[57:0], m_fpga_rd_reqGen_intermediateBuffer$D_OUT[131:0] } ; assign m_fpga_rd_reqGen_intermediateBuffer2$ENQ = m_fpga_rd_reqGen_intermediateBuffer$EMPTY_N && @@ -4487,8 +4369,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_rd_reqGen_outgoingBuffer assign m_fpga_rd_reqGen_outgoingBuffer$D_IN = { m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[139:132], - request_data_requests_total__h55466, - request_data_address__h55467, + request_data_requests_total__h53801, + request_data_address__h53802, m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[3:0], m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[201:132], m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[73:68], @@ -4500,19 +4382,27 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_fpga_rd_reqGen_outgoingBuffer$CLR = 1'b0 ; // submodule m_fpga_wr_beatsPerRequestFIFO - assign m_fpga_wr_beatsPerRequestFIFO$D_IN = _theResult____h42825 ; + assign m_fpga_wr_beatsPerRequestFIFO$D_IN = _theResult____h41256 ; assign m_fpga_wr_beatsPerRequestFIFO$ENQ = WILL_FIRE_RL_m_fpga_wr_placeRequest ; assign m_fpga_wr_beatsPerRequestFIFO$DEQ = WILL_FIRE_RL_m_fpga_wr_forwardData && - m_fpga_wr_beatsThisRequestCntr_22_EQ_m_fpga_wr_ETC___d924 ; + m_fpga_wr_beatsThisRequestCntr_13_EQ_m_fpga_wr_ETC___d915 ; assign m_fpga_wr_beatsPerRequestFIFO$CLR = 1'b0 ; + // submodule m_fpga_wr_incomingBuffer + assign m_fpga_wr_incomingBuffer$D_IN = fpga_request_converter$dD_OUT ; + assign m_fpga_wr_incomingBuffer$ENQ = + fpga_request_converter$dEMPTY_N && + m_fpga_wr_incomingBuffer$FULL_N ; + assign m_fpga_wr_incomingBuffer$DEQ = WILL_FIRE_RL_m_fpga_wr_forwardData ; + assign m_fpga_wr_incomingBuffer$CLR = 1'b0 ; + // submodule m_fpga_wr_master_wr_in_addr assign m_fpga_wr_master_wr_in_addr$D_IN = { 1'd0, m_fpga_wr_task_data_requests_reg[67:4], - _theResult____h42825, + _theResult____h41256, 17'd102784, m_fpga_wr_task_data_requests_reg[3:0], 1'd0 } ; @@ -4523,9 +4413,15 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_fpga_wr_master_wr_in_addr$CLR = 1'b0 ; // submodule m_fpga_wr_master_wr_in_data - assign m_fpga_wr_master_wr_in_data$D_IN = 578'h0 ; - assign m_fpga_wr_master_wr_in_data$ENQ = 1'b0 ; - assign m_fpga_wr_master_wr_in_data$DEQ = 1'b0 ; + assign m_fpga_wr_master_wr_in_data$D_IN = + { m_fpga_wr_incomingBuffer$D_OUT, + x_strb__h41878, + m_fpga_wr_beatsThisRequestCntr_13_EQ_m_fpga_wr_ETC___d915, + 1'd0 } ; + assign m_fpga_wr_master_wr_in_data$ENQ = + WILL_FIRE_RL_m_fpga_wr_forwardData ; + assign m_fpga_wr_master_wr_in_data$DEQ = + m_fpga_wr_master_wr_in_data$EMPTY_N && fpga_wr_wready ; assign m_fpga_wr_master_wr_in_data$CLR = 1'b0 ; // submodule m_fpga_wr_master_wr_out @@ -4548,8 +4444,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_reqGen_intermediateBuffer assign m_fpga_wr_reqGen_intermediateBuffer$D_IN = - { x__h39245[5:0], - m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8[5:0], + { x__h38136[5:0], + m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7[5:0], m_fpga_wr_reqGen_incomingBuffer$D_OUT } ; assign m_fpga_wr_reqGen_intermediateBuffer$ENQ = m_fpga_wr_reqGen_incomingBuffer$EMPTY_N && @@ -4562,7 +4458,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_reqGen_intermediateBuffer2 assign m_fpga_wr_reqGen_intermediateBuffer2$D_IN = { m_fpga_wr_reqGen_intermediateBuffer$D_OUT[143:132], - x__h39426[57:0], + x__h38317[57:0], m_fpga_wr_reqGen_intermediateBuffer$D_OUT[131:0] } ; assign m_fpga_wr_reqGen_intermediateBuffer2$ENQ = m_fpga_wr_reqGen_intermediateBuffer$EMPTY_N && @@ -4574,8 +4470,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_reqGen_outgoingBuffer assign m_fpga_wr_reqGen_outgoingBuffer$D_IN = { m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[139:132], - request_data_requests_total__h39563, - request_data_address__h39564, + request_data_requests_total__h38454, + request_data_address__h38455, m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[3:0], m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[201:132], m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[73:68], @@ -4592,8 +4488,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_rd_task_data_requests_reg[67:4], (m_pcie_rd_task_data_requests_reg[126:68] == 59'd1 && m_pcie_rd_task_data_requests_reg[134:127] != 8'd0) ? - beatsThisRequest___1__h37490 : - 8'd15, + beatsThisRequest___1__h36662 : + 8'd63, 17'd86400, m_pcie_rd_task_data_requests_reg[3:0], 1'd0 } ; @@ -4603,11 +4499,19 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_pcie_rd_master_rd_in$CLR = 1'b0 ; // submodule m_pcie_rd_master_rd_out - assign m_pcie_rd_master_rd_out$D_IN = 261'h0 ; - assign m_pcie_rd_master_rd_out$ENQ = 1'b0 ; - assign m_pcie_rd_master_rd_out$DEQ = 1'b0 ; + assign m_pcie_rd_master_rd_out$D_IN = m_pcie_rd_master_rd_rinpkg$wget ; + assign m_pcie_rd_master_rd_out$ENQ = + m_pcie_rd_master_rd_out$FULL_N && pcie_rd_rvalid ; + assign m_pcie_rd_master_rd_out$DEQ = WILL_FIRE_RL_m_pcie_rd_forwardData ; assign m_pcie_rd_master_rd_out$CLR = 1'b0 ; + // submodule m_pcie_rd_outgoingBuffer + assign m_pcie_rd_outgoingBuffer$D_IN = + m_pcie_rd_master_rd_out$D_OUT[259:4] ; + assign m_pcie_rd_outgoingBuffer$ENQ = WILL_FIRE_RL_m_pcie_rd_forwardData ; + assign m_pcie_rd_outgoingBuffer$DEQ = WILL_FIRE_RL_mkConnectionGetPut_3 ; + assign m_pcie_rd_outgoingBuffer$CLR = 1'b0 ; + // submodule m_pcie_rd_reqGen_incomingBuffer assign m_pcie_rd_reqGen_incomingBuffer$D_IN = mclk_m_pcie_put_req_rd_ff$dD_OUT ; @@ -4621,8 +4525,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_reqGen_intermediateBuffer assign m_pcie_rd_reqGen_intermediateBuffer$D_IN = - { x__h34803[4:0], - m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9[4:0], + { x__h34247[4:0], + m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8[4:0], m_pcie_rd_reqGen_incomingBuffer$D_OUT } ; assign m_pcie_rd_reqGen_intermediateBuffer$ENQ = m_pcie_rd_reqGen_incomingBuffer$EMPTY_N && @@ -4635,7 +4539,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_reqGen_intermediateBuffer2 assign m_pcie_rd_reqGen_intermediateBuffer2$D_IN = { m_pcie_rd_reqGen_intermediateBuffer$D_OUT[141:132], - x__h34984[58:0], + x__h34428[58:0], m_pcie_rd_reqGen_intermediateBuffer$D_OUT[131:0] } ; assign m_pcie_rd_reqGen_intermediateBuffer2$ENQ = m_pcie_rd_reqGen_intermediateBuffer$EMPTY_N && @@ -4646,9 +4550,9 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_reqGen_outgoingBuffer assign m_pcie_rd_reqGen_outgoingBuffer$D_IN = - { requests_last__h35084, - request_data_requests_total__h35121, - request_data_address__h35122, + { requests_last__h34528, + request_data_requests_total__h34565, + request_data_address__h34566, m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[3:0], m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[200:132], m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[72:68], @@ -4660,19 +4564,31 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_pcie_rd_reqGen_outgoingBuffer$CLR = 1'b0 ; // submodule m_pcie_wr_beatsPerRequestFIFO - assign m_pcie_wr_beatsPerRequestFIFO$D_IN = _theResult____h27888 ; + assign m_pcie_wr_beatsPerRequestFIFO$D_IN = _theResult____h27428 ; assign m_pcie_wr_beatsPerRequestFIFO$ENQ = WILL_FIRE_RL_m_pcie_wr_placeRequest ; assign m_pcie_wr_beatsPerRequestFIFO$DEQ = WILL_FIRE_RL_m_pcie_wr_forwardData && - m_pcie_wr_beatsThisRequestCntr_30_EQ_m_pcie_wr_ETC___d432 ; + m_pcie_wr_beatsThisRequestCntr_28_EQ_m_pcie_wr_ETC___d430 ; assign m_pcie_wr_beatsPerRequestFIFO$CLR = 1'b0 ; + // submodule m_pcie_wr_incomingBuffer + always@(readConverter_wordInCntr or readConverter_buffer) + begin + case (readConverter_wordInCntr) + 1'd0: m_pcie_wr_incomingBuffer$D_IN = readConverter_buffer[255:0]; + 1'd1: m_pcie_wr_incomingBuffer$D_IN = readConverter_buffer[511:256]; + endcase + end + assign m_pcie_wr_incomingBuffer$ENQ = WILL_FIRE_RL_mkConnectionGetPut_2 ; + assign m_pcie_wr_incomingBuffer$DEQ = WILL_FIRE_RL_m_pcie_wr_forwardData ; + assign m_pcie_wr_incomingBuffer$CLR = 1'b0 ; + // submodule m_pcie_wr_master_wr_in_addr assign m_pcie_wr_master_wr_in_addr$D_IN = { 1'd0, m_pcie_wr_task_data_requests_reg[67:4], - _theResult____h27888, + _theResult____h27428, 17'd86400, m_pcie_wr_task_data_requests_reg[3:0], 1'd0 } ; @@ -4683,9 +4599,15 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_pcie_wr_master_wr_in_addr$CLR = 1'b0 ; // submodule m_pcie_wr_master_wr_in_data - assign m_pcie_wr_master_wr_in_data$D_IN = 290'h0 ; - assign m_pcie_wr_master_wr_in_data$ENQ = 1'b0 ; - assign m_pcie_wr_master_wr_in_data$DEQ = 1'b0 ; + assign m_pcie_wr_master_wr_in_data$D_IN = + { m_pcie_wr_incomingBuffer$D_OUT, + x_strb__h28050, + m_pcie_wr_beatsThisRequestCntr_28_EQ_m_pcie_wr_ETC___d430, + 1'd0 } ; + assign m_pcie_wr_master_wr_in_data$ENQ = + WILL_FIRE_RL_m_pcie_wr_forwardData ; + assign m_pcie_wr_master_wr_in_data$DEQ = + m_pcie_wr_master_wr_in_data$EMPTY_N && pcie_wr_wready ; assign m_pcie_wr_master_wr_in_data$CLR = 1'b0 ; // submodule m_pcie_wr_master_wr_out @@ -4709,7 +4631,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_wr_reqGen_intermediateBuffer assign m_pcie_wr_reqGen_intermediateBuffer$D_IN = { x__h24293[4:0], - m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q10[4:0], + m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9[4:0], m_pcie_wr_reqGen_incomingBuffer$D_OUT } ; assign m_pcie_wr_reqGen_intermediateBuffer$ENQ = m_pcie_wr_reqGen_incomingBuffer$EMPTY_N && @@ -4780,7 +4702,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign pcieDone$sD_IN = 1'd1 ; assign pcieDone$sENQ = pcieDone$sFULL_N && - pcieLastCycle_696_AND_m_pcie_rd_task_data_outp_ETC___d1698 ; + pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665 ; assign pcieDone$dDEQ = WILL_FIRE_RL_setInterrupt ; // submodule pcie_put_delay @@ -4796,7 +4718,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign pcie_write_4kbarriers$sEN = pcie_write_4kbarriers$sRDY ; // submodule readConvBTT_ff - assign readConvBTT_ff$sD_IN = { btt__h103430, readIn_rv[69] } ; + assign readConvBTT_ff$sD_IN = { btt__h100105, readIn_rv[69] } ; assign readConvBTT_ff$sENQ = WILL_FIRE_RL_handleRead ; assign readConvBTT_ff$dDEQ = readConvBTT_ff$dEMPTY_N ; @@ -4980,33 +4902,50 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign s_config_writeSlave_out$CLR = 1'b0 ; // submodule writeConvBTT_ff - assign writeConvBTT_ff$sD_IN = { btt__h147854, writeIn_rv[69] } ; + assign writeConvBTT_ff$sD_IN = { btt__h143147, writeIn_rv[69] } ; assign writeConvBTT_ff$sENQ = WILL_FIRE_RL_handleWrite ; assign writeConvBTT_ff$dDEQ = writeConvBTT_ff$dEMPTY_N ; + // submodule writeConverter_dataSync + assign writeConverter_dataSync$D_IN = + { (writeConverter_wordInCntr == 2'd1) ? + m_pcie_rd_outgoingBuffer$D_OUT : + 256'd0, + (writeConverter_wordInCntr == 2'd0) ? + m_pcie_rd_outgoingBuffer$D_OUT : + writeConverter_buffer_0 } ; + assign writeConverter_dataSync$ENQ = + WILL_FIRE_RL_mkConnectionGetPut_3 && + (writeConverter_wordInCntr == 2'd1 || + writeConverter_byteCntr <= 64'd32) ; + assign writeConverter_dataSync$DEQ = + fpga_request_converter$sFULL_N && + writeConverter_dataSync$EMPTY_N ; + assign writeConverter_dataSync$CLR = 1'b0 ; + // remaining internal signals assign IF_0_CONCAT_readConverter_wordInCntr_EQ_1_OR_r_ETC__q1 = ({ 1'd0, readConverter_wordInCntr } == 2'd1 || readConverter_byteCntr <= 64'd32) ? 2'd0 : { 1'd0, readConverter_wordInCntr } + 2'd1 ; - assign IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 = + assign IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 = (m_fpga_wr_task_data_output_reg[0] && m_fpga_wr_task_data_output_reg[76:71] != 6'd0) ? - endByte___1__h46449 : + endByte___1__h44787 : ((m_fpga_wr_task_data_output_reg[64:7] == 58'd1) ? ((m_fpga_wr_task_data_output_reg[70:65] == 6'd0) ? 7'd64 : - endByte___1__h46475) : + endByte___1__h44813) : 7'd64) ; - assign IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 = + assign IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 = (m_pcie_wr_task_data_output_reg[0] && m_pcie_wr_task_data_output_reg[74:70] != 5'd0) ? - endByte___1__h30104 : + endByte___1__h29551 : ((m_pcie_wr_task_data_output_reg[64:6] == 59'd1) ? ((m_pcie_wr_task_data_output_reg[69:65] == 5'd0) ? 6'd32 : - endByte___1__h30130) : + endByte___1__h29577) : 6'd32) ; assign _theResult____h24288 = (m_pcie_wr_reqGen_incomingBuffer$D_OUT[72:68] == 5'd0) ? @@ -5016,172 +4955,174 @@ module mkBlueDMA(CLK_m32_axi_aclk, (m_pcie_wr_reqGen_intermediateBuffer$D_OUT[141:137] == 5'd0) ? transfers_total__h24471 : transfers_total___1__h24480 ; - assign _theResult____h27888 = + assign _theResult____h27428 = (m_pcie_wr_task_data_requests_reg[126:68] == 59'd1 && m_pcie_wr_task_data_requests_reg[134:127] != 8'd0) ? - beatsThisRequest___1__h27936 : - 8'd15 ; - assign _theResult____h34798 = + beatsThisRequest___1__h27476 : + 8'd63 ; + assign _theResult____h34242 = (m_pcie_rd_reqGen_incomingBuffer$D_OUT[72:68] == 5'd0) ? - bytes_first__h34797 : - bytes_first___1__h34833 ; - assign _theResult____h34982 = + bytes_first__h34241 : + bytes_first___1__h34277 ; + assign _theResult____h34426 = (m_pcie_rd_reqGen_intermediateBuffer$D_OUT[141:137] == 5'd0) ? - transfers_total__h34981 : - transfers_total___1__h34990 ; - assign _theResult____h39240 = + transfers_total__h34425 : + transfers_total___1__h34434 ; + assign _theResult____h38131 = (m_fpga_wr_reqGen_incomingBuffer$D_OUT[73:68] == 6'd0) ? - bytes_first__h39239 : - bytes_first___1__h39275 ; - assign _theResult____h39424 = + bytes_first__h38130 : + bytes_first___1__h38166 ; + assign _theResult____h38315 = (m_fpga_wr_reqGen_intermediateBuffer$D_OUT[143:138] == 6'd0) ? - transfers_total__h39423 : - transfers_total___1__h39432 ; - assign _theResult____h42825 = + transfers_total__h38314 : + transfers_total___1__h38323 ; + assign _theResult____h41256 = (m_fpga_wr_task_data_requests_reg[125:68] == 58'd1 && m_fpga_wr_task_data_requests_reg[133:126] != 8'd0) ? - beatsThisRequest___1__h42873 : + beatsThisRequest___1__h41304 : 8'd255 ; - assign _theResult____h55143 = + assign _theResult____h53478 = (m_fpga_rd_reqGen_incomingBuffer$D_OUT[73:68] == 6'd0) ? - bytes_first__h55142 : - bytes_first___1__h55178 ; - assign _theResult____h55327 = + bytes_first__h53477 : + bytes_first___1__h53513 ; + assign _theResult____h53662 = (m_fpga_rd_reqGen_intermediateBuffer$D_OUT[143:138] == 6'd0) ? - transfers_total__h55326 : - transfers_total___1__h55335 ; - assign b__h117504 = + transfers_total__h53661 : + transfers_total___1__h53670 ; + assign b__h113489 = byteAlignerWriter_bytes_left_in_buffer$EN_port0__write ? byteAlignerWriter_bytes_left_in_buffer$port0__write_1 : byteAlignerWriter_bytes_left_in_buffer ; - assign b__h73043 = + assign b__h70410 = byteAlignerReader_bytes_left_in_buffer$EN_port0__write ? byteAlignerReader_bytes_left_in_buffer$port0__write_1 : byteAlignerReader_bytes_left_in_buffer ; - assign beatsThisRequestCntrT__h28413 = + assign beatsThisRequestCntrT__h27936 = m_pcie_wr_beatsThisRequestCntr + 8'd1 ; - assign beatsThisRequestCntrT__h43350 = + assign beatsThisRequestCntrT__h41764 = m_fpga_wr_beatsThisRequestCntr + 8'd1 ; - assign beatsThisRequest___1__h27936 = + assign beatsThisRequest___1__h27476 = m_pcie_wr_task_data_requests_reg[134:127] - 8'd1 ; - assign beatsThisRequest___1__h37490 = + assign beatsThisRequest___1__h36662 = m_pcie_rd_task_data_requests_reg[134:127] - 8'd1 ; - assign beatsThisRequest___1__h42873 = + assign beatsThisRequest___1__h41304 = m_fpga_wr_task_data_requests_reg[133:126] - 8'd1 ; - assign beatsThisRequest___1__h57832 = + assign beatsThisRequest___1__h55895 = m_fpga_rd_task_data_requests_reg[133:126] - 8'd1 ; - assign btt__h103430 = readIn_rv[63:0] + y__h103467 ; - assign btt__h147854 = writeIn_rv[63:0] + y__h147882 ; - assign byteAlignerReader_bytes_in_453_ULT_byteAligner_ETC___d1455 = + assign btt__h100105 = readIn_rv[63:0] + y__h100142 ; + assign btt__h143147 = writeIn_rv[63:0] + y__h143175 ; + assign byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 = byteAlignerReader_bytes_in < byteAlignerReader_bytes_total ; - assign byteAlignerReader_bytes_left_in_buffer_port1___ETC___d1472 = - b__h73043 < byteAlignerReader_bytes_out_needed ; - assign byteAlignerWriter_bytes_in_582_ULT_byteAligner_ETC___d1584 = + assign byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 = + byteAlignerReader_bytes_left_in_buffer < + byteAlignerReader_bytes_out_needed ; + assign byteAlignerWriter_bytes_in_559_ULT_byteAligner_ETC___d1561 = byteAlignerWriter_bytes_in < byteAlignerWriter_bytes_total ; - assign byteAlignerWriter_bytes_left_in_buffer_port1___ETC___d1601 = - b__h117504 < byteAlignerWriter_bytes_out_needed ; + assign byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1576 = + byteAlignerWriter_bytes_left_in_buffer < + byteAlignerWriter_bytes_out_needed ; assign bytes_first___1__h24323 = 64'd32 - bytes_first__h24287 ; - assign bytes_first___1__h34833 = 64'd32 - bytes_first__h34797 ; - assign bytes_first___1__h39275 = 64'd64 - bytes_first__h39239 ; - assign bytes_first___1__h55178 = 64'd64 - bytes_first__h55142 ; + assign bytes_first___1__h34277 = 64'd32 - bytes_first__h34241 ; + assign bytes_first___1__h38166 = 64'd64 - bytes_first__h38130 ; + assign bytes_first___1__h53513 = 64'd64 - bytes_first__h53477 ; assign bytes_first__h24287 = { 59'd0, m_pcie_wr_reqGen_incomingBuffer$D_OUT[72:68] } ; - assign bytes_first__h34797 = + assign bytes_first__h34241 = { 59'd0, m_pcie_rd_reqGen_incomingBuffer$D_OUT[72:68] } ; - assign bytes_first__h39239 = + assign bytes_first__h38130 = { 58'd0, m_fpga_wr_reqGen_incomingBuffer$D_OUT[73:68] } ; - assign bytes_first__h55142 = + assign bytes_first__h53477 = { 58'd0, m_fpga_rd_reqGen_incomingBuffer$D_OUT[73:68] } ; - assign endByte___1__h30104 = - startByte___1__h30103 + + assign endByte___1__h29551 = + startByte___1__h29550 + { 1'd0, m_pcie_wr_task_data_output_reg[74:70] } ; - assign endByte___1__h30130 = + assign endByte___1__h29577 = { 1'd0, m_pcie_wr_task_data_output_reg[69:65] } ; - assign endByte___1__h46449 = - startByte___1__h46448 + + assign endByte___1__h44787 = + startByte___1__h44786 + { 1'd0, m_fpga_wr_task_data_output_reg[76:71] } ; - assign endByte___1__h46475 = + assign endByte___1__h44813 = { 1'd0, m_fpga_wr_task_data_output_reg[70:65] } ; - assign fpgaLastCycle_703_AND_m_fpga_rd_task_data_outp_ETC___d1705 = + assign fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672 = fpgaLastCycle && m_fpga_rd_task_data_output_reg[64:7] == 58'd0 && m_fpga_rd_task_data_requests_reg[125:68] == 58'd0 && m_fpga_wr_task_data_output_reg[64:7] == 58'd0 && m_fpga_wr_task_data_requests_reg[125:68] == 58'd0 ; - assign m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7 = - m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h55222 ; - assign m_fpga_wr_beatsThisRequestCntr_22_EQ_m_fpga_wr_ETC___d924 = + assign m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6 = + m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h53557 ; + assign m_fpga_wr_beatsThisRequestCntr_13_EQ_m_fpga_wr_ETC___d915 = m_fpga_wr_beatsThisRequestCntr == m_fpga_wr_beatsPerRequestFIFO$D_OUT ; - assign m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8 = - m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h39319 ; - assign m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9 = - m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h34877 ; - assign m_pcie_wr_beatsThisRequestCntr_30_EQ_m_pcie_wr_ETC___d432 = + assign m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7 = + m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h38210 ; + assign m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8 = + m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h34321 ; + assign m_pcie_wr_beatsThisRequestCntr_28_EQ_m_pcie_wr_ETC___d430 = m_pcie_wr_beatsThisRequestCntr == m_pcie_wr_beatsPerRequestFIFO$D_OUT ; - assign m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q10 = + assign m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9 = m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h24367 ; - assign pcieLastCycle_696_AND_m_pcie_rd_task_data_outp_ETC___d1698 = + assign pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665 = pcieLastCycle && m_pcie_rd_task_data_output_reg[64:6] == 59'd0 && m_pcie_rd_task_data_requests_reg[126:68] == 59'd0 && m_pcie_wr_task_data_output_reg[64:6] == 59'd0 && m_pcie_wr_task_data_requests_reg[126:68] == 59'd0 ; assign request_data_address__h24612 = { m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[131:73], 5'd0 } ; - assign request_data_address__h35122 = + assign request_data_address__h34566 = { m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[131:73], 5'd0 } ; - assign request_data_address__h39564 = + assign request_data_address__h38455 = { m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[131:74], 6'd0 } ; - assign request_data_address__h55467 = + assign request_data_address__h53802 = { m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[131:74], 6'd0 } ; assign request_data_requests_total__h24611 = - (m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[135:132] == 4'd0) ? + (m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[137:132] == 6'd0) ? requests_total__h24575 : requests_total___1__h24637 ; - assign request_data_requests_total__h35121 = - (m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[135:132] == 4'd0) ? - requests_total__h35085 : - requests_total___1__h35147 ; - assign request_data_requests_total__h39563 = + assign request_data_requests_total__h34565 = + (m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[137:132] == 6'd0) ? + requests_total__h34529 : + requests_total___1__h34591 ; + assign request_data_requests_total__h38454 = (m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[139:132] == 8'd0) ? - requests_total__h39527 : - requests_total___1__h39589 ; - assign request_data_requests_total__h55466 = + requests_total__h38418 : + requests_total___1__h38480 ; + assign request_data_requests_total__h53801 = (m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[139:132] == 8'd0) ? - requests_total__h55430 : - requests_total___1__h55492 ; + requests_total__h53765 : + requests_total___1__h53827 ; assign requests_last__h24574 = - { 4'd0, m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[135:132] } ; - assign requests_last__h35084 = - { 4'd0, m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[135:132] } ; + { 2'd0, m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[137:132] } ; + assign requests_last__h34528 = + { 2'd0, m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[137:132] } ; assign requests_total___1__h24637 = requests_total__h24575 + 59'd1 ; - assign requests_total___1__h35147 = requests_total__h35085 + 59'd1 ; - assign requests_total___1__h39589 = requests_total__h39527 + 58'd1 ; - assign requests_total___1__h55492 = requests_total__h55430 + 58'd1 ; + assign requests_total___1__h34591 = requests_total__h34529 + 59'd1 ; + assign requests_total___1__h38480 = requests_total__h38418 + 58'd1 ; + assign requests_total___1__h53827 = requests_total__h53765 + 58'd1 ; assign requests_total__h24575 = - m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[190:132] >> 4 ; - assign requests_total__h35085 = - m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[190:132] >> 4 ; - assign requests_total__h39527 = + m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[190:132] >> 6 ; + assign requests_total__h34529 = + m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[190:132] >> 6 ; + assign requests_total__h38418 = m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[189:132] >> 8 ; - assign requests_total__h55430 = + assign requests_total__h53765 = m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[189:132] >> 8 ; - assign startByte___1__h30103 = + assign startByte___1__h29550 = { 1'd0, m_pcie_wr_task_data_output_reg[5:1] } ; - assign startByte___1__h46448 = + assign startByte___1__h44786 = { 1'd0, m_fpga_wr_task_data_output_reg[6:1] } ; assign transfers_total___1__h24480 = transfers_total__h24471 + 64'd1 ; - assign transfers_total___1__h34990 = transfers_total__h34981 + 64'd1 ; - assign transfers_total___1__h39432 = transfers_total__h39423 + 64'd1 ; - assign transfers_total___1__h55335 = transfers_total__h55326 + 64'd1 ; + assign transfers_total___1__h34434 = transfers_total__h34425 + 64'd1 ; + assign transfers_total___1__h38323 = transfers_total__h38314 + 64'd1 ; + assign transfers_total___1__h53670 = transfers_total__h53661 + 64'd1 ; assign transfers_total__h24471 = (x__h24500 - y__h24501) >> 5 ; assign transfers_total__h24477 = _theResult____h24472 + 64'd1 ; - assign transfers_total__h34981 = (x__h35010 - y__h35011) >> 5 ; - assign transfers_total__h34987 = _theResult____h34982 + 64'd1 ; - assign transfers_total__h39423 = (x__h39452 - y__h39453) >> 6 ; - assign transfers_total__h39429 = _theResult____h39424 + 64'd1 ; - assign transfers_total__h55326 = (x__h55355 - y__h55356) >> 6 ; - assign transfers_total__h55332 = _theResult____h55327 + 64'd1 ; + assign transfers_total__h34425 = (x__h34454 - y__h34455) >> 5 ; + assign transfers_total__h34431 = _theResult____h34426 + 64'd1 ; + assign transfers_total__h38314 = (x__h38343 - y__h38344) >> 6 ; + assign transfers_total__h38320 = _theResult____h38315 + 64'd1 ; + assign transfers_total__h53661 = (x__h53690 - y__h53691) >> 6 ; + assign transfers_total__h53667 = _theResult____h53662 + 64'd1 ; assign x__h24293 = (m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] < _theResult____h24288 || @@ -5195,436 +5136,425 @@ module mkBlueDMA(CLK_m32_axi_aclk, transfers_total__h24477 ; assign x__h24500 = m_pcie_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h24503 ; - assign x__h30090 = + assign x__h29537 = (m_pcie_wr_task_data_output_reg[0] && m_pcie_wr_task_data_output_reg[74:70] != 5'd0) ? - startByte___1__h30103 : + startByte___1__h29550 : 6'd0 ; - assign x__h34803 = + assign x__h34247 = (m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] < - _theResult____h34798 || - _theResult____h34798 == 64'd0 && + _theResult____h34242 || + _theResult____h34242 == 64'd0 && m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] < 64'd32) ? m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] : - _theResult____h34798 ; - assign x__h34984 = + _theResult____h34242 ; + assign x__h34428 = (m_pcie_rd_reqGen_intermediateBuffer$D_OUT[136:132] == 5'd0) ? - _theResult____h34982 : - transfers_total__h34987 ; - assign x__h35010 = - m_pcie_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h35013 ; - assign x__h39245 = + _theResult____h34426 : + transfers_total__h34431 ; + assign x__h34454 = + m_pcie_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h34457 ; + assign x__h38136 = (m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] < - _theResult____h39240 || - _theResult____h39240 == 64'd0 && + _theResult____h38131 || + _theResult____h38131 == 64'd0 && m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] < 64'd64) ? m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] : - _theResult____h39240 ; - assign x__h39426 = + _theResult____h38131 ; + assign x__h38317 = (m_fpga_wr_reqGen_intermediateBuffer$D_OUT[137:132] == 6'd0) ? - _theResult____h39424 : - transfers_total__h39429 ; - assign x__h39452 = - m_fpga_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h39455 ; - assign x__h46435 = + _theResult____h38315 : + transfers_total__h38320 ; + assign x__h38343 = + m_fpga_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h38346 ; + assign x__h44773 = (m_fpga_wr_task_data_output_reg[0] && m_fpga_wr_task_data_output_reg[76:71] != 6'd0) ? - startByte___1__h46448 : + startByte___1__h44786 : 7'd0 ; - assign x__h55148 = + assign x__h53483 = (m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] < - _theResult____h55143 || - _theResult____h55143 == 64'd0 && + _theResult____h53478 || + _theResult____h53478 == 64'd0 && m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] < 64'd64) ? m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] : - _theResult____h55143 ; - assign x__h55329 = + _theResult____h53478 ; + assign x__h53664 = (m_fpga_rd_reqGen_intermediateBuffer$D_OUT[137:132] == 6'd0) ? - _theResult____h55327 : - transfers_total__h55332 ; - assign x__h55355 = - m_fpga_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h55358 ; - assign x_address__h27994 = - m_pcie_wr_task_data_requests_reg[67:4] + 64'd512 ; - assign x_address__h37519 = - m_pcie_rd_task_data_requests_reg[67:4] + 64'd512 ; - assign x_address__h42931 = + _theResult____h53662 : + transfers_total__h53667 ; + assign x__h53690 = + m_fpga_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h53693 ; + assign x_address__h27534 = + m_pcie_wr_task_data_requests_reg[67:4] + 64'd2048 ; + assign x_address__h36691 = + m_pcie_rd_task_data_requests_reg[67:4] + 64'd2048 ; + assign x_address__h41362 = m_fpga_wr_task_data_requests_reg[67:4] + 64'd16384 ; - assign x_address__h57861 = + assign x_address__h55924 = m_fpga_rd_task_data_requests_reg[67:4] + 64'd16384 ; - assign x_requests_total__h27993 = + assign x_requests_total__h27533 = m_pcie_wr_task_data_requests_reg[126:68] - 59'd1 ; - assign x_requests_total__h37518 = + assign x_requests_total__h36690 = m_pcie_rd_task_data_requests_reg[126:68] - 59'd1 ; - assign x_requests_total__h42930 = + assign x_requests_total__h41361 = m_fpga_wr_task_data_requests_reg[125:68] - 58'd1 ; - assign x_requests_total__h57860 = + assign x_requests_total__h55923 = m_fpga_rd_task_data_requests_reg[125:68] - 58'd1 ; - assign x_strb__h28588 = - { x__h30090 <= 6'd31 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + assign x_strb__h28050 = + { x__h29537 <= 6'd31 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd31, - x__h30090 <= 6'd30 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd30 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd30, - x__h30090 <= 6'd29 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd29 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd29, - x__h30090 <= 6'd28 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd28 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd28, - x__h30090 <= 6'd27 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd27 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd27, - x__h30090 <= 6'd26 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd26 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd26, - x__h30090 <= 6'd25 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd25 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd25, - x__h30090 <= 6'd24 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd24 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd24, - x__h30090 <= 6'd23 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd23 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd23, - x__h30090 <= 6'd22 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd22 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd22, - x__h30090 <= 6'd21 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd21 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd21, - x__h30090 <= 6'd20 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd20 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd20, - x__h30090 <= 6'd19 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd19 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd19, - x__h30090 <= 6'd18 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd18 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd18, - x__h30090 <= 6'd17 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd17 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd17, - x__h30090 <= 6'd16 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd16 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd16, - x__h30090 <= 6'd15 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd15 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd15, - x__h30090 <= 6'd14 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd14 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd14, - x__h30090 <= 6'd13 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd13 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd13, - x__h30090 <= 6'd12 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd12 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd12, - x__h30090 <= 6'd11 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd11 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd11, - x__h30090 <= 6'd10 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd10 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd10, - x__h30090 <= 6'd9 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd9 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd9, - x__h30090 <= 6'd8 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd8 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd8, - x__h30090 <= 6'd7 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd7 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd7, - x__h30090 <= 6'd6 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd6 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd6, - x__h30090 <= 6'd5 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd5 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd5, - x__h30090 <= 6'd4 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd4 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd4, - x__h30090 <= 6'd3 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd3 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd3, - x__h30090 <= 6'd2 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd2 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd2, - x__h30090 <= 6'd1 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 > + x__h29537 <= 6'd1 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > 6'd1, - x__h30090 == 6'd0 && - IF_m_pcie_wr_task_data_output_reg_24_BIT_0_36__ETC___d453 != + x__h29537 == 6'd0 && + IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 != 6'd0 } ; - assign x_strb__h43525 = - { x__h46435 <= 7'd63 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + assign x_strb__h41878 = + { x__h44773 <= 7'd63 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd63, - x__h46435 <= 7'd62 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd62 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd62, - x__h46435 <= 7'd61 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd61 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd61, - x__h46435 <= 7'd60 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd60 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd60, - x__h46435 <= 7'd59 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd59 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd59, - x__h46435 <= 7'd58 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd58 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd58, - x__h46435 <= 7'd57 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd57 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd57, - x__h46435 <= 7'd56 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd56 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd56, - x__h46435 <= 7'd55 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd55 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd55, - x__h46435 <= 7'd54 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd54 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd54, - x__h46435 <= 7'd53 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd53 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd53, - x__h46435 <= 7'd52 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd52 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd52, - x__h46435 <= 7'd51 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd51 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd51, - x__h46435 <= 7'd50 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd50 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd50, - x__h46435 <= 7'd49 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd49 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd49, - x__h46435 <= 7'd48 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd48 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd48, - x__h46435 <= 7'd47 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd47 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd47, - x__h46435 <= 7'd46 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd46 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd46, - x__h46435 <= 7'd45 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd45 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd45, - x__h46435 <= 7'd44 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd44 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd44, - x__h46435 <= 7'd43 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd43 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd43, - x__h46435 <= 7'd42 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd42 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd42, - x__h46435 <= 7'd41 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd41 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd41, - x__h46435 <= 7'd40 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd40 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd40, - x__h46435 <= 7'd39 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd39 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd39, - x__h46435 <= 7'd38 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd38 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd38, - x__h46435 <= 7'd37 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd37 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd37, - x__h46435 <= 7'd36 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd36 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd36, - x__h46435 <= 7'd35 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd35 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd35, - x__h46435 <= 7'd34 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd34 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd34, - x__h46435 <= 7'd33 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd33 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd33, - x__h46435 <= 7'd32 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd32 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd32, - x__h46435 <= 7'd31 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd31 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd31, - x__h46435 <= 7'd30 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd30 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd30, - x__h46435 <= 7'd29 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd29 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd29, - x__h46435 <= 7'd28 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd28 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd28, - x__h46435 <= 7'd27 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd27 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd27, - x__h46435 <= 7'd26 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd26 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd26, - x__h46435 <= 7'd25 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd25 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd25, - x__h46435 <= 7'd24 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd24 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd24, - x__h46435 <= 7'd23 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd23 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd23, - x__h46435 <= 7'd22 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd22 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd22, - x__h46435 <= 7'd21 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd21 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd21, - x__h46435 <= 7'd20 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd20 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd20, - x__h46435 <= 7'd19 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd19 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd19, - x__h46435 <= 7'd18 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd18 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd18, - x__h46435 <= 7'd17 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd17 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd17, - x__h46435 <= 7'd16 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd16 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd16, - x__h46435 <= 7'd15 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd15 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd15, - x__h46435 <= 7'd14 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd14 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd14, - x__h46435 <= 7'd13 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd13 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd13, - x__h46435 <= 7'd12 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd12 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd12, - x__h46435 <= 7'd11 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd11 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd11, - x__h46435 <= 7'd10 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd10 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd10, - x__h46435 <= 7'd9 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd9 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd9, - x__h46435 <= 7'd8 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd8 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd8, - x__h46435 <= 7'd7 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd7 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd7, - x__h46435 <= 7'd6 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd6 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd6, - x__h46435 <= 7'd5 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd5 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd5, - x__h46435 <= 7'd4 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd4 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd4, - x__h46435 <= 7'd3 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd3 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd3, - x__h46435 <= 7'd2 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd2 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd2, - x__h46435 <= 7'd1 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 > + x__h44773 <= 7'd1 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > 7'd1, - x__h46435 == 7'd0 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_28__ETC___d945 != + x__h44773 == 7'd0 && + IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 != 7'd0 } ; - assign x_transfers_total__h34115 = + assign x_transfers_total__h33560 = m_pcie_wr_task_data_output_reg[64:6] - 59'd1 ; - assign x_transfers_total__h38179 = + assign x_transfers_total__h37140 = m_pcie_rd_task_data_output_reg[64:6] - 59'd1 ; - assign x_transfers_total__h54460 = + assign x_transfers_total__h52796 = m_fpga_wr_task_data_output_reg[64:7] - 58'd1 ; - assign x_transfers_total__h58521 = + assign x_transfers_total__h56373 = m_fpga_rd_task_data_output_reg[64:7] - 58'd1 ; - assign y__h103467 = { 59'd0, readIn_rv[68:64] } ; - assign y__h147882 = { 59'd0, writeIn_rv[68:64] } ; + assign y__h100142 = { 59'd0, readIn_rv[68:64] } ; + assign y__h143175 = { 59'd0, writeIn_rv[68:64] } ; assign y__h24367 = { 59'd0, x__h24293[4:0] } ; assign y__h24501 = { 59'd0, m_pcie_wr_reqGen_intermediateBuffer$D_OUT[136:132] } ; assign y__h24503 = { 59'd0, m_pcie_wr_reqGen_intermediateBuffer$D_OUT[141:137] } ; - assign y__h34877 = { 59'd0, x__h34803[4:0] } ; - assign y__h35011 = + assign y__h34321 = { 59'd0, x__h34247[4:0] } ; + assign y__h34455 = { 59'd0, m_pcie_rd_reqGen_intermediateBuffer$D_OUT[136:132] } ; - assign y__h35013 = + assign y__h34457 = { 59'd0, m_pcie_rd_reqGen_intermediateBuffer$D_OUT[141:137] } ; - assign y__h39319 = { 58'd0, x__h39245[5:0] } ; - assign y__h39453 = + assign y__h38210 = { 58'd0, x__h38136[5:0] } ; + assign y__h38344 = { 58'd0, m_fpga_wr_reqGen_intermediateBuffer$D_OUT[137:132] } ; - assign y__h39455 = + assign y__h38346 = { 58'd0, m_fpga_wr_reqGen_intermediateBuffer$D_OUT[143:138] } ; - assign y__h55222 = { 58'd0, x__h55148[5:0] } ; - assign y__h55356 = + assign y__h53557 = { 58'd0, x__h53483[5:0] } ; + assign y__h53691 = { 58'd0, m_fpga_rd_reqGen_intermediateBuffer$D_OUT[137:132] } ; - assign y__h55358 = + assign y__h53693 = { 58'd0, m_fpga_rd_reqGen_intermediateBuffer$D_OUT[143:138] } ; - always@(readConverter_wordInCntr or readConverter_buffer) - begin - case (readConverter_wordInCntr) - 1'd0: - CASE_readConverter_wordInCntr_0_readConverter__ETC__q2 = - readConverter_buffer[255:0]; - 1'd1: - CASE_readConverter_wordInCntr_0_readConverter__ETC__q2 = - readConverter_buffer[511:256]; - endcase - end always@(m_pcie_wr_master_wr_wawcache$wget) begin case (m_pcie_wr_master_wr_wawcache$wget) 4'd1, 4'd2, 4'd3, 4'd6, 4'd7, 4'd14: - CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q3 = + CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q2 = m_pcie_wr_master_wr_wawcache$wget; - default: CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q3 = 4'd15; + default: CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q2 = 4'd15; endcase end always@(m_pcie_rd_master_rd_warcache$wget) begin case (m_pcie_rd_master_rd_warcache$wget) 4'd1, 4'd2, 4'd3, 4'd10, 4'd14, 4'd15: - CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q4 = + CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q3 = m_pcie_rd_master_rd_warcache$wget; - default: CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q4 = 4'd11; + default: CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q3 = 4'd11; endcase end always@(m_fpga_wr_master_wr_wawcache$wget) begin case (m_fpga_wr_master_wr_wawcache$wget) 4'd1, 4'd2, 4'd3, 4'd6, 4'd7, 4'd14: - CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q5 = + CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q4 = m_fpga_wr_master_wr_wawcache$wget; - default: CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q5 = 4'd15; + default: CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q4 = 4'd15; endcase end always@(m_fpga_rd_master_rd_warcache$wget) begin case (m_fpga_rd_master_rd_warcache$wget) 4'd1, 4'd2, 4'd3, 4'd10, 4'd14, 4'd15: - CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q6 = + CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q5 = m_fpga_rd_master_rd_warcache$wget; - default: CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q6 = 4'd11; + default: CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q5 = 4'd11; endcase end @@ -5637,7 +5567,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, doneInterruptReg <= `BSV_ASSIGNMENT_DELAY 1'd0; fpga_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; host_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; - id <= `BSV_ASSIGNMENT_DELAY 64'h0020FF0F0E5A0023; + id <= `BSV_ASSIGNMENT_DELAY 64'h0020FF3F0E5A0023; opInProgress <= `BSV_ASSIGNMENT_DELAY 1'd0; readIn_rv <= `BSV_ASSIGNMENT_DELAY 193'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -5698,21 +5628,13 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpgaLastCycle <= `BSV_ASSIGNMENT_DELAY 1'd0; m_fpga_rd_clkCntr <= `BSV_ASSIGNMENT_DELAY 32'd0; m_fpga_rd_lastPut <= `BSV_ASSIGNMENT_DELAY 32'd0; - m_fpga_rd_master_rd_out_1_rv <= `BSV_ASSIGNMENT_DELAY - 518'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_fpga_rd_outgoingBuffer_rv <= `BSV_ASSIGNMENT_DELAY - 513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_fpga_rd_putDelay <= `BSV_ASSIGNMENT_DELAY 32'd0; m_fpga_rd_task_data_output_reg <= `BSV_ASSIGNMENT_DELAY 77'd0; m_fpga_rd_task_data_requests_reg <= `BSV_ASSIGNMENT_DELAY 134'd0; m_fpga_rd_totalPuts <= `BSV_ASSIGNMENT_DELAY 32'd0; m_fpga_wr_beatsThisRequestCntr <= `BSV_ASSIGNMENT_DELAY 8'd0; m_fpga_wr_clkCntr <= `BSV_ASSIGNMENT_DELAY 32'd0; - m_fpga_wr_incomingBuffer_rv <= `BSV_ASSIGNMENT_DELAY - 513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_fpga_wr_lastPut <= `BSV_ASSIGNMENT_DELAY 32'd0; - m_fpga_wr_master_wr_in_data_1_rv <= `BSV_ASSIGNMENT_DELAY - 579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_fpga_wr_putDelay <= `BSV_ASSIGNMENT_DELAY 32'd0; m_fpga_wr_task_data_output_reg <= `BSV_ASSIGNMENT_DELAY 77'd0; m_fpga_wr_task_data_requests_reg <= `BSV_ASSIGNMENT_DELAY 134'd0; @@ -5726,12 +5648,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_rd_clkCntr <= `BSV_ASSIGNMENT_DELAY m_fpga_rd_clkCntr$D_IN; if (m_fpga_rd_lastPut$EN) m_fpga_rd_lastPut <= `BSV_ASSIGNMENT_DELAY m_fpga_rd_lastPut$D_IN; - if (m_fpga_rd_master_rd_out_1_rv$EN) - m_fpga_rd_master_rd_out_1_rv <= `BSV_ASSIGNMENT_DELAY - m_fpga_rd_master_rd_out_1_rv$D_IN; - if (m_fpga_rd_outgoingBuffer_rv$EN) - m_fpga_rd_outgoingBuffer_rv <= `BSV_ASSIGNMENT_DELAY - m_fpga_rd_outgoingBuffer_rv$D_IN; if (m_fpga_rd_putDelay$EN) m_fpga_rd_putDelay <= `BSV_ASSIGNMENT_DELAY m_fpga_rd_putDelay$D_IN; if (m_fpga_rd_task_data_output_reg$EN) @@ -5748,14 +5664,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_beatsThisRequestCntr$D_IN; if (m_fpga_wr_clkCntr$EN) m_fpga_wr_clkCntr <= `BSV_ASSIGNMENT_DELAY m_fpga_wr_clkCntr$D_IN; - if (m_fpga_wr_incomingBuffer_rv$EN) - m_fpga_wr_incomingBuffer_rv <= `BSV_ASSIGNMENT_DELAY - m_fpga_wr_incomingBuffer_rv$D_IN; if (m_fpga_wr_lastPut$EN) m_fpga_wr_lastPut <= `BSV_ASSIGNMENT_DELAY m_fpga_wr_lastPut$D_IN; - if (m_fpga_wr_master_wr_in_data_1_rv$EN) - m_fpga_wr_master_wr_in_data_1_rv <= `BSV_ASSIGNMENT_DELAY - m_fpga_wr_master_wr_in_data_1_rv$D_IN; if (m_fpga_wr_putDelay$EN) m_fpga_wr_putDelay <= `BSV_ASSIGNMENT_DELAY m_fpga_wr_putDelay$D_IN; if (m_fpga_wr_task_data_output_reg$EN) @@ -5775,32 +5685,16 @@ module mkBlueDMA(CLK_m32_axi_aclk, if (RST_N_m64_axi_arestn == `BSV_RESET_VALUE) begin byteAlignerReader_fetchedDatum <= `BSV_ASSIGNMENT_DELAY 1'd0; - byteAlignerReader_incoming_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - byteAlignerReader_outgoing_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; byteAlignerWriter_fetchedDatum <= `BSV_ASSIGNMENT_DELAY 1'd0; - byteAlignerWriter_incoming_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - byteAlignerWriter_outgoing_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_pcie_rd_clkCntr <= `BSV_ASSIGNMENT_DELAY 32'd0; m_pcie_rd_lastPut <= `BSV_ASSIGNMENT_DELAY 32'd0; - m_pcie_rd_master_rd_out_1_rv <= `BSV_ASSIGNMENT_DELAY - 262'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_pcie_rd_outgoingBuffer_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_pcie_rd_putDelay <= `BSV_ASSIGNMENT_DELAY 32'd0; m_pcie_rd_task_data_output_reg <= `BSV_ASSIGNMENT_DELAY 75'd0; m_pcie_rd_task_data_requests_reg <= `BSV_ASSIGNMENT_DELAY 135'd0; m_pcie_rd_totalPuts <= `BSV_ASSIGNMENT_DELAY 32'd0; m_pcie_wr_beatsThisRequestCntr <= `BSV_ASSIGNMENT_DELAY 8'd0; m_pcie_wr_clkCntr <= `BSV_ASSIGNMENT_DELAY 32'd0; - m_pcie_wr_incomingBuffer_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_pcie_wr_lastPut <= `BSV_ASSIGNMENT_DELAY 32'd0; - m_pcie_wr_master_wr_in_data_1_rv <= `BSV_ASSIGNMENT_DELAY - 291'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_pcie_wr_putDelay <= `BSV_ASSIGNMENT_DELAY 32'd0; m_pcie_wr_task_data_output_reg <= `BSV_ASSIGNMENT_DELAY 75'd0; m_pcie_wr_task_data_requests_reg <= `BSV_ASSIGNMENT_DELAY 135'd0; @@ -5811,8 +5705,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, readConverter_wordInCntr <= `BSV_ASSIGNMENT_DELAY 1'd0; writeConverter_buffer_0 <= `BSV_ASSIGNMENT_DELAY 256'd0; writeConverter_byteCntr <= `BSV_ASSIGNMENT_DELAY 64'd0; - writeConverter_dataSync_rv <= `BSV_ASSIGNMENT_DELAY - 513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; writeConverter_wordInCntr <= `BSV_ASSIGNMENT_DELAY 2'd0; end else @@ -5820,31 +5712,13 @@ module mkBlueDMA(CLK_m32_axi_aclk, if (byteAlignerReader_fetchedDatum$EN) byteAlignerReader_fetchedDatum <= `BSV_ASSIGNMENT_DELAY byteAlignerReader_fetchedDatum$D_IN; - if (byteAlignerReader_incoming_rv$EN) - byteAlignerReader_incoming_rv <= `BSV_ASSIGNMENT_DELAY - byteAlignerReader_incoming_rv$D_IN; - if (byteAlignerReader_outgoing_rv$EN) - byteAlignerReader_outgoing_rv <= `BSV_ASSIGNMENT_DELAY - byteAlignerReader_outgoing_rv$D_IN; if (byteAlignerWriter_fetchedDatum$EN) byteAlignerWriter_fetchedDatum <= `BSV_ASSIGNMENT_DELAY byteAlignerWriter_fetchedDatum$D_IN; - if (byteAlignerWriter_incoming_rv$EN) - byteAlignerWriter_incoming_rv <= `BSV_ASSIGNMENT_DELAY - byteAlignerWriter_incoming_rv$D_IN; - if (byteAlignerWriter_outgoing_rv$EN) - byteAlignerWriter_outgoing_rv <= `BSV_ASSIGNMENT_DELAY - byteAlignerWriter_outgoing_rv$D_IN; if (m_pcie_rd_clkCntr$EN) m_pcie_rd_clkCntr <= `BSV_ASSIGNMENT_DELAY m_pcie_rd_clkCntr$D_IN; if (m_pcie_rd_lastPut$EN) m_pcie_rd_lastPut <= `BSV_ASSIGNMENT_DELAY m_pcie_rd_lastPut$D_IN; - if (m_pcie_rd_master_rd_out_1_rv$EN) - m_pcie_rd_master_rd_out_1_rv <= `BSV_ASSIGNMENT_DELAY - m_pcie_rd_master_rd_out_1_rv$D_IN; - if (m_pcie_rd_outgoingBuffer_rv$EN) - m_pcie_rd_outgoingBuffer_rv <= `BSV_ASSIGNMENT_DELAY - m_pcie_rd_outgoingBuffer_rv$D_IN; if (m_pcie_rd_putDelay$EN) m_pcie_rd_putDelay <= `BSV_ASSIGNMENT_DELAY m_pcie_rd_putDelay$D_IN; if (m_pcie_rd_task_data_output_reg$EN) @@ -5861,14 +5735,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_wr_beatsThisRequestCntr$D_IN; if (m_pcie_wr_clkCntr$EN) m_pcie_wr_clkCntr <= `BSV_ASSIGNMENT_DELAY m_pcie_wr_clkCntr$D_IN; - if (m_pcie_wr_incomingBuffer_rv$EN) - m_pcie_wr_incomingBuffer_rv <= `BSV_ASSIGNMENT_DELAY - m_pcie_wr_incomingBuffer_rv$D_IN; if (m_pcie_wr_lastPut$EN) m_pcie_wr_lastPut <= `BSV_ASSIGNMENT_DELAY m_pcie_wr_lastPut$D_IN; - if (m_pcie_wr_master_wr_in_data_1_rv$EN) - m_pcie_wr_master_wr_in_data_1_rv <= `BSV_ASSIGNMENT_DELAY - m_pcie_wr_master_wr_in_data_1_rv$D_IN; if (m_pcie_wr_putDelay$EN) m_pcie_wr_putDelay <= `BSV_ASSIGNMENT_DELAY m_pcie_wr_putDelay$D_IN; if (m_pcie_wr_task_data_output_reg$EN) @@ -5897,9 +5765,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, if (writeConverter_byteCntr$EN) writeConverter_byteCntr <= `BSV_ASSIGNMENT_DELAY writeConverter_byteCntr$D_IN; - if (writeConverter_dataSync_rv$EN) - writeConverter_dataSync_rv <= `BSV_ASSIGNMENT_DELAY - writeConverter_dataSync_rv$D_IN; if (writeConverter_wordInCntr$EN) writeConverter_wordInCntr <= `BSV_ASSIGNMENT_DELAY writeConverter_wordInCntr$D_IN; @@ -5957,10 +5822,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerReader_bytes_out_needed = 6'h2A; byteAlignerReader_bytes_total = 64'hAAAAAAAAAAAAAAAA; byteAlignerReader_fetchedDatum = 1'h0; - byteAlignerReader_incoming_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - byteAlignerReader_outgoing_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; byteAlignerWriter_buffer = 512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; byteAlignerWriter_bytes_in = 64'hAAAAAAAAAAAAAAAA; @@ -5969,10 +5830,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_bytes_out_needed = 6'h2A; byteAlignerWriter_bytes_total = 64'hAAAAAAAAAAAAAAAA; byteAlignerWriter_fetchedDatum = 1'h0; - byteAlignerWriter_incoming_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - byteAlignerWriter_outgoing_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; doneInterruptReg = 1'h0; fpgaLastCycle = 1'h0; fpga_addr = 64'hAAAAAAAAAAAAAAAA; @@ -5982,10 +5839,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, id = 64'hAAAAAAAAAAAAAAAA; m_fpga_rd_clkCntr = 32'hAAAAAAAA; m_fpga_rd_lastPut = 32'hAAAAAAAA; - m_fpga_rd_master_rd_out_1_rv = - 518'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_fpga_rd_outgoingBuffer_rv = - 513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_fpga_rd_putDelay = 32'hAAAAAAAA; m_fpga_rd_task_data_output_reg = 77'h0AAAAAAAAAAAAAAAAAAA; m_fpga_rd_task_data_requests_reg = @@ -5993,11 +5846,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_rd_totalPuts = 32'hAAAAAAAA; m_fpga_wr_beatsThisRequestCntr = 8'hAA; m_fpga_wr_clkCntr = 32'hAAAAAAAA; - m_fpga_wr_incomingBuffer_rv = - 513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_fpga_wr_lastPut = 32'hAAAAAAAA; - m_fpga_wr_master_wr_in_data_1_rv = - 579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_fpga_wr_putDelay = 32'hAAAAAAAA; m_fpga_wr_task_data_output_reg = 77'h0AAAAAAAAAAAAAAAAAAA; m_fpga_wr_task_data_requests_reg = @@ -6005,10 +5854,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_totalPuts = 32'hAAAAAAAA; m_pcie_rd_clkCntr = 32'hAAAAAAAA; m_pcie_rd_lastPut = 32'hAAAAAAAA; - m_pcie_rd_master_rd_out_1_rv = - 262'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_pcie_rd_outgoingBuffer_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_pcie_rd_putDelay = 32'hAAAAAAAA; m_pcie_rd_task_data_output_reg = 75'h2AAAAAAAAAAAAAAAAAA; m_pcie_rd_task_data_requests_reg = @@ -6016,11 +5861,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_rd_totalPuts = 32'hAAAAAAAA; m_pcie_wr_beatsThisRequestCntr = 8'hAA; m_pcie_wr_clkCntr = 32'hAAAAAAAA; - m_pcie_wr_incomingBuffer_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_pcie_wr_lastPut = 32'hAAAAAAAA; - m_pcie_wr_master_wr_in_data_1_rv = - 291'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_pcie_wr_putDelay = 32'hAAAAAAAA; m_pcie_wr_task_data_output_reg = 75'h2AAAAAAAAAAAAAAAAAA; m_pcie_wr_task_data_requests_reg = @@ -6043,8 +5884,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, writeConverter_buffer_0 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; writeConverter_byteCntr = 64'hAAAAAAAAAAAAAAAA; - writeConverter_dataSync_rv = - 513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; writeConverter_wordInCntr = 2'h2; writeIn_rv = 193'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; write_requests = 64'hAAAAAAAAAAAAAAAA; @@ -6061,7 +5900,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_handleRead) - $display("btt org %d, btt after %d", readIn_rv[63:0], btt__h103430); + $display("btt org %d, btt after %d", readIn_rv[63:0], btt__h100105); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_s_config_axiReadSpecial_4 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4) && @@ -6604,10 +6443,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_wr_reqGen_finishRequest) $display("[WRITE] requests_total: %d", - request_data_requests_total__h39563); + request_data_requests_total__h38454); if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_wr_reqGen_finishRequest) - $display("[WRITE] address: %x", request_data_address__h39564); + $display("[WRITE] address: %x", request_data_address__h38455); if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest) $display("[READ] request:"); @@ -6634,10 +6473,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest) $display("[READ] requests_total: %d", - request_data_requests_total__h55466); + request_data_requests_total__h53801); if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest) - $display("[READ] address: %x", request_data_address__h55467); + $display("[READ] address: %x", request_data_address__h53802); end // synopsys translate_on @@ -6695,14 +6534,14 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[72:68]); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest) - $display("[READ] requests_last: %d", requests_last__h35084); + $display("[READ] requests_last: %d", requests_last__h34528); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest) $display("[READ] requests_total: %d", - request_data_requests_total__h35121); + request_data_requests_total__h34565); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest) - $display("[READ] address: %x", request_data_address__h35122); + $display("[READ] address: %x", request_data_address__h34566); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (byteAlignerReader_addr_ff$dEMPTY_N) $display("Init data:"); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) diff --git a/common/ip/BlueDMA/src/mkBlueDMAVivado.v b/common/ip/BlueDMA/src/mkBlueDMAVivado.v index cd9f16cd6fee04b0e40b04cd16568705b6a1a994..ff067d3f961e9f5ee999fdda9b3c03e4fd5b4c97 100644 --- a/common/ip/BlueDMA/src/mkBlueDMAVivado.v +++ b/common/ip/BlueDMA/src/mkBlueDMAVivado.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07) // -// On Thu Jul 6 13:00:49 CEST 2017 +// On Fri Jul 7 10:38:51 CEST 2017 // // // Ports: @@ -26,7 +26,7 @@ // m64_axi_arqos O 4 // m64_axi_arregion O 4 // m64_axi_aruser O 1 -// m64_axi_rready O 1 +// m64_axi_rready O 1 reg // m64_axi_awvalid O 1 reg // m64_axi_awid O 1 // m64_axi_awaddr O 64 @@ -39,7 +39,7 @@ // m64_axi_awqos O 4 // m64_axi_awregion O 4 // m64_axi_awuser O 1 -// m64_axi_wvalid O 1 +// m64_axi_wvalid O 1 reg // m64_axi_wdata O 256 // m64_axi_wstrb O 32 // m64_axi_wlast O 1 @@ -57,7 +57,7 @@ // m32_axi_arqos O 4 // m32_axi_arregion O 4 // m32_axi_aruser O 1 -// m32_axi_rready O 1 +// m32_axi_rready O 1 reg // m32_axi_awvalid O 1 reg // m32_axi_awid O 1 // m32_axi_awaddr O 64 @@ -70,7 +70,7 @@ // m32_axi_awqos O 4 // m32_axi_awregion O 4 // m32_axi_awuser O 1 -// m32_axi_wvalid O 1 +// m32_axi_wvalid O 1 reg // m32_axi_wdata O 512 // m32_axi_wstrb O 64 // m32_axi_wlast O 1 @@ -96,11 +96,11 @@ // S_AXI_bready I 1 // m64_axi_arready I 1 // m64_axi_rvalid I 1 -// m64_axi_rid I 1 -// m64_axi_rdata I 256 -// m64_axi_rresp I 2 -// m64_axi_rlast I 1 -// m64_axi_ruser I 1 +// m64_axi_rid I 1 reg +// m64_axi_rdata I 256 reg +// m64_axi_rresp I 2 reg +// m64_axi_rlast I 1 reg +// m64_axi_ruser I 1 reg // m64_axi_awready I 1 // m64_axi_wready I 1 // m64_axi_bvalid I 1 @@ -109,11 +109,11 @@ // m64_axi_buser I 1 reg // m32_axi_arready I 1 // m32_axi_rvalid I 1 -// m32_axi_rid I 1 -// m32_axi_rdata I 512 -// m32_axi_rresp I 2 -// m32_axi_rlast I 1 -// m32_axi_ruser I 1 +// m32_axi_rid I 1 reg +// m32_axi_rdata I 512 reg +// m32_axi_rresp I 2 reg +// m32_axi_rlast I 1 reg +// m32_axi_ruser I 1 reg // m32_axi_awready I 1 // m32_axi_wready I 1 // m32_axi_bvalid I 1 diff --git a/common/ip/MSIXIntrCtrl/component.xml b/common/ip/MSIXIntrCtrl/component.xml index e41978f4a9a8cb975daf6c2655914065e7a165bc..d2f5cdefd8a80ef18b19e77588394ed15973af81 100644 --- a/common/ip/MSIXIntrCtrl/component.xml +++ b/common/ip/MSIXIntrCtrl/component.xml @@ -427,7 +427,7 @@ viewChecksum - 558b72aa + e07e9e3a @@ -443,7 +443,7 @@ viewChecksum - 558b72aa + e07e9e3a @@ -1267,7 +1267,7 @@ src/mkMSIXIntrCtrl.v verilogSource - CHECKSUM_7049b426 + CHECKSUM_f02cbad3 @@ -1323,7 +1323,7 @@ MSIXIntrCtrl package_project 1 - 2017-07-05T16:28:24Z + 2017-07-07T08:36:48Z @@ -1333,7 +1333,7 @@ - + diff --git a/common/ip/MSIXIntrCtrl/msix_intr_ctrl.xdc b/common/ip/MSIXIntrCtrl/msix_intr_ctrl.xdc deleted file mode 100644 index 7f327383f2125ea3d4bfdaa1715dddb935b9fb59..0000000000000000000000000000000000000000 --- a/common/ip/MSIXIntrCtrl/msix_intr_ctrl.xdc +++ /dev/null @@ -1 +0,0 @@ -set_false_path -through [get_pins system_i/InterruptControl/msix_intr_ctrl/interrupt*] diff --git a/common/ip/MSIXIntrCtrl/src/mkMSIXIntrCtrl.v b/common/ip/MSIXIntrCtrl/src/mkMSIXIntrCtrl.v index 2961bf39e2d30b5bff5ca3418e298229a717220f..3e9a6756b89a43482acdf069113f8fdf4b1344c7 100644 --- a/common/ip/MSIXIntrCtrl/src/mkMSIXIntrCtrl.v +++ b/common/ip/MSIXIntrCtrl/src/mkMSIXIntrCtrl.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07) // -// On Wed Jul 5 18:26:03 CEST 2017 +// On Fri Jul 7 10:35:33 CEST 2017 // // // Ports: @@ -344,8 +344,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, nextInterrupt_rv$port1__write_1, nextInterrupt_rv$port2__read; wire [1 : 0] msixTable_serverAdapterB_s1_1$wget; - wire msixTable_serverAdapterA_outData_deqCalled$whas, - msixTable_serverAdapterA_outData_enqData$whas, + wire msixTable_serverAdapterA_outData_enqData$whas, msixTable_serverAdapterA_outData_outData$whas, msixTable_serverAdapterB_cnt_1$whas, msixTable_serverAdapterB_outData_enqData$whas, @@ -357,9 +356,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, s_config_writeSlave_addrIn_rv$EN_port1__write, s_config_writeSlave_dataIn_rv$EN_port0__write, s_config_writeSlave_dataIn_rv$EN_port1__write, - send_pending$EN_port0__write, - send_pending$port1__read, - send_pending$port2__read, writeMaster_addrOut_rv$EN_port0__write, writeMaster_addrOut_rv$EN_port1__write, writeMaster_dataOut_rv$EN_port0__write, @@ -3508,7 +3504,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, MUX_s_config_readSlave_out$enq_1__VAL_4, MUX_s_config_readSlave_out$enq_1__VAL_5, MUX_s_config_readSlave_out$enq_1__VAL_6; - wire MUX_msixTable_memory$b_put_1__SEL_1, + wire MUX_msixTable_memory$b_put_2__SEL_1, MUX_pba_vector_0$write_1__SEL_1, MUX_pba_vector_1$write_1__SEL_1, MUX_pba_vector_10$write_1__SEL_1, @@ -3641,14 +3637,15 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, MUX_pba_vector_97$write_1__SEL_1, MUX_pba_vector_98$write_1__SEL_1, MUX_pba_vector_99$write_1__SEL_1, - MUX_s_config_readBusy$write_1__SEL_1; + MUX_s_config_readBusy$write_1__SEL_1, + MUX_send_pending$write_1__SEL_2; // remaining internal signals - reg [31 : 0] v__h28374; + reg [31 : 0] v__h28373; reg SEL_ARR_vector_control_0_81_vector_control_1_8_ETC___d315; - wire [63 : 0] x_addr__h93628; - wire [31 : 0] r__h28539; - wire [15 : 0] addr__h28722, i__h28619, i__h54995; + wire [63 : 0] x_addr__h93468; + wire [31 : 0] r__h28538; + wire [15 : 0] addr__h28721, i__h28618, i__h54994; wire [7 : 0] IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1830, IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1832, IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1833, @@ -3698,7 +3695,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1739; wire [2 : 0] msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32, msixTable_serverAdapterB_cnt_3_PLUS_IF_msixTab_ETC___d89; - wire [1 : 0] ab__h18814; + wire [1 : 0] ab__h18813; wire NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1015, NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1315, NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d931, @@ -4047,8 +4044,8 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, // rule RL_s_config_axiReadSpecialRangeDelayedIsHandled_1 assign WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled_1 = - s_config_readSlave_in$EMPTY_N && i__h28619 >= 16'd32768 && - i__h28619 < 16'd32788 ; + s_config_readSlave_in$EMPTY_N && i__h28618 >= 16'd32768 && + i__h28618 < 16'd32788 ; // rule RL_s_config_axiReadSpecialIsHandled assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled = @@ -4073,8 +4070,8 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, // rule RL_s_config_axiReadSpecialRangeDelayed_1 assign WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed_1 = s_config_readSlave_in$EMPTY_N && pbaRet$FULL_N && - i__h28619 >= 16'd32768 && - i__h28619 < 16'd32788 && + i__h28618 >= 16'd32768 && + i__h28618 < 16'd32788 && !s_config_readBusy ; // rule RL_s_config_axiReadSpecialRangeDelayedReturn @@ -4668,7 +4665,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, assign WILL_FIRE_RL_msixTable_serverAdapterA_outData_enqAndDeq = msixTable_serverAdapterA_outDataCore$EMPTY_N && msixTable_serverAdapterA_outDataCore$FULL_N && - msixTable_serverAdapterA_outData_deqCalled$whas && + MUX_send_pending$write_1__SEL_2 && msixTable_serverAdapterA_outData_enqData$whas ; // rule RL_s_config_1_axiWriteSpecialRange @@ -4676,7 +4673,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, s_config_writeSlave_in$EMPTY_N && s_config_writeSlave_out$FULL_N && msixTable_serverAdapterB_cnt_3_SLT_3___d168 && - i__h54995 < 16'd2112 && + i__h54994 < 16'd2112 && !WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed ; // rule RL_s_config_axiReadSpecialRangeDelayed @@ -4700,7 +4697,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, // rule RL_waitForCompletion assign WILL_FIRE_RL_waitForCompletion = - writeMaster_out$EMPTY_N && active && send_pending$port1__read && + writeMaster_out$EMPTY_N && active && send_pending && !WILL_FIRE_RL_catchInterrupt_131 && !WILL_FIRE_RL_catchInterrupt_130 && !WILL_FIRE_RL_catchInterrupt_129 && @@ -4835,7 +4832,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, !WILL_FIRE_RL_catchInterrupt ; // inputs to muxes for submodule ports - assign MUX_msixTable_memory$b_put_1__SEL_1 = + assign MUX_msixTable_memory$b_put_2__SEL_1 = WILL_FIRE_RL_s_config_1_axiWriteSpecialRange && (s_config_writeSlave_in$D_OUT[42:41] == 2'd0 || s_config_writeSlave_in$D_OUT[42:41] == 2'd1 || @@ -5239,6 +5236,9 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, assign MUX_s_config_readBusy$write_1__SEL_1 = WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedReturn_1 || WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedReturn ; + assign MUX_send_pending$write_1__SEL_2 = + msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 && + enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ; always@(s_config_writeSlave_in$D_OUT) begin case (s_config_writeSlave_in$D_OUT[42:41]) @@ -5249,7 +5249,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, end assign MUX_msixTable_memory$b_put_3__VAL_1 = {3{s_config_writeSlave_in$D_OUT[38:7]}} ; - assign MUX_s_config_readSlave_out$enq_1__VAL_1 = { v__h28374, 2'd0 } ; + assign MUX_s_config_readSlave_out$enq_1__VAL_1 = { v__h28373, 2'd0 } ; assign MUX_s_config_readSlave_out$enq_1__VAL_2 = { pbaRet$D_OUT, 2'd0 } ; assign MUX_s_config_readSlave_out$enq_1__VAL_3 = { id, 2'd0 } ; assign MUX_s_config_readSlave_out$enq_1__VAL_4 = { enableAndMask, 2'd0 } ; @@ -5280,14 +5280,14 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, WILL_FIRE_RL_msixTable_serverAdapterB_outData_setFirstEnq || msixTable_serverAdapterB_outDataCore$EMPTY_N ; assign msixTable_serverAdapterB_cnt_1$whas = - (MUX_msixTable_memory$b_put_1__SEL_1 || + (MUX_msixTable_memory$b_put_2__SEL_1 || WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed) && - (!ab__h18814[1] || ab__h18814[0]) ; + (!ab__h18813[1] || ab__h18813[0]) ; assign msixTable_serverAdapterB_writeWithResp$whas = - MUX_msixTable_memory$b_put_1__SEL_1 || + MUX_msixTable_memory$b_put_2__SEL_1 || WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed ; assign msixTable_serverAdapterB_s1_1$wget = - { 1'd1, !ab__h18814[1] || ab__h18814[0] } ; + { 1'd1, !ab__h18813[1] || ab__h18813[0] } ; assign s_config_readIsHandled$whas = WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 || @@ -5295,9 +5295,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, WILL_FIRE_RL_s_config_axiReadSpecialIsHandled || WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled_1 || WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled ; - assign msixTable_serverAdapterA_outData_deqCalled$whas = - msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 && - enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ; assign s_config_writeSlave_addrIn_rv$EN_port0__write = !s_config_writeSlave_addrIn_rv[19] && S_AXI_awvalid ; assign s_config_writeSlave_addrIn_rv$port0__write_1 = @@ -5330,13 +5327,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, s_config_writeSlave_dataIn_rv$EN_port1__write ? 37'h0AAAAAAAAA : s_config_writeSlave_dataIn_rv$port1__read ; - assign send_pending$EN_port0__write = - msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 && - enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ; - assign send_pending$port1__read = - send_pending$EN_port0__write || send_pending ; - assign send_pending$port2__read = - !WILL_FIRE_RL_waitForCompletion && send_pending$port1__read ; assign nextInterrupt_rv$port1__read = WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways ? 9'd170 : @@ -7137,7 +7127,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32 ; assign msixTable_serverAdapterA_cnt$EN = WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways || - msixTable_serverAdapterA_outData_deqCalled$whas ; + MUX_send_pending$write_1__SEL_2 ; // register msixTable_serverAdapterA_s1 assign msixTable_serverAdapterA_s1$D_IN = @@ -8125,12 +8115,15 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, assign s_config_writeSlave_dataIn_rv$EN = 1'b1 ; // register send_pending - assign send_pending$D_IN = send_pending$port2__read ; - assign send_pending$EN = 1'b1 ; + assign send_pending$D_IN = !WILL_FIRE_RL_waitForCompletion ; + assign send_pending$EN = + WILL_FIRE_RL_waitForCompletion || + msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 && + enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ; // register sentReg assign sentReg$D_IN = sentReg + 32'd1 ; - assign sentReg$EN = msixTable_serverAdapterA_outData_deqCalled$whas ; + assign sentReg$EN = MUX_send_pending$write_1__SEL_2 ; // register vector_control_0 assign vector_control_0$D_IN = s_config_writeSlave_in$D_OUT[7] ; @@ -9067,17 +9060,17 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, // submodule msixTable_memory assign msixTable_memory$ADDRA = nextInterrupt_rv[7:0] ; assign msixTable_memory$ADDRB = - MUX_msixTable_memory$b_put_1__SEL_1 ? + MUX_msixTable_memory$b_put_2__SEL_1 ? s_config_writeSlave_in$D_OUT[50:43] : s_config_readSlave_in$D_OUT[14:7] ; assign msixTable_memory$DIA = 96'd0 ; assign msixTable_memory$DIB = - MUX_msixTable_memory$b_put_1__SEL_1 ? + MUX_msixTable_memory$b_put_2__SEL_1 ? MUX_msixTable_memory$b_put_3__VAL_1 : 96'd0 ; assign msixTable_memory$WEA = 12'd0 ; assign msixTable_memory$WEB = - MUX_msixTable_memory$b_put_1__SEL_1 ? + MUX_msixTable_memory$b_put_2__SEL_1 ? MUX_msixTable_memory$b_put_1__VAL_1 : 12'd0 ; assign msixTable_memory$ENA = @@ -9094,12 +9087,12 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, assign msixTable_serverAdapterA_outDataCore$ENQ = WILL_FIRE_RL_msixTable_serverAdapterA_outData_enqAndDeq || msixTable_serverAdapterA_outDataCore$FULL_N && - !msixTable_serverAdapterA_outData_deqCalled$whas && + !MUX_send_pending$write_1__SEL_2 && msixTable_serverAdapterA_outData_enqData$whas ; assign msixTable_serverAdapterA_outDataCore$DEQ = WILL_FIRE_RL_msixTable_serverAdapterA_outData_enqAndDeq || msixTable_serverAdapterA_outDataCore$EMPTY_N && - msixTable_serverAdapterA_outData_deqCalled$whas && + MUX_send_pending$write_1__SEL_2 && !msixTable_serverAdapterA_outData_enqData$whas ; assign msixTable_serverAdapterA_outDataCore$CLR = 1'b0 ; @@ -9118,7 +9111,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, assign msixTable_serverAdapterB_outDataCore$CLR = 1'b0 ; // submodule pbaRet - always@(addr__h28722 or + always@(addr__h28721 or pba_vector_31 or pba_vector_30 or pba_vector_29 or @@ -9250,7 +9243,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, pba_vector_131 or pba_vector_130 or pba_vector_129 or pba_vector_128) begin - case (addr__h28722[6:2]) + case (addr__h28721[6:2]) 5'd0: pbaRet$D_IN = { pba_vector_31, @@ -9533,11 +9526,10 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, // submodule writeMaster_in assign writeMaster_in$D_IN = - { x_addr__h93628, + { x_addr__h93468, msixTable_serverAdapterA_outData_outData$wget[31:0], 7'd120 } ; - assign writeMaster_in$ENQ = - msixTable_serverAdapterA_outData_deqCalled$whas ; + assign writeMaster_in$ENQ = MUX_send_pending$write_1__SEL_2 ; assign writeMaster_in$DEQ = writeMaster_in$EMPTY_N && !writeMaster_addrOut_rv[67] && !writeMaster_dataOut_rv[36] ; @@ -10038,20 +10030,20 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, NOT_vector_control_116_97_265_AND_pba_vector_1_ETC___d1275 || NOT_vector_control_120_01_277_AND_pba_vector_1_ETC___d1287 || NOT_vector_control_124_05_288_AND_pba_vector_1_ETC___d1298 ; - assign ab__h18814 = MUX_msixTable_memory$b_put_1__SEL_1 ? 2'd2 : 2'd1 ; - assign addr__h28722 = s_config_readSlave_in$D_OUT[18:3] - 16'd32768 ; + assign ab__h18813 = MUX_msixTable_memory$b_put_2__SEL_1 ? 2'd2 : 2'd1 ; + assign addr__h28721 = s_config_readSlave_in$D_OUT[18:3] - 16'd32768 ; assign enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 = cfg_interrupt_msix_enable[0] && !cfg_interrupt_msix_mask[0] && active && !send_pending ; - assign i__h28619 = { s_config_readSlave_in$D_OUT[18:5], 2'd0 } ; - assign i__h54995 = { s_config_writeSlave_in$D_OUT[54:41], 2'd0 } ; + assign i__h28618 = { s_config_readSlave_in$D_OUT[18:5], 2'd0 } ; + assign i__h54994 = { s_config_writeSlave_in$D_OUT[54:41], 2'd0 } ; assign msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32 = msixTable_serverAdapterA_cnt + (WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways ? 3'd1 : 3'd0) + - (msixTable_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ; + (MUX_send_pending$write_1__SEL_2 ? 3'd7 : 3'd0) ; assign msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 = (msixTable_serverAdapterA_outDataCore$EMPTY_N || msixTable_serverAdapterA_outData_enqData$whas) && @@ -10065,9 +10057,9 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, 3'd0) ; assign msixTable_serverAdapterB_cnt_3_SLT_3___d168 = (msixTable_serverAdapterB_cnt ^ 3'h4) < 3'd7 ; - assign r__h28539 = { 31'd0, typeRequest$D_OUT[0] } ; + assign r__h28538 = { 31'd0, typeRequest$D_OUT[0] } ; assign s_config_readSlave_in_first__71_BITS_18_TO_5_7_ETC___d174 = - i__h28619 < 16'd2112 ; + i__h28618 < 16'd2112 ; assign typeRequest_i_notEmpty__27_AND_msixTable_serve_ETC___d333 = typeRequest$EMPTY_N && (msixTable_serverAdapterB_outDataCore$EMPTY_N || @@ -10270,7 +10262,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, vector_control_116_97_OR_NOT_pba_vector_116_26_ETC___d1670 && vector_control_120_01_OR_NOT_pba_vector_120_20_ETC___d1682 && vector_control_124_05_OR_NOT_pba_vector_124_14_ETC___d1693 ; - assign x_addr__h93628 = + assign x_addr__h93468 = { msixTable_serverAdapterA_outData_outData$wget[63:32], msixTable_serverAdapterA_outData_outData$wget[95:64] } ; always@(s_config_readSlave_in$D_OUT or @@ -10807,13 +10799,13 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, endcase end always@(typeRequest$D_OUT or - msixTable_serverAdapterB_outData_outData$wget or r__h28539) + msixTable_serverAdapterB_outData_outData$wget or r__h28538) begin case (typeRequest$D_OUT[2:1]) - 2'd0: v__h28374 = msixTable_serverAdapterB_outData_outData$wget[95:64]; - 2'd1: v__h28374 = msixTable_serverAdapterB_outData_outData$wget[63:32]; - 2'd2: v__h28374 = msixTable_serverAdapterB_outData_outData$wget[31:0]; - 2'd3: v__h28374 = r__h28539; + 2'd0: v__h28373 = msixTable_serverAdapterB_outData_outData$wget[95:64]; + 2'd1: v__h28373 = msixTable_serverAdapterB_outData_outData$wget[63:32]; + 2'd2: v__h28373 = msixTable_serverAdapterB_outData_outData$wget[31:0]; + 2'd3: v__h28373 = r__h28538; endcase end @@ -13703,7 +13695,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (S_AXI_ARESETN != `BSV_RESET_VALUE) if (WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed_1) - $display("addr %x, addrShifted %x", addr__h28722, addr__h28722[6:2]); + $display("addr %x, addrShifted %x", addr__h28721, addr__h28721[6:2]); if (S_AXI_ARESETN != `BSV_RESET_VALUE) if (WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways) $display("Preparing to send interrupt %d", nextInterrupt_rv[7:0]);