From e495ff2123fb046ea4de4ad8bac816f1831a49de Mon Sep 17 00:00:00 2001 From: Jaco Hofmann Date: Fri, 7 Jul 2017 16:34:03 +0200 Subject: [PATCH 1/2] Adds performance counters to BlueDMA - Closes #89 - Adopts DebugScreen accordingly - Implements all registers requested in #89 expect for * Host read delay * FPGA read delay --- arch/tests/debug-screens/BlueDebugScreen.hpp | 57 +- common/ip/BlueDMA/component.xml | 210 +- common/ip/BlueDMA/src/SyncHandshake.v | 130 - common/ip/BlueDMA/src/SyncRegister.v | 175 -- common/ip/BlueDMA/src/mkBlueDMA.v | 2669 ++++++++---------- common/ip/BlueDMA/src/mkBlueDMAVivado.v | 66 +- 6 files changed, 1220 insertions(+), 2087 deletions(-) delete mode 100644 common/ip/BlueDMA/src/SyncHandshake.v delete mode 100644 common/ip/BlueDMA/src/SyncRegister.v diff --git a/arch/tests/debug-screens/BlueDebugScreen.hpp b/arch/tests/debug-screens/BlueDebugScreen.hpp index 62e5e17d..d386e96c 100644 --- a/arch/tests/debug-screens/BlueDebugScreen.hpp +++ b/arch/tests/debug-screens/BlueDebugScreen.hpp @@ -23,6 +23,8 @@ public: for(int i = 0; i < pba_vecs; ++i) { intr.pba.push_back(0); } + uint64_t accumulated_delay = 199; + platform::platform_write_ctl(0x300000 + 96, sizeof(accumulated_delay), &accumulated_delay, platform::PLATFORM_CTL_FLAGS_RAW); } virtual ~BlueDebugScreen() {} @@ -54,13 +56,10 @@ protected: platform::platform_read_ctl(0x300000 + 40, sizeof(dma.status), &dma.status, platform::PLATFORM_CTL_FLAGS_RAW); platform::platform_read_ctl(0x300000 + 48, sizeof(dma.read_requests), &dma.read_requests, platform::PLATFORM_CTL_FLAGS_RAW); platform::platform_read_ctl(0x300000 + 56, sizeof(dma.write_requests), &dma.write_requests, platform::PLATFORM_CTL_FLAGS_RAW); - platform::platform_read_ctl(0x300000 + 64, sizeof(dma.ack_count), &dma.ack_count, platform::PLATFORM_CTL_FLAGS_RAW); - platform::platform_read_ctl(0x300000 + 120, sizeof(dma.reads_faulty), &dma.reads_faulty, platform::PLATFORM_CTL_FLAGS_RAW); - platform::platform_read_ctl(0x300000 + 128, sizeof(dma.writes_faulty), &dma.writes_faulty, platform::PLATFORM_CTL_FLAGS_RAW); - platform::platform_read_ctl(0x300000 + 136, sizeof(dma.get_delay), &dma.get_delay, platform::PLATFORM_CTL_FLAGS_RAW); - platform::platform_read_ctl(0x300000 + 144, sizeof(dma.put_delay), &dma.put_delay, platform::PLATFORM_CTL_FLAGS_RAW); - platform::platform_read_ctl(0x300000 + 152, sizeof(dma.last_written), &dma.last_written, platform::PLATFORM_CTL_FLAGS_RAW); - platform::platform_read_ctl(0x300000 + 160, sizeof(dma.last_read), &dma.last_read, platform::PLATFORM_CTL_FLAGS_RAW); + platform::platform_read_ctl(0x300000 + 64, sizeof(dma.last_request), &dma.last_request, platform::PLATFORM_CTL_FLAGS_RAW); + platform::platform_read_ctl(0x300000 + 72, sizeof(dma.cycles_between), &dma.cycles_between, platform::PLATFORM_CTL_FLAGS_RAW); + platform::platform_read_ctl(0x300000 + 96, sizeof(dma.cycles_between_set), &dma.cycles_between_set, platform::PLATFORM_CTL_FLAGS_RAW); + ++dma.cycles_between_set; // Register contains num requests - 1 // Update Interrupt data uint32_t base_addr = 0x500000; @@ -97,13 +96,9 @@ private: uint64_t status; uint64_t read_requests; uint64_t write_requests; - uint64_t ack_count; - uint64_t reads_faulty; - uint64_t writes_faulty; - uint64_t get_delay; - uint64_t put_delay; - uint64_t last_written; - uint64_t last_read; + uint64_t last_request; + uint64_t cycles_between; + uint64_t cycles_between_set; }; struct interrupt_data { @@ -124,37 +119,33 @@ private: dma_regs dma; intr_regs intr; - const int32_t total_interrupts = 64; + const int32_t total_interrupts = 131; void render_dma(int start_row, int start_col) { - mvprintw(start_row++, start_col, "Host Address: %016lx, FPGA Address: %016lx", dma.host_addr, dma.fpga_addr); - mvprintw(start_row++, start_col, "Bytes to Transfer: %ld", dma.transfer_length); - mvprintw(start_row++, start_col, "Read requests: %ld, Reads faulty: %ld", dma.read_requests, dma.reads_faulty); - mvprintw(start_row++, start_col, "Write requests: %ld, Writes faulty: %ld", dma.write_requests, dma.writes_faulty); - mvprintw(start_row++, start_col, "ACKs: %ld", dma.ack_count); - mvprintw(start_row++, start_col, "Last written: %lx, Last read: %lx", dma.last_written, dma.last_read); - uint32_t total_gets = (dma.get_delay & 0xFFFFFFFF); - uint32_t total_puts = (dma.put_delay & 0xFFFFFFFF); - uint32_t get_delay = (dma.get_delay >> 32); - uint32_t put_delay = (dma.put_delay >> 32); - - double get_latency = (double) get_delay / (double) total_gets; - double put_latency = (double) put_delay / (double) total_puts; - - mvprintw(start_row++, start_col, "Put Delay: %f, Total Puts: %d %d", put_latency, total_puts, put_delay); - mvprintw(start_row++, start_col, "Get Delay: %f, Total Gets: %d %d", get_latency, total_gets, get_delay); + mvprintw(start_row++, start_col, "Host Address: %lx, FPGA Address: %lx", dma.host_addr, dma.fpga_addr); + + mvprintw(start_row++, start_col, "Transfer length: %ld, CMD: %lx", dma.transfer_length, dma.cmd); + + mvprintw(start_row++, start_col, "Read Requests: %ld, Write Requests: %ld", dma.read_requests, dma.write_requests); + float frequency = 250000000.0f; + float transfer_ms = (dma.last_request/frequency) * 1000; + float transfer_mib = ((1000.0f / transfer_ms) * dma.transfer_length) / (1024.0f * 1024.0f); + mvprintw(start_row++, start_col, "ms for last request: %f / %f MiB", transfer_ms, transfer_mib); + transfer_ms = ((dma.cycles_between/dma.cycles_between_set)/frequency) * 1000; + transfer_mib = ((1000.0f / transfer_ms) * dma.transfer_length) / (1024.0f * 1024.0f); + mvprintw(start_row++, start_col, "ms averaged over last %ld request(s): %f / %f MiB", dma.cycles_between_set, transfer_ms, transfer_mib); } void render_msix(int start_row, int start_col) { mvprintw(start_row++, start_col, "Core ID: %x", intr.core_id); - for(int i = 0; i < total_interrupts; ++i) { + for(int i = 0; i < 8; ++i) { if(!intr.interrupts[i].vector_control) { mvprintw(start_row++, start_col, "Interrupt %d Address: %016lx Data: %08x Vector: %08x", i, intr.interrupts[i].addr, intr.interrupts[i].data, intr.interrupts[i].vector_control); } } int pba_vecs = (total_interrupts / 64) + ((total_interrupts % 64) != 0); for(int i = 0; i < pba_vecs; ++i) { - mvprintw(start_row++, start_col, "PBA %d - %d: %16lx", i * 64, i * 64 + 63, intr.pba[i]); + mvprintw(start_row++, start_col, "PBA %3d - %3d: %16lx", i * 64, i * 64 + 63, intr.pba[i]); } mvprintw(start_row++, start_col, "Enable: %x Mask: %x", (intr.enableAndMask >> 16) & 0x1, intr.enableAndMask & 0x1); mvprintw(start_row++, start_col, "Sent Interrupts: %d", intr.sentInterrupts); diff --git a/common/ip/BlueDMA/component.xml b/common/ip/BlueDMA/component.xml index 61996520..eeaa28d8 100644 --- a/common/ip/BlueDMA/component.xml +++ b/common/ip/BlueDMA/component.xml @@ -175,14 +175,6 @@ - - - AWID - - - m32_axi_awid - - AWADDR @@ -327,14 +319,6 @@ m32_axi_wready - - - BID - - - m32_axi_bid - - BRESP @@ -367,14 +351,6 @@ m32_axi_bready - - - ARID - - - m32_axi_arid - - ARADDR @@ -471,14 +447,6 @@ m32_axi_arready - - - RID - - - m32_axi_rid - - RDATA @@ -551,14 +519,6 @@ - - - AWID - - - m64_axi_awid - - AWADDR @@ -703,14 +663,6 @@ m64_axi_wready - - - BID - - - m64_axi_bid - - BRESP @@ -743,14 +695,6 @@ m64_axi_bready - - - ARID - - - m64_axi_arid - - ARADDR @@ -847,14 +791,6 @@ m64_axi_arready - - - RID - - - m64_axi_rid - - RDATA @@ -1124,7 +1060,7 @@ viewChecksum - 6dca3063 + d8bbcf6d @@ -1140,7 +1076,7 @@ viewChecksum - 6dca3063 + d8bbcf6d @@ -1583,19 +1519,6 @@ - - m64_axi_arid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - m64_axi_araddr @@ -1787,22 +1710,6 @@ - - m64_axi_rid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - m64_axi_rdata @@ -1904,19 +1811,6 @@ - - m64_axi_awid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - m64_axi_awaddr @@ -2217,22 +2111,6 @@ - - m64_axi_bid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - m64_axi_buser @@ -2278,19 +2156,6 @@ - - m32_axi_arid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - m32_axi_araddr @@ -2482,22 +2347,6 @@ - - m32_axi_rid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - m32_axi_rdata @@ -2599,19 +2448,6 @@ - - m32_axi_awid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - m32_axi_awaddr @@ -2912,22 +2748,6 @@ - - m32_axi_bid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - m32_axi_buser @@ -2976,18 +2796,10 @@ xilinx_anylanguagesynthesis_view_fileset - - src/SyncHandshake.v - verilogSource - src/SyncFIFO1.v verilogSource - - src/SyncRegister.v - verilogSource - src/FIFO1.v verilogSource @@ -3011,23 +2823,15 @@ src/mkBlueDMAVivado.v verilogSource - CHECKSUM_031e6e27 + CHECKSUM_ded56ed9 xilinx_anylanguagebehavioralsimulation_view_fileset - - src/SyncHandshake.v - verilogSource - src/SyncFIFO1.v verilogSource - - src/SyncRegister.v - verilogSource - src/FIFO1.v verilogSource @@ -3083,18 +2887,18 @@ BlueDMA package_project 1 - 2017-07-07T08:39:29Z + 2017-07-07T14:29:44Z 2016.4 - + - - + + diff --git a/common/ip/BlueDMA/src/SyncHandshake.v b/common/ip/BlueDMA/src/SyncHandshake.v deleted file mode 100644 index 4e93eca1..00000000 --- a/common/ip/BlueDMA/src/SyncHandshake.v +++ /dev/null @@ -1,130 +0,0 @@ -// Copyright (c) 2000-2013 Bluespec, Inc. - -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: - -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. - -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. -// -// $Revision: 30617 $ -// $Date: 2013-02-20 17:47:41 +0000 (Wed, 20 Feb 2013) $ - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - - -// -// Transfer takes 2 dCLK to see data, -// sRDY recovers takes 2 dCLK + 2 sCLK -module SyncHandshake( - sCLK, - sRST, - dCLK, - sEN, - sRDY, - dPulse - ); - parameter init = 1'b0; - parameter delayreturn = 1'b0; - - // Source clock port signal - input sCLK ; - input sRST ; - input sEN ; - output sRDY ; - - // Destination clock port signal - input dCLK ; - output dPulse ; - - // Flops to hold data - reg dSyncReg1, dSyncReg2 ; - reg dLastState ; - reg sToggleReg ; - reg sSyncReg1, sSyncReg2 ; - - // Output signal - assign dPulse = dSyncReg2 != dLastState ; - assign sRDY = sSyncReg2 == sToggleReg; - wire ackValue = delayreturn ? dLastState : dSyncReg2 ; - - always @(posedge sCLK or `BSV_RESET_EDGE sRST) - begin - if (sRST == `BSV_RESET_VALUE) - begin - sSyncReg1 <= `BSV_ASSIGNMENT_DELAY ! init ; // Reset hi so sRDY is low during reset - sSyncReg2 <= `BSV_ASSIGNMENT_DELAY ! init ; - sToggleReg <= `BSV_ASSIGNMENT_DELAY init ; - end - else - begin - - // hadshake return synchronizer - sSyncReg1 <= `BSV_ASSIGNMENT_DELAY ackValue ;// clock domain crossing - sSyncReg2 <= `BSV_ASSIGNMENT_DELAY sSyncReg1 ; - - // Pulse send - if ( sEN ) - begin - sToggleReg <= `BSV_ASSIGNMENT_DELAY ! sToggleReg ; - end // if ( sEN ) - - end - end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST) - - always @(posedge dCLK or `BSV_RESET_EDGE sRST) - begin - if (sRST == `BSV_RESET_VALUE) - begin - dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init; - dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init; - dLastState <= `BSV_ASSIGNMENT_DELAY init ; - end - else - begin - dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sToggleReg ;// domain crossing - dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ; - dLastState <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ; - end - end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST) - -`ifdef BSV_NO_INITIAL_BLOCKS -`else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off - initial - begin - dSyncReg1 = init ; - dSyncReg2 = init ; - dLastState = init ; - - sToggleReg = init ; - sSyncReg1 = ! init ; - sSyncReg2 = ! init ; - - end // initial begin - // synopsys translate_on -`endif // BSV_NO_INITIAL_BLOCKS - -endmodule // HandshakeSync diff --git a/common/ip/BlueDMA/src/SyncRegister.v b/common/ip/BlueDMA/src/SyncRegister.v deleted file mode 100644 index b3fe7641..00000000 --- a/common/ip/BlueDMA/src/SyncRegister.v +++ /dev/null @@ -1,175 +0,0 @@ - -// Copyright (c) 2000-2013 Bluespec, Inc. - -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: - -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. - -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. -// -// $Revision: 30617 $ -// $Date: 2013-02-20 17:47:41 +0000 (Wed, 20 Feb 2013) $ - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - - -// A register synchronization module across clock domains. -// Uses a Handshake Pulse protocol to trigger the load on -// destination side registers -// Transfer takes 3 dCLK for destination side to see data, -// sRDY recovers takes 3 dCLK + 3 sCLK -module SyncRegister( - sCLK, - sRST, - dCLK, - sEN, - sRDY, - sD_IN, - dD_OUT - ); - parameter width = 1 ; - parameter init = { width {1'b0 }} ; - - // Source clock domain ports - input sCLK ; - input sRST ; - input sEN ; - input [width -1 : 0] sD_IN ; - output sRDY ; - - // Destination clock domain ports - input dCLK ; - output [width -1 : 0] dD_OUT ; - - wire dPulse ; - reg [width -1 : 0] sDataSyncIn ; - reg [width -1 : 0] dD_OUT ; - - // instantiate a Handshake Sync - SyncHandshake #(.init(0),.delayreturn(1)) - sync( .sCLK(sCLK), .sRST(sRST), - .dCLK(dCLK), - .sEN(sEN), .sRDY(sRDY), - .dPulse(dPulse) ) ; - - always @(posedge sCLK or `BSV_RESET_EDGE sRST) - begin - if (sRST == `BSV_RESET_VALUE) - begin - sDataSyncIn <= `BSV_ASSIGNMENT_DELAY init ; - end // if (sRST == `BSV_RESET_VALUE) - else - begin - if ( sEN ) - begin - sDataSyncIn <= `BSV_ASSIGNMENT_DELAY sD_IN ; - end // if ( sEN ) - end // else: !if(sRST == `BSV_RESET_VALUE) - end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST) - - - // Transfer the data to destination domain when dPulsed is asserted. - // Setup and hold time are assured since at least 2 dClks occured since - // sDataSyncIn have been written. - always @(posedge dCLK or `BSV_RESET_EDGE sRST) - begin - if (sRST == `BSV_RESET_VALUE) - begin - dD_OUT <= `BSV_ASSIGNMENT_DELAY init ; - end // if (sRST == `BSV_RESET_VALUE) - else - begin - if ( dPulse ) - begin - dD_OUT <= `BSV_ASSIGNMENT_DELAY sDataSyncIn ;// clock domain crossing - end // if ( dPulse ) - end // else: !if(sRST == `BSV_RESET_VALUE) - end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST) - - -`ifdef BSV_NO_INITIAL_BLOCKS -`else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off - initial - begin - sDataSyncIn = {((width + 1)/2){2'b10}} ; - dD_OUT = {((width + 1)/2){2'b10}} ; - end // initial begin - // synopsys translate_on -`endif // BSV_NO_INITIAL_BLOCKS - - -endmodule // RegisterSync - - - -`ifdef testBluespec -module testSyncRegister() ; - parameter dsize = 8; - - wire sCLK, sRST, dCLK ; - wire sEN ; - wire sRDY ; - - reg [dsize -1:0] sCNT ; - wire [dsize -1:0] sDIN, dDOUT ; - - ClockGen#(20,9,10) sc( sCLK ); - ClockGen#(11,12,26) dc( dCLK ); - - initial - begin - sCNT = 0; - - $dumpfile("SyncRegister.dump"); - $dumpvars(5) ; - $dumpon ; - #100000 $finish ; - end - - SyncRegister #(dsize) - dut( sCLK, sRST, dCLK, - sEN, sRDY, sDIN, - dDOUT ) ; - - - assign sDIN = sCNT ; - assign sEN = sRDY ; - - always @(posedge sCLK) - begin - if (sRDY ) - begin - sCNT <= `BSV_ASSIGNMENT_DELAY sCNT + 1; - end - end // always @ (posedge sCLK) - - - -endmodule // testSyncFIFO -`endif - - diff --git a/common/ip/BlueDMA/src/mkBlueDMA.v b/common/ip/BlueDMA/src/mkBlueDMA.v index 880a2d49..460dbcbf 100644 --- a/common/ip/BlueDMA/src/mkBlueDMA.v +++ b/common/ip/BlueDMA/src/mkBlueDMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07) // -// On Fri Jul 7 10:38:49 CEST 2017 +// On Fri Jul 7 14:37:16 CEST 2017 // // // Ports: @@ -15,7 +15,6 @@ // S_AXI_bvalid O 1 reg // S_AXI_bresp O 2 // pcie_rd_arvalid O 1 reg -// pcie_rd_arid O 1 // pcie_rd_araddr O 64 // pcie_rd_arlen O 8 // pcie_rd_arsize O 3 @@ -28,7 +27,6 @@ // pcie_rd_aruser O 1 // pcie_rd_rready O 1 reg // pcie_wr_awvalid O 1 reg -// pcie_wr_awid O 1 // pcie_wr_awaddr O 64 // pcie_wr_awlen O 8 // pcie_wr_awsize O 3 @@ -46,7 +44,6 @@ // pcie_wr_wuser O 1 // pcie_wr_bready O 1 reg // fpga_rd_arvalid O 1 reg -// fpga_rd_arid O 1 // fpga_rd_araddr O 64 // fpga_rd_arlen O 8 // fpga_rd_arsize O 3 @@ -59,7 +56,6 @@ // fpga_rd_aruser O 1 // fpga_rd_rready O 1 reg // fpga_wr_awvalid O 1 reg -// fpga_wr_awid O 1 // fpga_wr_awaddr O 64 // fpga_wr_awlen O 8 // fpga_wr_awsize O 3 @@ -96,7 +92,6 @@ // S_AXI_bready I 1 // pcie_rd_arready I 1 // pcie_rd_rvalid I 1 -// pcie_rd_rid I 1 reg // pcie_rd_rdata I 256 reg // pcie_rd_rresp I 2 reg // pcie_rd_rlast I 1 reg @@ -105,11 +100,9 @@ // pcie_wr_wready I 1 // pcie_wr_bvalid I 1 // pcie_wr_bresp I 2 reg -// pcie_wr_bid I 1 reg // pcie_wr_buser I 1 reg // fpga_rd_arready I 1 // fpga_rd_rvalid I 1 -// fpga_rd_rid I 1 reg // fpga_rd_rdata I 512 reg // fpga_rd_rresp I 2 reg // fpga_rd_rlast I 1 reg @@ -118,7 +111,6 @@ // fpga_wr_wready I 1 // fpga_wr_bvalid I 1 // fpga_wr_bresp I 2 reg -// fpga_wr_bid I 1 reg // fpga_wr_buser I 1 reg // // No combinational paths from inputs to outputs @@ -187,8 +179,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, pcie_rd_arready, - pcie_rd_arid, - pcie_rd_araddr, pcie_rd_arlen, @@ -213,7 +203,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, pcie_rd_rvalid, - pcie_rd_rid, pcie_rd_rdata, pcie_rd_rresp, pcie_rd_rlast, @@ -223,8 +212,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, pcie_wr_awvalid, - pcie_wr_awid, - pcie_wr_awaddr, pcie_wr_awlen, @@ -262,15 +249,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, pcie_wr_bready, pcie_wr_bresp, - pcie_wr_bid, pcie_wr_buser, fpga_rd_arvalid, fpga_rd_arready, - fpga_rd_arid, - fpga_rd_araddr, fpga_rd_arlen, @@ -295,7 +279,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_rd_rvalid, - fpga_rd_rid, fpga_rd_rdata, fpga_rd_rresp, fpga_rd_rlast, @@ -305,8 +288,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_wr_awvalid, - fpga_wr_awid, - fpga_wr_awaddr, fpga_wr_awlen, @@ -344,7 +325,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_wr_bready, fpga_wr_bresp, - fpga_wr_bid, fpga_wr_buser, interrupt); @@ -419,7 +399,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, input pcie_rd_arready; // value method pcie_rd_arid - output pcie_rd_arid; // value method pcie_rd_araddr output [63 : 0] pcie_rd_araddr; @@ -458,7 +437,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, input pcie_rd_rvalid; // action method pcie_rd_prchannel - input pcie_rd_rid; input [255 : 0] pcie_rd_rdata; input [1 : 0] pcie_rd_rresp; input pcie_rd_rlast; @@ -471,7 +449,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, output pcie_wr_awvalid; // value method pcie_wr_awid - output pcie_wr_awid; // value method pcie_wr_awaddr output [63 : 0] pcie_wr_awaddr; @@ -529,7 +506,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, // action method pcie_wr_bin input [1 : 0] pcie_wr_bresp; - input pcie_wr_bid; input pcie_wr_buser; // value method fpga_rd_arvalid @@ -539,7 +515,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, input fpga_rd_arready; // value method fpga_rd_arid - output fpga_rd_arid; // value method fpga_rd_araddr output [63 : 0] fpga_rd_araddr; @@ -578,7 +553,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, input fpga_rd_rvalid; // action method fpga_rd_prchannel - input fpga_rd_rid; input [511 : 0] fpga_rd_rdata; input [1 : 0] fpga_rd_rresp; input fpga_rd_rlast; @@ -591,7 +565,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, output fpga_wr_awvalid; // value method fpga_wr_awid - output fpga_wr_awid; // value method fpga_wr_awaddr output [63 : 0] fpga_wr_awaddr; @@ -649,7 +622,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, // action method fpga_wr_bin input [1 : 0] fpga_wr_bresp; - input fpga_wr_bid; input fpga_wr_buser; // value method interrupt @@ -697,12 +669,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, S_AXI_bvalid, S_AXI_rvalid, S_AXI_wready, - fpga_rd_arid, fpga_rd_arlock, fpga_rd_aruser, fpga_rd_arvalid, fpga_rd_rready, - fpga_wr_awid, fpga_wr_awlock, fpga_wr_awuser, fpga_wr_awvalid, @@ -711,12 +681,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_wr_wuser, fpga_wr_wvalid, interrupt, - pcie_rd_arid, pcie_rd_arlock, pcie_rd_aruser, pcie_rd_arvalid, pcie_rd_rready, - pcie_wr_awid, pcie_wr_awlock, pcie_wr_awuser, pcie_wr_awvalid, @@ -730,7 +698,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_master_wr_wawcache$wget, m_pcie_rd_master_rd_warcache$wget, m_pcie_wr_master_wr_wawcache$wget; - wire [516 : 0] m_fpga_rd_master_rd_rinpkg$wget; + wire [515 : 0] m_fpga_rd_master_rd_rinpkg$wget; wire [511 : 0] byteAlignerReader_buffer$port0__write_1, byteAlignerReader_buffer$port1__read, byteAlignerReader_buffer$port1__write_1, @@ -739,7 +707,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_buffer$port1__read, byteAlignerWriter_buffer$port1__write_1, byteAlignerWriter_buffer$port2__read; - wire [260 : 0] m_pcie_rd_master_rd_rinpkg$wget; + wire [259 : 0] m_pcie_rd_master_rd_rinpkg$wget; wire [192 : 0] readIn_rv$port1__read, readIn_rv$port1__write_1, readIn_rv$port2__read, @@ -757,7 +725,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_bytes_left_in_buffer$port0__write_1, byteAlignerWriter_bytes_left_in_buffer$port1__write_1, byteAlignerWriter_bytes_left_in_buffer$port2__read; - wire [3 : 0] m_fpga_wr_master_wr_rinpkg$wget, + wire [2 : 0] m_fpga_wr_master_wr_rinpkg$wget, m_pcie_wr_master_wr_rinpkg$wget; wire byteAlignerReader_buffer$EN_port0__write, byteAlignerReader_bytes_left_in_buffer$EN_port0__write, @@ -850,6 +818,26 @@ module mkBlueDMA(CLK_m32_axi_aclk, reg byteAlignerWriter_fetchedDatum; wire byteAlignerWriter_fetchedDatum$D_IN, byteAlignerWriter_fetchedDatum$EN; + // register clkCntr + reg [31 : 0] clkCntr; + wire [31 : 0] clkCntr$D_IN; + wire clkCntr$EN; + + // register cycles_between + reg [63 : 0] cycles_between; + wire [63 : 0] cycles_between$D_IN; + wire cycles_between$EN; + + // register cycles_between_set + reg [63 : 0] cycles_between_set; + wire [63 : 0] cycles_between_set$D_IN; + wire cycles_between_set$EN; + + // register cycles_last_request + reg [63 : 0] cycles_last_request; + wire [63 : 0] cycles_last_request$D_IN; + wire cycles_last_request$EN; + // register doneInterruptReg reg doneInterruptReg; wire doneInterruptReg$D_IN, doneInterruptReg$EN; @@ -863,26 +851,20 @@ module mkBlueDMA(CLK_m32_axi_aclk, wire [63 : 0] fpga_addr$D_IN; wire fpga_addr$EN; - // register fpga_addr_last_req - reg [63 : 0] fpga_addr_last_req; - wire [63 : 0] fpga_addr_last_req$D_IN; - wire fpga_addr_last_req$EN; - // register host_addr reg [63 : 0] host_addr; wire [63 : 0] host_addr$D_IN; wire host_addr$EN; - // register host_addr_last_req - reg [63 : 0] host_addr_last_req; - wire [63 : 0] host_addr_last_req$D_IN; - wire host_addr_last_req$EN; - // register id reg [63 : 0] id; wire [63 : 0] id$D_IN; wire id$EN; + // register isWriteActive + reg isWriteActive; + wire isWriteActive$D_IN, isWriteActive$EN; + // register m_fpga_rd_clkCntr reg [31 : 0] m_fpga_rd_clkCntr; wire [31 : 0] m_fpga_rd_clkCntr$D_IN; @@ -1017,6 +999,21 @@ module mkBlueDMA(CLK_m32_axi_aclk, reg opInProgress; wire opInProgress$D_IN, opInProgress$EN; + // register pc_betweenStart + reg [31 : 0] pc_betweenStart; + wire [31 : 0] pc_betweenStart$D_IN; + wire pc_betweenStart$EN; + + // register pc_reqCntr + reg [11 : 0] pc_reqCntr; + wire [11 : 0] pc_reqCntr$D_IN; + wire pc_reqCntr$EN; + + // register pc_start + reg [31 : 0] pc_start; + wire [31 : 0] pc_start$D_IN; + wire pc_start$EN; + // register pcieLastCycle reg pcieLastCycle; wire pcieLastCycle$D_IN, pcieLastCycle$EN; @@ -1049,11 +1046,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, wire [63 : 0] read_requests$D_IN; wire read_requests$EN; - // register reads_faulty - reg [63 : 0] reads_faulty; - wire [63 : 0] reads_faulty$D_IN; - wire reads_faulty$EN; - // register s_config_readBusy reg s_config_readBusy; wire s_config_readBusy$D_IN, s_config_readBusy$EN; @@ -1098,11 +1090,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, wire [63 : 0] write_requests$D_IN; wire write_requests$EN; - // register writes_faulty - reg [63 : 0] writes_faulty; - wire [63 : 0] writes_faulty$D_IN; - wire writes_faulty$EN; - // ports of submodule byteAlignerReader_addr_ff wire [191 : 0] byteAlignerReader_addr_ff$dD_OUT, byteAlignerReader_addr_ff$sD_IN; @@ -1163,14 +1150,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpgaDone$sENQ, fpgaDone$sFULL_N; - // ports of submodule fpga_get_delay - wire [63 : 0] fpga_get_delay$dD_OUT, fpga_get_delay$sD_IN; - wire fpga_get_delay$sEN, fpga_get_delay$sRDY; - - // ports of submodule fpga_read_4kbarriers - wire [63 : 0] fpga_read_4kbarriers$dD_OUT, fpga_read_4kbarriers$sD_IN; - wire fpga_read_4kbarriers$sEN, fpga_read_4kbarriers$sRDY; - // ports of submodule fpga_request_converter wire [511 : 0] fpga_request_converter$dD_OUT, fpga_request_converter$sD_IN; wire fpga_request_converter$dDEQ, @@ -1186,20 +1165,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_response_converter$sENQ, fpga_response_converter$sFULL_N; - // ports of submodule fpga_write_4kbarriers - wire [63 : 0] fpga_write_4kbarriers$dD_OUT, fpga_write_4kbarriers$sD_IN; - wire fpga_write_4kbarriers$sEN, fpga_write_4kbarriers$sRDY; - - // ports of submodule last_read_pcie - wire [63 : 0] last_read_pcie$dD_OUT, last_read_pcie$sD_IN; - wire last_read_pcie$sEN, last_read_pcie$sRDY; - - // ports of submodule last_written_pcie - wire [63 : 0] last_written_pcie$dD_OUT, last_written_pcie$sD_IN; - wire last_written_pcie$sEN, last_written_pcie$sRDY; - // ports of submodule m_fpga_rd_master_rd_in - wire [94 : 0] m_fpga_rd_master_rd_in$D_IN, m_fpga_rd_master_rd_in$D_OUT; + wire [93 : 0] m_fpga_rd_master_rd_in$D_IN, m_fpga_rd_master_rd_in$D_OUT; wire m_fpga_rd_master_rd_in$CLR, m_fpga_rd_master_rd_in$DEQ, m_fpga_rd_master_rd_in$EMPTY_N, @@ -1207,7 +1174,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_rd_master_rd_in$FULL_N; // ports of submodule m_fpga_rd_master_rd_out - wire [516 : 0] m_fpga_rd_master_rd_out$D_IN, m_fpga_rd_master_rd_out$D_OUT; + wire [515 : 0] m_fpga_rd_master_rd_out$D_IN, m_fpga_rd_master_rd_out$D_OUT; wire m_fpga_rd_master_rd_out$CLR, m_fpga_rd_master_rd_out$DEQ, m_fpga_rd_master_rd_out$EMPTY_N, @@ -1278,7 +1245,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_incomingBuffer$FULL_N; // ports of submodule m_fpga_wr_master_wr_in_addr - wire [94 : 0] m_fpga_wr_master_wr_in_addr$D_IN, + wire [93 : 0] m_fpga_wr_master_wr_in_addr$D_IN, m_fpga_wr_master_wr_in_addr$D_OUT; wire m_fpga_wr_master_wr_in_addr$CLR, m_fpga_wr_master_wr_in_addr$DEQ, @@ -1296,7 +1263,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_master_wr_in_data$FULL_N; // ports of submodule m_fpga_wr_master_wr_out - wire [3 : 0] m_fpga_wr_master_wr_out$D_IN; + wire [2 : 0] m_fpga_wr_master_wr_out$D_IN; wire m_fpga_wr_master_wr_out$CLR, m_fpga_wr_master_wr_out$DEQ, m_fpga_wr_master_wr_out$EMPTY_N, @@ -1340,7 +1307,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_reqGen_outgoingBuffer$FULL_N; // ports of submodule m_pcie_rd_master_rd_in - wire [94 : 0] m_pcie_rd_master_rd_in$D_IN, m_pcie_rd_master_rd_in$D_OUT; + wire [93 : 0] m_pcie_rd_master_rd_in$D_IN, m_pcie_rd_master_rd_in$D_OUT; wire m_pcie_rd_master_rd_in$CLR, m_pcie_rd_master_rd_in$DEQ, m_pcie_rd_master_rd_in$EMPTY_N, @@ -1348,7 +1315,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_rd_master_rd_in$FULL_N; // ports of submodule m_pcie_rd_master_rd_out - wire [260 : 0] m_pcie_rd_master_rd_out$D_IN, m_pcie_rd_master_rd_out$D_OUT; + wire [259 : 0] m_pcie_rd_master_rd_out$D_IN, m_pcie_rd_master_rd_out$D_OUT; wire m_pcie_rd_master_rd_out$CLR, m_pcie_rd_master_rd_out$DEQ, m_pcie_rd_master_rd_out$EMPTY_N, @@ -1419,7 +1386,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_wr_incomingBuffer$FULL_N; // ports of submodule m_pcie_wr_master_wr_in_addr - wire [94 : 0] m_pcie_wr_master_wr_in_addr$D_IN, + wire [93 : 0] m_pcie_wr_master_wr_in_addr$D_IN, m_pcie_wr_master_wr_in_addr$D_OUT; wire m_pcie_wr_master_wr_in_addr$CLR, m_pcie_wr_master_wr_in_addr$DEQ, @@ -1437,7 +1404,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_wr_master_wr_in_data$FULL_N; // ports of submodule m_pcie_wr_master_wr_out - wire [3 : 0] m_pcie_wr_master_wr_out$D_IN; + wire [2 : 0] m_pcie_wr_master_wr_out$D_IN; wire m_pcie_wr_master_wr_out$CLR, m_pcie_wr_master_wr_out$DEQ, m_pcie_wr_master_wr_out$EMPTY_N, @@ -1519,18 +1486,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, pcieDone$sENQ, pcieDone$sFULL_N; - // ports of submodule pcie_put_delay - wire [63 : 0] pcie_put_delay$dD_OUT, pcie_put_delay$sD_IN; - wire pcie_put_delay$sEN, pcie_put_delay$sRDY; - - // ports of submodule pcie_read_4kbarriers - wire [63 : 0] pcie_read_4kbarriers$dD_OUT, pcie_read_4kbarriers$sD_IN; - wire pcie_read_4kbarriers$sEN, pcie_read_4kbarriers$sRDY; - - // ports of submodule pcie_write_4kbarriers - wire [63 : 0] pcie_write_4kbarriers$dD_OUT, pcie_write_4kbarriers$sD_IN; - wire pcie_write_4kbarriers$sEN, pcie_write_4kbarriers$sRDY; - // ports of submodule readConvBTT_ff wire [64 : 0] readConvBTT_ff$dD_OUT, readConvBTT_ff$sD_IN; wire readConvBTT_ff$dDEQ, @@ -1623,18 +1578,13 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_1_axiWriteSpecial_1, WILL_FIRE_RL_s_config_1_axiWriteSpecial_2, WILL_FIRE_RL_s_config_1_axiWriteSpecial_3, + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4, + WILL_FIRE_RL_s_config_1_axiWriteSpecial_5, + WILL_FIRE_RL_s_config_1_axiWriteSpecial_6, WILL_FIRE_RL_s_config_axiReadFallback, WILL_FIRE_RL_s_config_axiReadSpecial, WILL_FIRE_RL_s_config_axiReadSpecialIsHandled, WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1, - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10, - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11, - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12, - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13, - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14, - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15, - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16, - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17, WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2, WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3, WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4, @@ -1642,16 +1592,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6, WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7, WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8, - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9, WILL_FIRE_RL_s_config_axiReadSpecial_1, - WILL_FIRE_RL_s_config_axiReadSpecial_10, - WILL_FIRE_RL_s_config_axiReadSpecial_11, - WILL_FIRE_RL_s_config_axiReadSpecial_12, - WILL_FIRE_RL_s_config_axiReadSpecial_13, - WILL_FIRE_RL_s_config_axiReadSpecial_14, - WILL_FIRE_RL_s_config_axiReadSpecial_15, - WILL_FIRE_RL_s_config_axiReadSpecial_16, - WILL_FIRE_RL_s_config_axiReadSpecial_17, WILL_FIRE_RL_s_config_axiReadSpecial_2, WILL_FIRE_RL_s_config_axiReadSpecial_3, WILL_FIRE_RL_s_config_axiReadSpecial_4, @@ -1659,7 +1600,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_axiReadSpecial_6, WILL_FIRE_RL_s_config_axiReadSpecial_7, WILL_FIRE_RL_s_config_axiReadSpecial_8, - WILL_FIRE_RL_s_config_axiReadSpecial_9, WILL_FIRE_RL_setInterrupt; // inputs to muxes for submodule ports @@ -1674,15 +1614,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, wire [74 : 0] MUX_m_pcie_rd_task_data_output_reg$write_1__VAL_1, MUX_m_pcie_wr_task_data_output_reg$write_1__VAL_1; wire [65 : 0] MUX_s_config_readSlave_out$enq_1__VAL_1, - MUX_s_config_readSlave_out$enq_1__VAL_10, - MUX_s_config_readSlave_out$enq_1__VAL_11, - MUX_s_config_readSlave_out$enq_1__VAL_12, - MUX_s_config_readSlave_out$enq_1__VAL_13, - MUX_s_config_readSlave_out$enq_1__VAL_14, - MUX_s_config_readSlave_out$enq_1__VAL_15, - MUX_s_config_readSlave_out$enq_1__VAL_16, - MUX_s_config_readSlave_out$enq_1__VAL_17, - MUX_s_config_readSlave_out$enq_1__VAL_18, MUX_s_config_readSlave_out$enq_1__VAL_2, MUX_s_config_readSlave_out$enq_1__VAL_3, MUX_s_config_readSlave_out$enq_1__VAL_4, @@ -1697,6 +1628,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, MUX_byteAlignerWriter_bytes_in$write_1__VAL_1, MUX_byteAlignerWriter_bytes_out$write_1__VAL_1, MUX_byteAlignerWriter_bytes_out$write_1__VAL_2, + MUX_cycles_between$write_1__VAL_1, + MUX_cycles_between$write_1__VAL_2, + MUX_cycles_last_request$write_1__VAL_1, + MUX_cycles_last_request$write_1__VAL_2, MUX_readConverter_byteCntr$write_1__VAL_2, MUX_writeConverter_byteCntr$write_1__VAL_2; wire [7 : 0] MUX_m_fpga_wr_beatsThisRequestCntr$write_1__VAL_1, @@ -1707,134 +1642,135 @@ module mkBlueDMA(CLK_m32_axi_aclk, MUX_byteAlignerWriter_bytes_out_needed$write_1__VAL_1; wire [1 : 0] MUX_writeConverter_wordInCntr$write_1__VAL_1, MUX_writeConverter_wordInCntr$write_1__VAL_2; - wire MUX_opInProgress$write_1__SEL_2; + wire MUX_cycles_between$write_1__SEL_1, MUX_opInProgress$write_1__SEL_2; // remaining internal signals reg [3 : 0] CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q5, CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q4, CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q3, CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q2; - wire [63 : 0] _theResult____h24288, - _theResult____h24472, - _theResult____h34242, - _theResult____h34426, - _theResult____h38131, - _theResult____h38315, - _theResult____h53478, - _theResult____h53662, - btt__h100105, - btt__h143147, - bytes_first___1__h24323, - bytes_first___1__h34277, - bytes_first___1__h38166, - bytes_first___1__h53513, - bytes_first__h24287, - bytes_first__h34241, - bytes_first__h38130, - bytes_first__h53477, + wire [63 : 0] _theResult____h26331, + _theResult____h26515, + _theResult____h36270, + _theResult____h36454, + _theResult____h40144, + _theResult____h40328, + _theResult____h55476, + _theResult____h55660, + btt__h102029, + btt__h145135, + bytes_first___1__h26366, + bytes_first___1__h36305, + bytes_first___1__h40179, + bytes_first___1__h55511, + bytes_first__h26330, + bytes_first__h36269, + bytes_first__h40143, + bytes_first__h55475, m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6, m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7, m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8, m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9, - request_data_address__h24612, - request_data_address__h34566, - request_data_address__h38455, - request_data_address__h53802, - transfers_total___1__h24480, - transfers_total___1__h34434, - transfers_total___1__h38323, - transfers_total___1__h53670, - transfers_total__h24471, - transfers_total__h24477, - transfers_total__h34425, - transfers_total__h34431, - transfers_total__h38314, - transfers_total__h38320, - transfers_total__h53661, - transfers_total__h53667, - x__h24293, - x__h24474, - x__h24500, - x__h34247, - x__h34428, - x__h34454, - x__h38136, - x__h38317, - x__h38343, - x__h53483, - x__h53664, - x__h53690, - x_address__h27534, - x_address__h36691, - x_address__h41362, - x_address__h55924, - x_strb__h41878, - y__h100142, - y__h143175, - y__h24367, - y__h24501, - y__h24503, - y__h34321, - y__h34455, - y__h34457, - y__h38210, - y__h38344, - y__h38346, - y__h53557, - y__h53691, - y__h53693; - wire [58 : 0] request_data_requests_total__h24611, - request_data_requests_total__h34565, - requests_total___1__h24637, - requests_total___1__h34591, - requests_total__h24575, - requests_total__h34529, - x_requests_total__h27533, - x_requests_total__h36690, - x_transfers_total__h33560, - x_transfers_total__h37140; - wire [57 : 0] request_data_requests_total__h38454, - request_data_requests_total__h53801, - requests_total___1__h38480, - requests_total___1__h53827, - requests_total__h38418, - requests_total__h53765, - x_requests_total__h41361, - x_requests_total__h55923, - x_transfers_total__h52796, - x_transfers_total__h56373; - wire [31 : 0] x_strb__h28050; - wire [7 : 0] _theResult____h27428, - _theResult____h41256, - beatsThisRequestCntrT__h27936, - beatsThisRequestCntrT__h41764, - beatsThisRequest___1__h27476, - beatsThisRequest___1__h36662, - beatsThisRequest___1__h41304, - beatsThisRequest___1__h55895, - requests_last__h24574, - requests_last__h34528; - wire [6 : 0] IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936, - endByte___1__h44787, - endByte___1__h44813, - startByte___1__h44786, - x__h44773; - wire [5 : 0] IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451, - b__h113489, - b__h70410, - endByte___1__h29551, - endByte___1__h29577, - startByte___1__h29550, - x__h29537; + request_data_address__h26655, + request_data_address__h36594, + request_data_address__h40468, + request_data_address__h55800, + transfers_total___1__h26523, + transfers_total___1__h36462, + transfers_total___1__h40336, + transfers_total___1__h55668, + transfers_total__h26514, + transfers_total__h26520, + transfers_total__h36453, + transfers_total__h36459, + transfers_total__h40327, + transfers_total__h40333, + transfers_total__h55659, + transfers_total__h55665, + x__h26336, + x__h26517, + x__h26543, + x__h36275, + x__h36456, + x__h36482, + x__h40149, + x__h40330, + x__h40356, + x__h55481, + x__h55662, + x__h55688, + x_address__h29562, + x_address__h38704, + x_address__h43360, + x_address__h57907, + x_strb__h43876, + y__h102066, + y__h145163, + y__h26410, + y__h26544, + y__h26546, + y__h36349, + y__h36483, + y__h36485, + y__h40223, + y__h40357, + y__h40359, + y__h55555, + y__h55689, + y__h55691; + wire [58 : 0] request_data_requests_total__h26654, + request_data_requests_total__h36593, + requests_total___1__h26680, + requests_total___1__h36619, + requests_total__h26618, + requests_total__h36557, + x_requests_total__h29561, + x_requests_total__h38703, + x_transfers_total__h35588, + x_transfers_total__h39153; + wire [57 : 0] request_data_requests_total__h40467, + request_data_requests_total__h55799, + requests_total___1__h40493, + requests_total___1__h55825, + requests_total__h40431, + requests_total__h55763, + x_requests_total__h43359, + x_requests_total__h57906, + x_transfers_total__h54794, + x_transfers_total__h58356; + wire [31 : 0] x_strb__h30078; + wire [7 : 0] _theResult____h29456, + _theResult____h43254, + beatsThisRequestCntrT__h29964, + beatsThisRequestCntrT__h43762, + beatsThisRequest___1__h29504, + beatsThisRequest___1__h38675, + beatsThisRequest___1__h43302, + beatsThisRequest___1__h57878, + requests_last__h26617, + requests_last__h36556; + wire [6 : 0] IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944, + endByte___1__h46785, + endByte___1__h46811, + startByte___1__h46784, + x__h46771; + wire [5 : 0] IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463, + b__h115415, + b__h72232, + endByte___1__h31579, + endByte___1__h31605, + startByte___1__h31578, + x__h31565; wire [1 : 0] IF_0_CONCAT_readConverter_wordInCntr_EQ_1_OR_r_ETC__q1; - wire byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440, - byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455, - byteAlignerWriter_bytes_in_559_ULT_byteAligner_ETC___d1561, - byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1576, - fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672, - m_fpga_wr_beatsThisRequestCntr_13_EQ_m_fpga_wr_ETC___d915, - m_pcie_wr_beatsThisRequestCntr_28_EQ_m_pcie_wr_ETC___d430, - pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665; + wire byteAlignerReader_bytes_in_430_ULT_byteAligner_ETC___d1432, + byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1447, + byteAlignerWriter_bytes_in_552_ULT_byteAligner_ETC___d1554, + byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1569, + fpgaLastCycle_662_AND_m_fpga_rd_task_data_outp_ETC___d1664, + m_fpga_wr_beatsThisRequestCntr_21_EQ_m_fpga_wr_ETC___d923, + m_pcie_wr_beatsThisRequestCntr_40_EQ_m_pcie_wr_ETC___d442, + pc_reqCntr_491_EQ_cycles_between_set_6_BITS_11_ETC___d1673, + pcieLastCycle_655_AND_m_pcie_rd_task_data_outp_ETC___d1657; // value method s_rd_arready assign S_AXI_arready = s_config_readSlave_in$FULL_N ; @@ -1872,11 +1808,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, // value method pcie_rd_arvalid assign pcie_rd_arvalid = m_pcie_rd_master_rd_in$EMPTY_N ; - // value method pcie_rd_arid - assign pcie_rd_arid = - m_pcie_rd_master_rd_in$EMPTY_N && - m_pcie_rd_master_rd_in$D_OUT[94] ; - // value method pcie_rd_araddr assign pcie_rd_araddr = m_pcie_rd_master_rd_in$EMPTY_N ? @@ -1942,11 +1873,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, // value method pcie_wr_awvalid assign pcie_wr_awvalid = m_pcie_wr_master_wr_in_addr$EMPTY_N ; - // value method pcie_wr_awid - assign pcie_wr_awid = - m_pcie_wr_master_wr_in_addr$EMPTY_N && - m_pcie_wr_master_wr_in_addr$D_OUT[94] ; - // value method pcie_wr_awaddr assign pcie_wr_awaddr = m_pcie_wr_master_wr_in_addr$EMPTY_N ? @@ -2037,11 +1963,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, // value method fpga_rd_arvalid assign fpga_rd_arvalid = m_fpga_rd_master_rd_in$EMPTY_N ; - // value method fpga_rd_arid - assign fpga_rd_arid = - m_fpga_rd_master_rd_in$EMPTY_N && - m_fpga_rd_master_rd_in$D_OUT[94] ; - // value method fpga_rd_araddr assign fpga_rd_araddr = m_fpga_rd_master_rd_in$EMPTY_N ? @@ -2107,11 +2028,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, // value method fpga_wr_awvalid assign fpga_wr_awvalid = m_fpga_wr_master_wr_in_addr$EMPTY_N ; - // value method fpga_wr_awid - assign fpga_wr_awid = - m_fpga_wr_master_wr_in_addr$EMPTY_N && - m_fpga_wr_master_wr_in_addr$D_OUT[94] ; - // value method fpga_wr_awaddr assign fpga_wr_awaddr = m_fpga_wr_master_wr_in_addr$EMPTY_N ? @@ -2294,26 +2210,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, .dEMPTY_N(fpgaDone$dEMPTY_N), .dD_OUT()); - // submodule fpga_get_delay - SyncRegister #(.width(32'd64), - .init(64'd4)) fpga_get_delay(.sCLK(CLK_m32_axi_aclk), - .dCLK(CLK), - .sRST(RST_N_m32_axi_arestn), - .sD_IN(fpga_get_delay$sD_IN), - .sEN(fpga_get_delay$sEN), - .sRDY(fpga_get_delay$sRDY), - .dD_OUT(fpga_get_delay$dD_OUT)); - - // submodule fpga_read_4kbarriers - SyncRegister #(.width(32'd64), - .init(64'd4)) fpga_read_4kbarriers(.sCLK(CLK_m32_axi_aclk), - .dCLK(CLK), - .sRST(RST_N_m32_axi_arestn), - .sD_IN(fpga_read_4kbarriers$sD_IN), - .sEN(fpga_read_4kbarriers$sEN), - .sRDY(fpga_read_4kbarriers$sRDY), - .dD_OUT(fpga_read_4kbarriers$dD_OUT)); - // submodule fpga_request_converter SyncFIFO #(.dataWidth(32'd512), .depth(32'd512), @@ -2340,38 +2236,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, .dEMPTY_N(fpga_response_converter$dEMPTY_N), .dD_OUT(fpga_response_converter$dD_OUT)); - // submodule fpga_write_4kbarriers - SyncRegister #(.width(32'd64), - .init(64'd4)) fpga_write_4kbarriers(.sCLK(CLK_m32_axi_aclk), - .dCLK(CLK), - .sRST(RST_N_m32_axi_arestn), - .sD_IN(fpga_write_4kbarriers$sD_IN), - .sEN(fpga_write_4kbarriers$sEN), - .sRDY(fpga_write_4kbarriers$sRDY), - .dD_OUT(fpga_write_4kbarriers$dD_OUT)); - - // submodule last_read_pcie - SyncRegister #(.width(32'd64), - .init(64'd4)) last_read_pcie(.sCLK(CLK_m64_axi_aclk), - .dCLK(CLK), - .sRST(RST_N_m64_axi_arestn), - .sD_IN(last_read_pcie$sD_IN), - .sEN(last_read_pcie$sEN), - .sRDY(last_read_pcie$sRDY), - .dD_OUT(last_read_pcie$dD_OUT)); - - // submodule last_written_pcie - SyncRegister #(.width(32'd64), - .init(64'd4)) last_written_pcie(.sCLK(CLK_m64_axi_aclk), - .dCLK(CLK), - .sRST(RST_N_m64_axi_arestn), - .sD_IN(last_written_pcie$sD_IN), - .sEN(last_written_pcie$sEN), - .sRDY(last_written_pcie$sRDY), - .dD_OUT(last_written_pcie$dD_OUT)); - // submodule m_fpga_rd_master_rd_in - SizedFIFO #(.p1width(32'd95), + SizedFIFO #(.p1width(32'd94), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) m_fpga_rd_master_rd_in(.RST(RST_N_m32_axi_arestn), @@ -2385,7 +2251,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_fpga_rd_master_rd_in$EMPTY_N)); // submodule m_fpga_rd_master_rd_out - FIFO2 #(.width(32'd517), + FIFO2 #(.width(32'd516), .guarded(32'd1)) m_fpga_rd_master_rd_out(.RST(RST_N_m32_axi_arestn), .CLK(CLK_m32_axi_aclk), .D_IN(m_fpga_rd_master_rd_out$D_IN), @@ -2483,7 +2349,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_fpga_wr_incomingBuffer$EMPTY_N)); // submodule m_fpga_wr_master_wr_in_addr - SizedFIFO #(.p1width(32'd95), + SizedFIFO #(.p1width(32'd94), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) m_fpga_wr_master_wr_in_addr(.RST(RST_N_m32_axi_arestn), @@ -2509,7 +2375,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_fpga_wr_master_wr_in_data$EMPTY_N)); // submodule m_fpga_wr_master_wr_out - FIFO2 #(.width(32'd4), + FIFO2 #(.width(32'd3), .guarded(32'd1)) m_fpga_wr_master_wr_out(.RST(RST_N_m32_axi_arestn), .CLK(CLK_m32_axi_aclk), .D_IN(m_fpga_wr_master_wr_out$D_IN), @@ -2569,7 +2435,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_fpga_wr_reqGen_outgoingBuffer$EMPTY_N)); // submodule m_pcie_rd_master_rd_in - SizedFIFO #(.p1width(32'd95), + SizedFIFO #(.p1width(32'd94), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) m_pcie_rd_master_rd_in(.RST(RST_N_m64_axi_arestn), @@ -2583,7 +2449,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_pcie_rd_master_rd_in$EMPTY_N)); // submodule m_pcie_rd_master_rd_out - FIFO2 #(.width(32'd261), + FIFO2 #(.width(32'd260), .guarded(32'd1)) m_pcie_rd_master_rd_out(.RST(RST_N_m64_axi_arestn), .CLK(CLK_m64_axi_aclk), .D_IN(m_pcie_rd_master_rd_out$D_IN), @@ -2681,7 +2547,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_pcie_wr_incomingBuffer$EMPTY_N)); // submodule m_pcie_wr_master_wr_in_addr - SizedFIFO #(.p1width(32'd95), + SizedFIFO #(.p1width(32'd94), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) m_pcie_wr_master_wr_in_addr(.RST(RST_N_m64_axi_arestn), @@ -2707,7 +2573,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_pcie_wr_master_wr_in_data$EMPTY_N)); // submodule m_pcie_wr_master_wr_out - FIFO2 #(.width(32'd4), + FIFO2 #(.width(32'd3), .guarded(32'd1)) m_pcie_wr_master_wr_out(.RST(RST_N_m64_axi_arestn), .CLK(CLK_m64_axi_aclk), .D_IN(m_pcie_wr_master_wr_out$D_IN), @@ -2821,36 +2687,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, .dEMPTY_N(pcieDone$dEMPTY_N), .dD_OUT()); - // submodule pcie_put_delay - SyncRegister #(.width(32'd64), - .init(64'd4)) pcie_put_delay(.sCLK(CLK_m64_axi_aclk), - .dCLK(CLK), - .sRST(RST_N_m64_axi_arestn), - .sD_IN(pcie_put_delay$sD_IN), - .sEN(pcie_put_delay$sEN), - .sRDY(pcie_put_delay$sRDY), - .dD_OUT(pcie_put_delay$dD_OUT)); - - // submodule pcie_read_4kbarriers - SyncRegister #(.width(32'd64), - .init(64'd4)) pcie_read_4kbarriers(.sCLK(CLK_m64_axi_aclk), - .dCLK(CLK), - .sRST(RST_N_m64_axi_arestn), - .sD_IN(pcie_read_4kbarriers$sD_IN), - .sEN(pcie_read_4kbarriers$sEN), - .sRDY(pcie_read_4kbarriers$sRDY), - .dD_OUT(pcie_read_4kbarriers$dD_OUT)); - - // submodule pcie_write_4kbarriers - SyncRegister #(.width(32'd64), - .init(64'd4)) pcie_write_4kbarriers(.sCLK(CLK_m64_axi_aclk), - .dCLK(CLK), - .sRST(RST_N_m64_axi_arestn), - .sD_IN(pcie_write_4kbarriers$sD_IN), - .sEN(pcie_write_4kbarriers$sEN), - .sRDY(pcie_write_4kbarriers$sRDY), - .dD_OUT(pcie_write_4kbarriers$dD_OUT)); - // submodule readConvBTT_ff SyncFIFO1 #(.dataWidth(32'd65)) readConvBTT_ff(.sCLK(CLK), .dCLK(CLK_m64_axi_aclk), @@ -2930,152 +2766,61 @@ module mkBlueDMA(CLK_m32_axi_aclk, .FULL_N(writeConverter_dataSync$FULL_N), .EMPTY_N(writeConverter_dataSync$EMPTY_N)); - // rule RL_setInterrupt - assign WILL_FIRE_RL_setInterrupt = - pcieDone$dEMPTY_N && fpgaDone$dEMPTY_N && opInProgress ; - // rule RL_s_config_axiReadSpecialIsHandled assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled = s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd0 ; + s_config_readSlave_in$D_OUT[9:6] == 4'd0 ; // rule RL_s_config_axiReadSpecialIsHandled_1 assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1 = s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd1 ; + s_config_readSlave_in$D_OUT[9:6] == 4'd1 ; // rule RL_s_config_axiReadSpecialIsHandled_2 assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 = s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd3 ; + s_config_readSlave_in$D_OUT[9:6] == 4'd8 ; // rule RL_s_config_axiReadSpecialIsHandled_3 assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 = s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd2 ; + s_config_readSlave_in$D_OUT[9:6] == 4'd9 ; // rule RL_s_config_axiReadSpecialIsHandled_4 assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 = s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd6 ; + s_config_readSlave_in$D_OUT[9:6] == 4'd12 ; // rule RL_s_config_axiReadSpecialIsHandled_5 assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_5 = s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd7 ; + s_config_readSlave_in$D_OUT[9:6] == 4'd3 ; // rule RL_s_config_axiReadSpecialIsHandled_6 assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 = s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd9 ; + s_config_readSlave_in$D_OUT[9:6] == 4'd2 ; // rule RL_s_config_axiReadSpecialIsHandled_7 assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 = s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd10 ; + s_config_readSlave_in$D_OUT[9:6] == 4'd6 ; // rule RL_s_config_axiReadSpecialIsHandled_8 assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 = s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd11 ; - - // rule RL_s_config_axiReadSpecialIsHandled_9 - assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 = - s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd12 ; - - // rule RL_s_config_axiReadSpecialIsHandled_10 - assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 = - s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd13 ; - - // rule RL_s_config_axiReadSpecialIsHandled_11 - assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 = - s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd14 ; - - // rule RL_s_config_axiReadSpecialIsHandled_12 - assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 = - s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd15 ; - - // rule RL_s_config_axiReadSpecialIsHandled_13 - assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 = - s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd16 ; - - // rule RL_s_config_axiReadSpecialIsHandled_14 - assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 = - s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd17 ; - - // rule RL_s_config_axiReadSpecialIsHandled_15 - assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 = - s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd18 ; - - // rule RL_s_config_axiReadSpecialIsHandled_16 - assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 = - s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd19 ; - - // rule RL_s_config_axiReadSpecialIsHandled_17 - assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17 = - s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd20 ; - - // rule RL_s_config_axiReadSpecial_2 - assign WILL_FIRE_RL_s_config_axiReadSpecial_2 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd3 && - !s_config_readBusy ; - - // rule RL_s_config_axiReadSpecial_4 - assign WILL_FIRE_RL_s_config_axiReadSpecial_4 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd6 && - !s_config_readBusy ; + s_config_readSlave_in$D_OUT[9:6] == 4'd7 ; // rule RL_s_config_axiReadSpecial_5 assign WILL_FIRE_RL_s_config_axiReadSpecial_5 = s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd7 && - !s_config_readBusy ; - - // rule RL_s_config_axiReadSpecial_6 - assign WILL_FIRE_RL_s_config_axiReadSpecial_6 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd9 && - !s_config_readBusy ; - - // rule RL_s_config_axiReadSpecial_8 - assign WILL_FIRE_RL_s_config_axiReadSpecial_8 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd11 && + s_config_readSlave_in$D_OUT[9:6] == 4'd3 && !s_config_readBusy ; // rule RL_s_config_axiReadSpecial_7 assign WILL_FIRE_RL_s_config_axiReadSpecial_7 = s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd10 && - !s_config_readBusy ; - - // rule RL_s_config_axiReadSpecial_9 - assign WILL_FIRE_RL_s_config_axiReadSpecial_9 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd12 && - !s_config_readBusy ; - - // rule RL_s_config_axiReadSpecial_10 - assign WILL_FIRE_RL_s_config_axiReadSpecial_10 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd13 && - !s_config_readBusy ; - - // rule RL_s_config_axiReadSpecial_11 - assign WILL_FIRE_RL_s_config_axiReadSpecial_11 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd14 && + s_config_readSlave_in$D_OUT[9:6] == 4'd6 && !s_config_readBusy ; // rule RL_handleRead @@ -3087,6 +2832,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign WILL_FIRE_RL_handleRead = CAN_FIRE_RL_handleRead && !WILL_FIRE_RL_handleWrite ; + // rule RL_s_config_axiReadSpecial_8 + assign WILL_FIRE_RL_s_config_axiReadSpecial_8 = + s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && + s_config_readSlave_in$D_OUT[9:6] == 4'd7 && + !s_config_readBusy ; + // rule RL_handleWrite assign WILL_FIRE_RL_handleWrite = writeIn_rv[192] && mclk_m_pcie_put_req_rd_ff$sFULL_N && @@ -3094,82 +2845,86 @@ module mkBlueDMA(CLK_m32_axi_aclk, writeConvBTT_ff$sFULL_N && !opInProgress ; - // rule RL_s_config_axiReadSpecial_12 - assign WILL_FIRE_RL_s_config_axiReadSpecial_12 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd15 && - !s_config_readBusy ; - - // rule RL_s_config_axiReadSpecial_13 - assign WILL_FIRE_RL_s_config_axiReadSpecial_13 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd16 && - !s_config_readBusy ; - - // rule RL_s_config_axiReadSpecial_14 - assign WILL_FIRE_RL_s_config_axiReadSpecial_14 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd17 && - !s_config_readBusy ; - - // rule RL_s_config_axiReadSpecial_15 - assign WILL_FIRE_RL_s_config_axiReadSpecial_15 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd18 && - !s_config_readBusy ; - - // rule RL_s_config_axiReadSpecial_16 - assign WILL_FIRE_RL_s_config_axiReadSpecial_16 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd19 && - !s_config_readBusy ; - - // rule RL_s_config_axiReadSpecial_17 - assign WILL_FIRE_RL_s_config_axiReadSpecial_17 = - s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd20 && - !s_config_readBusy ; - // rule RL_s_config_1_axiWriteSpecial assign WILL_FIRE_RL_s_config_1_axiWriteSpecial = s_config_writeSlave_in$EMPTY_N && s_config_writeSlave_out$FULL_N && cmdsIn$FULL_N && - s_config_writeSlave_in$D_OUT[82:78] == 5'd4 ; + s_config_writeSlave_in$D_OUT[81:78] == 4'd4 ; // rule RL_s_config_1_axiWriteSpecialIsHandled assign WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled = s_config_readSlave_in$EMPTY_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd4 ; + s_config_readSlave_in$D_OUT[9:6] == 4'd4 ; // rule RL_s_config_axiReadSpecial assign WILL_FIRE_RL_s_config_axiReadSpecial = s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd0 && + s_config_readSlave_in$D_OUT[9:6] == 4'd0 && !s_config_readBusy ; // rule RL_s_config_1_axiWriteSpecial_1 assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 = s_config_writeSlave_in$EMPTY_N && s_config_writeSlave_out$FULL_N && - s_config_writeSlave_in$D_OUT[82:78] == 5'd0 ; + s_config_writeSlave_in$D_OUT[81:78] == 4'd0 ; // rule RL_s_config_axiReadSpecial_1 assign WILL_FIRE_RL_s_config_axiReadSpecial_1 = s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd1 && + s_config_readSlave_in$D_OUT[9:6] == 4'd1 && !s_config_readBusy ; // rule RL_s_config_1_axiWriteSpecial_2 assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 = s_config_writeSlave_in$EMPTY_N && s_config_writeSlave_out$FULL_N && - s_config_writeSlave_in$D_OUT[82:78] == 5'd1 ; + s_config_writeSlave_in$D_OUT[81:78] == 4'd1 ; + + // rule RL_s_config_axiReadSpecial_2 + assign WILL_FIRE_RL_s_config_axiReadSpecial_2 = + s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && + s_config_readSlave_in$D_OUT[9:6] == 4'd8 && + !s_config_readBusy ; + + // rule RL_s_config_1_axiWriteSpecial_3 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 = + s_config_writeSlave_in$EMPTY_N && + s_config_writeSlave_out$FULL_N && + s_config_writeSlave_in$D_OUT[81:78] == 4'd8 ; // rule RL_s_config_axiReadSpecial_3 assign WILL_FIRE_RL_s_config_axiReadSpecial_3 = s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && - s_config_readSlave_in$D_OUT[10:6] == 5'd2 && + s_config_readSlave_in$D_OUT[9:6] == 4'd9 && + !s_config_readBusy ; + + // rule RL_s_config_1_axiWriteSpecial_4 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 = + s_config_writeSlave_in$EMPTY_N && + s_config_writeSlave_out$FULL_N && + s_config_writeSlave_in$D_OUT[81:78] == 4'd9 ; + + // rule RL_setInterrupt + assign WILL_FIRE_RL_setInterrupt = + pcieDone$dEMPTY_N && fpgaDone$dEMPTY_N && opInProgress ; + + // rule RL_s_config_axiReadSpecial_4 + assign WILL_FIRE_RL_s_config_axiReadSpecial_4 = + s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && + s_config_readSlave_in$D_OUT[9:6] == 4'd12 && + !s_config_readBusy ; + + // rule RL_s_config_1_axiWriteSpecial_5 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 = + s_config_writeSlave_in$EMPTY_N && + s_config_writeSlave_out$FULL_N && + s_config_writeSlave_in$D_OUT[81:78] == 4'd12 ; + + // rule RL_s_config_axiReadSpecial_6 + assign WILL_FIRE_RL_s_config_axiReadSpecial_6 = + s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && + s_config_readSlave_in$D_OUT[9:6] == 4'd2 && !s_config_readBusy ; // rule RL_s_config_axiReadFallback @@ -3177,17 +2932,20 @@ module mkBlueDMA(CLK_m32_axi_aclk, s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N && !s_config_readIsHandled$whas ; - // rule RL_s_config_1_axiWriteSpecial_3 - assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 = + // rule RL_s_config_1_axiWriteSpecial_6 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 = s_config_writeSlave_in$EMPTY_N && s_config_writeSlave_out$FULL_N && - s_config_writeSlave_in$D_OUT[82:78] == 5'd2 ; + s_config_writeSlave_in$D_OUT[81:78] == 4'd2 ; // rule RL_s_config_1_axiWriteFallback assign WILL_FIRE_RL_s_config_1_axiWriteFallback = s_config_writeSlave_in$EMPTY_N && s_config_writeSlave_out$FULL_N && !s_config_writeIsHandled$whas && + !WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && + !WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + !WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && !WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && !WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 && !WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 && @@ -3305,7 +3063,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerReader_outgoing$FULL_N && !byteAlignerReader_addr_ff$dEMPTY_N && byteAlignerReader_fetchedDatum && - !byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 && + !byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1447 && !byteAlignerReader_addr_ff$dEMPTY_N ; // rule RL_byteAlignerReader_fetchNewData @@ -3313,7 +3071,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerReader_incoming$EMPTY_N && !byteAlignerReader_addr_ff$dEMPTY_N && !byteAlignerReader_fetchedDatum$port1__read && - byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 && + byteAlignerReader_bytes_in_430_ULT_byteAligner_ETC___d1432 && !byteAlignerReader_addr_ff$dEMPTY_N ; // rule RL_byteAlignerReader_forwardOutputLast @@ -3321,7 +3079,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerReader_outgoing$FULL_N && !byteAlignerReader_addr_ff$dEMPTY_N && !byteAlignerReader_fetchedDatum && - !byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 && + !byteAlignerReader_bytes_in_430_ULT_byteAligner_ETC___d1432 && byteAlignerReader_bytes_out < byteAlignerReader_bytes_total ; assign WILL_FIRE_RL_byteAlignerReader_forwardOutputLast = CAN_FIRE_RL_byteAlignerReader_forwardOutputLast && @@ -3338,7 +3096,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_outgoing$FULL_N && !byteAlignerWriter_addr_ff$dEMPTY_N && byteAlignerWriter_fetchedDatum && - !byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1576 && + !byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1569 && !byteAlignerWriter_addr_ff$dEMPTY_N ; // rule RL_byteAlignerWriter_fetchNewData @@ -3346,7 +3104,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_incoming$EMPTY_N && !byteAlignerWriter_addr_ff$dEMPTY_N && !byteAlignerWriter_fetchedDatum$port1__read && - byteAlignerWriter_bytes_in_559_ULT_byteAligner_ETC___d1561 && + byteAlignerWriter_bytes_in_552_ULT_byteAligner_ETC___d1554 && !byteAlignerWriter_addr_ff$dEMPTY_N ; // rule RL_byteAlignerWriter_forwardOutputLast @@ -3354,13 +3112,16 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_outgoing$FULL_N && !byteAlignerWriter_addr_ff$dEMPTY_N && !byteAlignerWriter_fetchedDatum && - !byteAlignerWriter_bytes_in_559_ULT_byteAligner_ETC___d1561 && + !byteAlignerWriter_bytes_in_552_ULT_byteAligner_ETC___d1554 && byteAlignerWriter_bytes_out < byteAlignerWriter_bytes_total ; assign WILL_FIRE_RL_byteAlignerWriter_forwardOutputLast = CAN_FIRE_RL_byteAlignerWriter_forwardOutputLast && !byteAlignerWriter_addr_ff$dEMPTY_N ; // inputs to muxes for submodule ports + assign MUX_cycles_between$write_1__SEL_1 = + WILL_FIRE_RL_setInterrupt && + pc_reqCntr_491_EQ_cycles_between_set_6_BITS_11_ETC___d1673 ; assign MUX_opInProgress$write_1__SEL_2 = WILL_FIRE_RL_handleRead || WILL_FIRE_RL_handleWrite ; assign MUX_byteAlignerReader_buffer$port0__write_1__VAL_1 = @@ -3391,82 +3152,119 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_bytes_out + 64'd256 ; assign MUX_byteAlignerWriter_bytes_out_needed$write_1__VAL_1 = 6'd32 - { 1'd0, byteAlignerWriter_addr_ff$dD_OUT[68:64] } ; + assign MUX_cycles_between$write_1__VAL_1 = + { 32'd0, clkCntr - pc_betweenStart } ; + assign MUX_cycles_between$write_1__VAL_2 = + { s_config_writeSlave_in$D_OUT[10] ? + s_config_writeSlave_in$D_OUT[74:67] : + cycles_between[63:56], + s_config_writeSlave_in$D_OUT[9] ? + s_config_writeSlave_in$D_OUT[66:59] : + cycles_between[55:48], + s_config_writeSlave_in$D_OUT[8] ? + s_config_writeSlave_in$D_OUT[58:51] : + cycles_between[47:40], + s_config_writeSlave_in$D_OUT[7] ? + s_config_writeSlave_in$D_OUT[50:43] : + cycles_between[39:32], + s_config_writeSlave_in$D_OUT[6] ? + s_config_writeSlave_in$D_OUT[42:35] : + cycles_between[31:24], + s_config_writeSlave_in$D_OUT[5] ? + s_config_writeSlave_in$D_OUT[34:27] : + cycles_between[23:16], + s_config_writeSlave_in$D_OUT[4] ? + s_config_writeSlave_in$D_OUT[26:19] : + cycles_between[15:8], + s_config_writeSlave_in$D_OUT[3] ? + s_config_writeSlave_in$D_OUT[18:11] : + cycles_between[7:0] } ; + assign MUX_cycles_last_request$write_1__VAL_1 = + { 32'd0, clkCntr - pc_start } ; + assign MUX_cycles_last_request$write_1__VAL_2 = + { s_config_writeSlave_in$D_OUT[10] ? + s_config_writeSlave_in$D_OUT[74:67] : + cycles_last_request[63:56], + s_config_writeSlave_in$D_OUT[9] ? + s_config_writeSlave_in$D_OUT[66:59] : + cycles_last_request[55:48], + s_config_writeSlave_in$D_OUT[8] ? + s_config_writeSlave_in$D_OUT[58:51] : + cycles_last_request[47:40], + s_config_writeSlave_in$D_OUT[7] ? + s_config_writeSlave_in$D_OUT[50:43] : + cycles_last_request[39:32], + s_config_writeSlave_in$D_OUT[6] ? + s_config_writeSlave_in$D_OUT[42:35] : + cycles_last_request[31:24], + s_config_writeSlave_in$D_OUT[5] ? + s_config_writeSlave_in$D_OUT[34:27] : + cycles_last_request[23:16], + s_config_writeSlave_in$D_OUT[4] ? + s_config_writeSlave_in$D_OUT[26:19] : + cycles_last_request[15:8], + s_config_writeSlave_in$D_OUT[3] ? + s_config_writeSlave_in$D_OUT[18:11] : + cycles_last_request[7:0] } ; assign MUX_m_fpga_rd_task_data_output_reg$write_1__VAL_1 = { m_fpga_rd_task_data_output_reg[76:65], - x_transfers_total__h56373, + x_transfers_total__h58356, m_fpga_rd_task_data_output_reg[6:0] } ; assign MUX_m_fpga_rd_task_data_requests_reg$write_1__VAL_1 = { m_fpga_rd_task_data_requests_reg[133:126], - x_requests_total__h55923, - x_address__h55924, + x_requests_total__h57906, + x_address__h57907, m_fpga_rd_task_data_requests_reg[3:0] } ; assign MUX_m_fpga_wr_beatsThisRequestCntr$write_1__VAL_1 = - m_fpga_wr_beatsThisRequestCntr_13_EQ_m_fpga_wr_ETC___d915 ? + m_fpga_wr_beatsThisRequestCntr_21_EQ_m_fpga_wr_ETC___d923 ? 8'd0 : - beatsThisRequestCntrT__h41764 ; + beatsThisRequestCntrT__h43762 ; assign MUX_m_fpga_wr_task_data_output_reg$write_1__VAL_1 = { m_fpga_wr_task_data_output_reg[76:65], - x_transfers_total__h52796, + x_transfers_total__h54794, m_fpga_wr_task_data_output_reg[6:1], 1'd0 } ; assign MUX_m_fpga_wr_task_data_requests_reg$write_1__VAL_1 = { m_fpga_wr_task_data_requests_reg[133:126], - x_requests_total__h41361, - x_address__h41362, + x_requests_total__h43359, + x_address__h43360, m_fpga_wr_task_data_requests_reg[3:0] } ; assign MUX_m_pcie_rd_task_data_output_reg$write_1__VAL_1 = { m_pcie_rd_task_data_output_reg[74:65], - x_transfers_total__h37140, + x_transfers_total__h39153, m_pcie_rd_task_data_output_reg[5:0] } ; assign MUX_m_pcie_rd_task_data_requests_reg$write_1__VAL_1 = { m_pcie_rd_task_data_requests_reg[134:127], - x_requests_total__h36690, - x_address__h36691, + x_requests_total__h38703, + x_address__h38704, m_pcie_rd_task_data_requests_reg[3:0] } ; assign MUX_m_pcie_wr_beatsThisRequestCntr$write_1__VAL_1 = - m_pcie_wr_beatsThisRequestCntr_28_EQ_m_pcie_wr_ETC___d430 ? + m_pcie_wr_beatsThisRequestCntr_40_EQ_m_pcie_wr_ETC___d442 ? 8'd0 : - beatsThisRequestCntrT__h27936 ; + beatsThisRequestCntrT__h29964 ; assign MUX_m_pcie_wr_task_data_output_reg$write_1__VAL_1 = { m_pcie_wr_task_data_output_reg[74:65], - x_transfers_total__h33560, + x_transfers_total__h35588, m_pcie_wr_task_data_output_reg[5:1], 1'd0 } ; assign MUX_m_pcie_wr_task_data_requests_reg$write_1__VAL_1 = { m_pcie_wr_task_data_requests_reg[134:127], - x_requests_total__h27533, - x_address__h27534, + x_requests_total__h29561, + x_address__h29562, m_pcie_wr_task_data_requests_reg[3:0] } ; assign MUX_readConverter_byteCntr$write_1__VAL_2 = readConverter_byteCntr - 64'd32 ; assign MUX_s_config_readSlave_out$enq_1__VAL_1 = { host_addr, 2'd0 } ; assign MUX_s_config_readSlave_out$enq_1__VAL_2 = { fpga_addr, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_3 = { id, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_4 = { transfer_length, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_5 = { read_requests, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_6 = { write_requests, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_7 = - { fpga_write_4kbarriers$dD_OUT, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_8 = - { fpga_read_4kbarriers$dD_OUT, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_9 = - { pcie_write_4kbarriers$dD_OUT, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_10 = - { pcie_read_4kbarriers$dD_OUT, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_11 = - { host_addr_last_req, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_12 = - { fpga_addr_last_req, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_13 = { reads_faulty, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_14 = { writes_faulty, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_15 = - { fpga_get_delay$dD_OUT, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_16 = - { pcie_put_delay$dD_OUT, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_17 = - { last_written_pcie$dD_OUT, 2'd0 } ; - assign MUX_s_config_readSlave_out$enq_1__VAL_18 = - { last_read_pcie$dD_OUT, 2'd0 } ; + assign MUX_s_config_readSlave_out$enq_1__VAL_3 = + { cycles_last_request, 2'd0 } ; + assign MUX_s_config_readSlave_out$enq_1__VAL_4 = { cycles_between, 2'd0 } ; + assign MUX_s_config_readSlave_out$enq_1__VAL_5 = + { cycles_between_set, 2'd0 } ; + assign MUX_s_config_readSlave_out$enq_1__VAL_6 = { id, 2'd0 } ; + assign MUX_s_config_readSlave_out$enq_1__VAL_7 = { transfer_length, 2'd0 } ; + assign MUX_s_config_readSlave_out$enq_1__VAL_8 = { read_requests, 2'd0 } ; + assign MUX_s_config_readSlave_out$enq_1__VAL_9 = { write_requests, 2'd0 } ; assign MUX_writeConverter_byteCntr$write_1__VAL_2 = writeConverter_byteCntr - 64'd32 ; assign MUX_writeConverter_wordInCntr$write_1__VAL_1 = @@ -3479,15 +3277,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, // inlined wires assign s_config_readIsHandled$whas = - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 || @@ -3498,7 +3287,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled ; assign s_config_writeIsHandled$whas = + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled || WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled ; @@ -3538,22 +3330,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, default: m_fpga_rd_master_rd_warcache$wget = 4'd11; endcase end - assign m_pcie_wr_master_wr_rinpkg$wget = - { pcie_wr_bid, pcie_wr_bresp, pcie_wr_buser } ; + assign m_pcie_wr_master_wr_rinpkg$wget = { pcie_wr_bresp, pcie_wr_buser } ; assign m_pcie_rd_master_rd_rinpkg$wget = - { pcie_rd_rid, - pcie_rd_rdata, - pcie_rd_rresp, - pcie_rd_rlast, - pcie_rd_ruser } ; - assign m_fpga_wr_master_wr_rinpkg$wget = - { fpga_wr_bid, fpga_wr_bresp, fpga_wr_buser } ; + { pcie_rd_rdata, pcie_rd_rresp, pcie_rd_rlast, pcie_rd_ruser } ; + assign m_fpga_wr_master_wr_rinpkg$wget = { fpga_wr_bresp, fpga_wr_buser } ; assign m_fpga_rd_master_rd_rinpkg$wget = - { fpga_rd_rid, - fpga_rd_rdata, - fpga_rd_rresp, - fpga_rd_rlast, - fpga_rd_ruser } ; + { fpga_rd_rdata, fpga_rd_rresp, fpga_rd_rlast, fpga_rd_ruser } ; assign s_config_writeSlave_addrIn_rv$EN_port0__write = !s_config_writeSlave_addrIn_rv[67] && S_AXI_awvalid ; assign s_config_writeSlave_addrIn_rv$port0__write_1 = @@ -3647,16 +3429,16 @@ module mkBlueDMA(CLK_m32_axi_aclk, MUX_byteAlignerReader_bytes_left_in_buffer$port0__write_1__VAL_1 : 6'd0 ; assign byteAlignerReader_bytes_left_in_buffer$port1__write_1 = - b__h70410 + 6'd32 ; + b__h72232 + 6'd32 ; assign byteAlignerReader_bytes_left_in_buffer$port2__read = WILL_FIRE_RL_byteAlignerReader_fetchNewData ? byteAlignerReader_bytes_left_in_buffer$port1__write_1 : - b__h70410 ; + b__h72232 ; assign byteAlignerReader_fetchedDatum$EN_port0__write = byteAlignerReader_addr_ff$dEMPTY_N || !byteAlignerReader_addr_ff$dEMPTY_N && byteAlignerReader_fetchedDatum && - byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 || + byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1447 || WILL_FIRE_RL_byteAlignerReader_forwardOutput ; assign byteAlignerReader_fetchedDatum$port1__read = !byteAlignerReader_fetchedDatum$EN_port0__write && @@ -3690,16 +3472,16 @@ module mkBlueDMA(CLK_m32_axi_aclk, MUX_byteAlignerWriter_bytes_left_in_buffer$port0__write_1__VAL_1 : 6'd0 ; assign byteAlignerWriter_bytes_left_in_buffer$port1__write_1 = - b__h113489 + 6'd32 ; + b__h115415 + 6'd32 ; assign byteAlignerWriter_bytes_left_in_buffer$port2__read = WILL_FIRE_RL_byteAlignerWriter_fetchNewData ? byteAlignerWriter_bytes_left_in_buffer$port1__write_1 : - b__h113489 ; + b__h115415 ; assign byteAlignerWriter_fetchedDatum$EN_port0__write = byteAlignerWriter_addr_ff$dEMPTY_N || !byteAlignerWriter_addr_ff$dEMPTY_N && byteAlignerWriter_fetchedDatum && - byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1576 || + byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1569 || WILL_FIRE_RL_byteAlignerWriter_forwardOutput ; assign byteAlignerWriter_fetchedDatum$port1__read = !byteAlignerWriter_fetchedDatum$EN_port0__write && @@ -3836,6 +3618,57 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_fetchedDatum$port2__read ; assign byteAlignerWriter_fetchedDatum$EN = 1'b1 ; + // register clkCntr + assign clkCntr$D_IN = clkCntr + 32'd1 ; + assign clkCntr$EN = 1'd1 ; + + // register cycles_between + assign cycles_between$D_IN = + MUX_cycles_between$write_1__SEL_1 ? + MUX_cycles_between$write_1__VAL_1 : + MUX_cycles_between$write_1__VAL_2 ; + assign cycles_between$EN = + WILL_FIRE_RL_setInterrupt && + pc_reqCntr_491_EQ_cycles_between_set_6_BITS_11_ETC___d1673 || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 ; + + // register cycles_between_set + assign cycles_between_set$D_IN = + { s_config_writeSlave_in$D_OUT[10] ? + s_config_writeSlave_in$D_OUT[74:67] : + cycles_between_set[63:56], + s_config_writeSlave_in$D_OUT[9] ? + s_config_writeSlave_in$D_OUT[66:59] : + cycles_between_set[55:48], + s_config_writeSlave_in$D_OUT[8] ? + s_config_writeSlave_in$D_OUT[58:51] : + cycles_between_set[47:40], + s_config_writeSlave_in$D_OUT[7] ? + s_config_writeSlave_in$D_OUT[50:43] : + cycles_between_set[39:32], + s_config_writeSlave_in$D_OUT[6] ? + s_config_writeSlave_in$D_OUT[42:35] : + cycles_between_set[31:24], + s_config_writeSlave_in$D_OUT[5] ? + s_config_writeSlave_in$D_OUT[34:27] : + cycles_between_set[23:16], + s_config_writeSlave_in$D_OUT[4] ? + s_config_writeSlave_in$D_OUT[26:19] : + cycles_between_set[15:8], + s_config_writeSlave_in$D_OUT[3] ? + s_config_writeSlave_in$D_OUT[18:11] : + cycles_between_set[7:0] } ; + assign cycles_between_set$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 ; + + // register cycles_last_request + assign cycles_last_request$D_IN = + WILL_FIRE_RL_setInterrupt ? + MUX_cycles_last_request$write_1__VAL_1 : + MUX_cycles_last_request$write_1__VAL_2 ; + assign cycles_last_request$EN = + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 || + WILL_FIRE_RL_setInterrupt ; + // register doneInterruptReg assign doneInterruptReg$D_IN = WILL_FIRE_RL_setInterrupt ; assign doneInterruptReg$EN = 1'd1 ; @@ -3876,13 +3709,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_addr[7:0] } ; assign fpga_addr$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 ; - // register fpga_addr_last_req - assign fpga_addr_last_req$D_IN = - WILL_FIRE_RL_handleRead ? - readIn_rv[127:64] : - writeIn_rv[127:64] ; - assign fpga_addr_last_req$EN = MUX_opInProgress$write_1__SEL_2 ; - // register host_addr assign host_addr$D_IN = { s_config_writeSlave_in$D_OUT[10] ? @@ -3911,17 +3737,14 @@ module mkBlueDMA(CLK_m32_axi_aclk, host_addr[7:0] } ; assign host_addr$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 ; - // register host_addr_last_req - assign host_addr_last_req$D_IN = - WILL_FIRE_RL_handleRead ? - readIn_rv[191:128] : - writeIn_rv[191:128] ; - assign host_addr_last_req$EN = MUX_opInProgress$write_1__SEL_2 ; - // register id assign id$D_IN = 64'h0 ; assign id$EN = 1'b0 ; + // register isWriteActive + assign isWriteActive$D_IN = !WILL_FIRE_RL_handleRead ; + assign isWriteActive$EN = MUX_opInProgress$write_1__SEL_2 ; + // register m_fpga_rd_clkCntr assign m_fpga_rd_clkCntr$D_IN = m_fpga_rd_clkCntr + 32'd1 ; assign m_fpga_rd_clkCntr$EN = 1'd1 ; @@ -4082,6 +3905,22 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_setInterrupt || WILL_FIRE_RL_handleRead || WILL_FIRE_RL_handleWrite ; + // register pc_betweenStart + assign pc_betweenStart$D_IN = clkCntr ; + assign pc_betweenStart$EN = + MUX_opInProgress$write_1__SEL_2 && pc_reqCntr == 12'd0 ; + + // register pc_reqCntr + assign pc_reqCntr$D_IN = + pc_reqCntr_491_EQ_cycles_between_set_6_BITS_11_ETC___d1673 ? + 12'd0 : + pc_reqCntr + 12'd1 ; + assign pc_reqCntr$EN = WILL_FIRE_RL_setInterrupt ; + + // register pc_start + assign pc_start$D_IN = clkCntr ; + assign pc_start$EN = MUX_opInProgress$write_1__SEL_2 ; + // register pcieLastCycle assign pcieLastCycle$D_IN = m_pcie_rd_task_data_output_reg[64:6] != 59'd0 || @@ -4123,10 +3962,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign read_requests$D_IN = read_requests + 64'd1 ; assign read_requests$EN = WILL_FIRE_RL_handleRead ; - // register reads_faulty - assign reads_faulty$D_IN = 64'h0 ; - assign reads_faulty$EN = 1'b0 ; - // register s_config_readBusy assign s_config_readBusy$D_IN = 1'b0 ; assign s_config_readBusy$EN = 1'b0 ; @@ -4167,7 +4002,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, s_config_writeSlave_in$D_OUT[3] ? s_config_writeSlave_in$D_OUT[18:11] : transfer_length[7:0] } ; - assign transfer_length$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 ; + assign transfer_length$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 ; // register writeConverter_buffer_0 assign writeConverter_buffer_0$D_IN = m_pcie_rd_outgoingBuffer$D_OUT ; @@ -4199,10 +4034,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign write_requests$D_IN = write_requests + 64'd1 ; assign write_requests$EN = WILL_FIRE_RL_handleWrite ; - // register writes_faulty - assign writes_faulty$D_IN = 64'h0 ; - assign writes_faulty$EN = 1'b0 ; - // submodule byteAlignerReader_addr_ff assign byteAlignerReader_addr_ff$sD_IN = 192'h0 ; assign byteAlignerReader_addr_ff$sENQ = 1'b0 ; @@ -4259,17 +4090,9 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign fpgaDone$sD_IN = 1'd1 ; assign fpgaDone$sENQ = fpgaDone$sFULL_N && - fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672 ; + fpgaLastCycle_662_AND_m_fpga_rd_task_data_outp_ETC___d1664 ; assign fpgaDone$dDEQ = WILL_FIRE_RL_setInterrupt ; - // submodule fpga_get_delay - assign fpga_get_delay$sD_IN = { m_fpga_rd_putDelay, m_fpga_rd_totalPuts } ; - assign fpga_get_delay$sEN = fpga_get_delay$sRDY ; - - // submodule fpga_read_4kbarriers - assign fpga_read_4kbarriers$sD_IN = 64'd0 ; - assign fpga_read_4kbarriers$sEN = fpga_read_4kbarriers$sRDY ; - // submodule fpga_request_converter assign fpga_request_converter$sD_IN = writeConverter_dataSync$D_OUT ; assign fpga_request_converter$sENQ = @@ -4286,25 +4109,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_rd_outgoingBuffer$EMPTY_N ; assign fpga_response_converter$dDEQ = WILL_FIRE_RL_mkConnectionGetPut_1 ; - // submodule fpga_write_4kbarriers - assign fpga_write_4kbarriers$sD_IN = 64'd0 ; - assign fpga_write_4kbarriers$sEN = fpga_write_4kbarriers$sRDY ; - - // submodule last_read_pcie - assign last_read_pcie$sD_IN = 64'd0 ; - assign last_read_pcie$sEN = last_read_pcie$sRDY ; - - // submodule last_written_pcie - assign last_written_pcie$sD_IN = 64'd0 ; - assign last_written_pcie$sEN = last_written_pcie$sRDY ; - // submodule m_fpga_rd_master_rd_in assign m_fpga_rd_master_rd_in$D_IN = - { 1'd0, - m_fpga_rd_task_data_requests_reg[67:4], + { m_fpga_rd_task_data_requests_reg[67:4], (m_fpga_rd_task_data_requests_reg[125:68] == 58'd1 && m_fpga_rd_task_data_requests_reg[133:126] != 8'd0) ? - beatsThisRequest___1__h55895 : + beatsThisRequest___1__h57878 : 8'd255, 17'd102784, m_fpga_rd_task_data_requests_reg[3:0], @@ -4343,7 +4153,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_rd_reqGen_intermediateBuffer assign m_fpga_rd_reqGen_intermediateBuffer$D_IN = - { x__h53483[5:0], + { x__h55481[5:0], m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6[5:0], m_fpga_rd_reqGen_incomingBuffer$D_OUT } ; assign m_fpga_rd_reqGen_intermediateBuffer$ENQ = @@ -4357,7 +4167,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_rd_reqGen_intermediateBuffer2 assign m_fpga_rd_reqGen_intermediateBuffer2$D_IN = { m_fpga_rd_reqGen_intermediateBuffer$D_OUT[143:132], - x__h53664[57:0], + x__h55662[57:0], m_fpga_rd_reqGen_intermediateBuffer$D_OUT[131:0] } ; assign m_fpga_rd_reqGen_intermediateBuffer2$ENQ = m_fpga_rd_reqGen_intermediateBuffer$EMPTY_N && @@ -4369,8 +4179,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_rd_reqGen_outgoingBuffer assign m_fpga_rd_reqGen_outgoingBuffer$D_IN = { m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[139:132], - request_data_requests_total__h53801, - request_data_address__h53802, + request_data_requests_total__h55799, + request_data_address__h55800, m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[3:0], m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[201:132], m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[73:68], @@ -4382,12 +4192,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_fpga_rd_reqGen_outgoingBuffer$CLR = 1'b0 ; // submodule m_fpga_wr_beatsPerRequestFIFO - assign m_fpga_wr_beatsPerRequestFIFO$D_IN = _theResult____h41256 ; + assign m_fpga_wr_beatsPerRequestFIFO$D_IN = _theResult____h43254 ; assign m_fpga_wr_beatsPerRequestFIFO$ENQ = WILL_FIRE_RL_m_fpga_wr_placeRequest ; assign m_fpga_wr_beatsPerRequestFIFO$DEQ = WILL_FIRE_RL_m_fpga_wr_forwardData && - m_fpga_wr_beatsThisRequestCntr_13_EQ_m_fpga_wr_ETC___d915 ; + m_fpga_wr_beatsThisRequestCntr_21_EQ_m_fpga_wr_ETC___d923 ; assign m_fpga_wr_beatsPerRequestFIFO$CLR = 1'b0 ; // submodule m_fpga_wr_incomingBuffer @@ -4400,9 +4210,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_master_wr_in_addr assign m_fpga_wr_master_wr_in_addr$D_IN = - { 1'd0, - m_fpga_wr_task_data_requests_reg[67:4], - _theResult____h41256, + { m_fpga_wr_task_data_requests_reg[67:4], + _theResult____h43254, 17'd102784, m_fpga_wr_task_data_requests_reg[3:0], 1'd0 } ; @@ -4415,8 +4224,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_master_wr_in_data assign m_fpga_wr_master_wr_in_data$D_IN = { m_fpga_wr_incomingBuffer$D_OUT, - x_strb__h41878, - m_fpga_wr_beatsThisRequestCntr_13_EQ_m_fpga_wr_ETC___d915, + x_strb__h43876, + m_fpga_wr_beatsThisRequestCntr_21_EQ_m_fpga_wr_ETC___d923, 1'd0 } ; assign m_fpga_wr_master_wr_in_data$ENQ = WILL_FIRE_RL_m_fpga_wr_forwardData ; @@ -4444,7 +4253,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_reqGen_intermediateBuffer assign m_fpga_wr_reqGen_intermediateBuffer$D_IN = - { x__h38136[5:0], + { x__h40149[5:0], m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7[5:0], m_fpga_wr_reqGen_incomingBuffer$D_OUT } ; assign m_fpga_wr_reqGen_intermediateBuffer$ENQ = @@ -4458,7 +4267,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_reqGen_intermediateBuffer2 assign m_fpga_wr_reqGen_intermediateBuffer2$D_IN = { m_fpga_wr_reqGen_intermediateBuffer$D_OUT[143:132], - x__h38317[57:0], + x__h40330[57:0], m_fpga_wr_reqGen_intermediateBuffer$D_OUT[131:0] } ; assign m_fpga_wr_reqGen_intermediateBuffer2$ENQ = m_fpga_wr_reqGen_intermediateBuffer$EMPTY_N && @@ -4470,8 +4279,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_reqGen_outgoingBuffer assign m_fpga_wr_reqGen_outgoingBuffer$D_IN = { m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[139:132], - request_data_requests_total__h38454, - request_data_address__h38455, + request_data_requests_total__h40467, + request_data_address__h40468, m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[3:0], m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[201:132], m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[73:68], @@ -4484,11 +4293,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_master_rd_in assign m_pcie_rd_master_rd_in$D_IN = - { 1'd0, - m_pcie_rd_task_data_requests_reg[67:4], + { m_pcie_rd_task_data_requests_reg[67:4], (m_pcie_rd_task_data_requests_reg[126:68] == 59'd1 && m_pcie_rd_task_data_requests_reg[134:127] != 8'd0) ? - beatsThisRequest___1__h36662 : + beatsThisRequest___1__h38675 : 8'd63, 17'd86400, m_pcie_rd_task_data_requests_reg[3:0], @@ -4525,7 +4333,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_reqGen_intermediateBuffer assign m_pcie_rd_reqGen_intermediateBuffer$D_IN = - { x__h34247[4:0], + { x__h36275[4:0], m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8[4:0], m_pcie_rd_reqGen_incomingBuffer$D_OUT } ; assign m_pcie_rd_reqGen_intermediateBuffer$ENQ = @@ -4539,7 +4347,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_reqGen_intermediateBuffer2 assign m_pcie_rd_reqGen_intermediateBuffer2$D_IN = { m_pcie_rd_reqGen_intermediateBuffer$D_OUT[141:132], - x__h34428[58:0], + x__h36456[58:0], m_pcie_rd_reqGen_intermediateBuffer$D_OUT[131:0] } ; assign m_pcie_rd_reqGen_intermediateBuffer2$ENQ = m_pcie_rd_reqGen_intermediateBuffer$EMPTY_N && @@ -4550,9 +4358,9 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_reqGen_outgoingBuffer assign m_pcie_rd_reqGen_outgoingBuffer$D_IN = - { requests_last__h34528, - request_data_requests_total__h34565, - request_data_address__h34566, + { requests_last__h36556, + request_data_requests_total__h36593, + request_data_address__h36594, m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[3:0], m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[200:132], m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[72:68], @@ -4564,12 +4372,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_pcie_rd_reqGen_outgoingBuffer$CLR = 1'b0 ; // submodule m_pcie_wr_beatsPerRequestFIFO - assign m_pcie_wr_beatsPerRequestFIFO$D_IN = _theResult____h27428 ; + assign m_pcie_wr_beatsPerRequestFIFO$D_IN = _theResult____h29456 ; assign m_pcie_wr_beatsPerRequestFIFO$ENQ = WILL_FIRE_RL_m_pcie_wr_placeRequest ; assign m_pcie_wr_beatsPerRequestFIFO$DEQ = WILL_FIRE_RL_m_pcie_wr_forwardData && - m_pcie_wr_beatsThisRequestCntr_28_EQ_m_pcie_wr_ETC___d430 ; + m_pcie_wr_beatsThisRequestCntr_40_EQ_m_pcie_wr_ETC___d442 ; assign m_pcie_wr_beatsPerRequestFIFO$CLR = 1'b0 ; // submodule m_pcie_wr_incomingBuffer @@ -4586,9 +4394,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_wr_master_wr_in_addr assign m_pcie_wr_master_wr_in_addr$D_IN = - { 1'd0, - m_pcie_wr_task_data_requests_reg[67:4], - _theResult____h27428, + { m_pcie_wr_task_data_requests_reg[67:4], + _theResult____h29456, 17'd86400, m_pcie_wr_task_data_requests_reg[3:0], 1'd0 } ; @@ -4601,8 +4408,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_wr_master_wr_in_data assign m_pcie_wr_master_wr_in_data$D_IN = { m_pcie_wr_incomingBuffer$D_OUT, - x_strb__h28050, - m_pcie_wr_beatsThisRequestCntr_28_EQ_m_pcie_wr_ETC___d430, + x_strb__h30078, + m_pcie_wr_beatsThisRequestCntr_40_EQ_m_pcie_wr_ETC___d442, 1'd0 } ; assign m_pcie_wr_master_wr_in_data$ENQ = WILL_FIRE_RL_m_pcie_wr_forwardData ; @@ -4630,7 +4437,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_wr_reqGen_intermediateBuffer assign m_pcie_wr_reqGen_intermediateBuffer$D_IN = - { x__h24293[4:0], + { x__h26336[4:0], m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9[4:0], m_pcie_wr_reqGen_incomingBuffer$D_OUT } ; assign m_pcie_wr_reqGen_intermediateBuffer$ENQ = @@ -4644,7 +4451,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_wr_reqGen_intermediateBuffer2 assign m_pcie_wr_reqGen_intermediateBuffer2$D_IN = { m_pcie_wr_reqGen_intermediateBuffer$D_OUT[141:132], - x__h24474[58:0], + x__h26517[58:0], m_pcie_wr_reqGen_intermediateBuffer$D_OUT[131:0] } ; assign m_pcie_wr_reqGen_intermediateBuffer2$ENQ = m_pcie_wr_reqGen_intermediateBuffer$EMPTY_N && @@ -4655,9 +4462,9 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_wr_reqGen_outgoingBuffer assign m_pcie_wr_reqGen_outgoingBuffer$D_IN = - { requests_last__h24574, - request_data_requests_total__h24611, - request_data_address__h24612, + { requests_last__h26617, + request_data_requests_total__h26654, + request_data_address__h26655, m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[3:0], m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[200:132], m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[72:68], @@ -4702,23 +4509,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign pcieDone$sD_IN = 1'd1 ; assign pcieDone$sENQ = pcieDone$sFULL_N && - pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665 ; + pcieLastCycle_655_AND_m_pcie_rd_task_data_outp_ETC___d1657 ; assign pcieDone$dDEQ = WILL_FIRE_RL_setInterrupt ; - // submodule pcie_put_delay - assign pcie_put_delay$sD_IN = { m_pcie_wr_putDelay, m_pcie_wr_totalPuts } ; - assign pcie_put_delay$sEN = pcie_put_delay$sRDY ; - - // submodule pcie_read_4kbarriers - assign pcie_read_4kbarriers$sD_IN = 64'd0 ; - assign pcie_read_4kbarriers$sEN = pcie_read_4kbarriers$sRDY ; - - // submodule pcie_write_4kbarriers - assign pcie_write_4kbarriers$sD_IN = 64'd0 ; - assign pcie_write_4kbarriers$sEN = pcie_write_4kbarriers$sRDY ; - // submodule readConvBTT_ff - assign readConvBTT_ff$sD_IN = { btt__h100105, readIn_rv[69] } ; + assign readConvBTT_ff$sD_IN = { btt__h102029, readIn_rv[69] } ; assign readConvBTT_ff$sENQ = WILL_FIRE_RL_handleRead ; assign readConvBTT_ff$dDEQ = readConvBTT_ff$dEMPTY_N ; @@ -4728,15 +4523,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, s_config_readSlave_in$FULL_N && S_AXI_arvalid ; assign s_config_readSlave_in$DEQ = WILL_FIRE_RL_s_config_axiReadFallback || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_9 || WILL_FIRE_RL_s_config_axiReadSpecial_8 || WILL_FIRE_RL_s_config_axiReadSpecial_7 || WILL_FIRE_RL_s_config_axiReadSpecial_6 || @@ -4767,24 +4553,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, MUX_s_config_readSlave_out$enq_1__VAL_8 or WILL_FIRE_RL_s_config_axiReadSpecial_8 or MUX_s_config_readSlave_out$enq_1__VAL_9 or - WILL_FIRE_RL_s_config_axiReadSpecial_9 or - MUX_s_config_readSlave_out$enq_1__VAL_10 or - WILL_FIRE_RL_s_config_axiReadSpecial_10 or - MUX_s_config_readSlave_out$enq_1__VAL_11 or - WILL_FIRE_RL_s_config_axiReadSpecial_11 or - MUX_s_config_readSlave_out$enq_1__VAL_12 or - WILL_FIRE_RL_s_config_axiReadSpecial_12 or - MUX_s_config_readSlave_out$enq_1__VAL_13 or - WILL_FIRE_RL_s_config_axiReadSpecial_13 or - MUX_s_config_readSlave_out$enq_1__VAL_14 or - WILL_FIRE_RL_s_config_axiReadSpecial_14 or - MUX_s_config_readSlave_out$enq_1__VAL_15 or - WILL_FIRE_RL_s_config_axiReadSpecial_15 or - MUX_s_config_readSlave_out$enq_1__VAL_16 or - WILL_FIRE_RL_s_config_axiReadSpecial_16 or - MUX_s_config_readSlave_out$enq_1__VAL_17 or - WILL_FIRE_RL_s_config_axiReadSpecial_17 or - MUX_s_config_readSlave_out$enq_1__VAL_18 or WILL_FIRE_RL_s_config_axiReadFallback) begin case (1'b1) // synopsys parallel_case @@ -4815,33 +4583,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_axiReadSpecial_8: s_config_readSlave_out$D_IN = MUX_s_config_readSlave_out$enq_1__VAL_9; - WILL_FIRE_RL_s_config_axiReadSpecial_9: - s_config_readSlave_out$D_IN = - MUX_s_config_readSlave_out$enq_1__VAL_10; - WILL_FIRE_RL_s_config_axiReadSpecial_10: - s_config_readSlave_out$D_IN = - MUX_s_config_readSlave_out$enq_1__VAL_11; - WILL_FIRE_RL_s_config_axiReadSpecial_11: - s_config_readSlave_out$D_IN = - MUX_s_config_readSlave_out$enq_1__VAL_12; - WILL_FIRE_RL_s_config_axiReadSpecial_12: - s_config_readSlave_out$D_IN = - MUX_s_config_readSlave_out$enq_1__VAL_13; - WILL_FIRE_RL_s_config_axiReadSpecial_13: - s_config_readSlave_out$D_IN = - MUX_s_config_readSlave_out$enq_1__VAL_14; - WILL_FIRE_RL_s_config_axiReadSpecial_14: - s_config_readSlave_out$D_IN = - MUX_s_config_readSlave_out$enq_1__VAL_15; - WILL_FIRE_RL_s_config_axiReadSpecial_15: - s_config_readSlave_out$D_IN = - MUX_s_config_readSlave_out$enq_1__VAL_16; - WILL_FIRE_RL_s_config_axiReadSpecial_16: - s_config_readSlave_out$D_IN = - MUX_s_config_readSlave_out$enq_1__VAL_17; - WILL_FIRE_RL_s_config_axiReadSpecial_17: - s_config_readSlave_out$D_IN = - MUX_s_config_readSlave_out$enq_1__VAL_18; WILL_FIRE_RL_s_config_axiReadFallback: s_config_readSlave_out$D_IN = 66'd0; default: s_config_readSlave_out$D_IN = @@ -4858,15 +4599,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_axiReadSpecial_6 || WILL_FIRE_RL_s_config_axiReadSpecial_7 || WILL_FIRE_RL_s_config_axiReadSpecial_8 || - WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || WILL_FIRE_RL_s_config_axiReadFallback ; assign s_config_readSlave_out$DEQ = s_config_readSlave_out$EMPTY_N && S_AXI_rready ; @@ -4882,6 +4614,9 @@ module mkBlueDMA(CLK_m32_axi_aclk, s_config_writeSlave_dataIn_rv$port1__read[72] && s_config_writeSlave_in$FULL_N ; assign s_config_writeSlave_in$DEQ = + WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 || WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 || WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 || WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 || @@ -4892,6 +4627,9 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule s_config_writeSlave_out assign s_config_writeSlave_out$D_IN = 2'd0 ; assign s_config_writeSlave_out$ENQ = + WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 || WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 || WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 || WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 || @@ -4902,7 +4640,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign s_config_writeSlave_out$CLR = 1'b0 ; // submodule writeConvBTT_ff - assign writeConvBTT_ff$sD_IN = { btt__h143147, writeIn_rv[69] } ; + assign writeConvBTT_ff$sD_IN = { btt__h145135, writeIn_rv[69] } ; assign writeConvBTT_ff$sENQ = WILL_FIRE_RL_handleWrite ; assign writeConvBTT_ff$dDEQ = writeConvBTT_ff$dEMPTY_N ; @@ -4929,597 +4667,599 @@ module mkBlueDMA(CLK_m32_axi_aclk, readConverter_byteCntr <= 64'd32) ? 2'd0 : { 1'd0, readConverter_wordInCntr } + 2'd1 ; - assign IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 = + assign IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 = (m_fpga_wr_task_data_output_reg[0] && m_fpga_wr_task_data_output_reg[76:71] != 6'd0) ? - endByte___1__h44787 : + endByte___1__h46785 : ((m_fpga_wr_task_data_output_reg[64:7] == 58'd1) ? ((m_fpga_wr_task_data_output_reg[70:65] == 6'd0) ? 7'd64 : - endByte___1__h44813) : + endByte___1__h46811) : 7'd64) ; - assign IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 = + assign IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 = (m_pcie_wr_task_data_output_reg[0] && m_pcie_wr_task_data_output_reg[74:70] != 5'd0) ? - endByte___1__h29551 : + endByte___1__h31579 : ((m_pcie_wr_task_data_output_reg[64:6] == 59'd1) ? ((m_pcie_wr_task_data_output_reg[69:65] == 5'd0) ? 6'd32 : - endByte___1__h29577) : + endByte___1__h31605) : 6'd32) ; - assign _theResult____h24288 = + assign _theResult____h26331 = (m_pcie_wr_reqGen_incomingBuffer$D_OUT[72:68] == 5'd0) ? - bytes_first__h24287 : - bytes_first___1__h24323 ; - assign _theResult____h24472 = + bytes_first__h26330 : + bytes_first___1__h26366 ; + assign _theResult____h26515 = (m_pcie_wr_reqGen_intermediateBuffer$D_OUT[141:137] == 5'd0) ? - transfers_total__h24471 : - transfers_total___1__h24480 ; - assign _theResult____h27428 = + transfers_total__h26514 : + transfers_total___1__h26523 ; + assign _theResult____h29456 = (m_pcie_wr_task_data_requests_reg[126:68] == 59'd1 && m_pcie_wr_task_data_requests_reg[134:127] != 8'd0) ? - beatsThisRequest___1__h27476 : + beatsThisRequest___1__h29504 : 8'd63 ; - assign _theResult____h34242 = + assign _theResult____h36270 = (m_pcie_rd_reqGen_incomingBuffer$D_OUT[72:68] == 5'd0) ? - bytes_first__h34241 : - bytes_first___1__h34277 ; - assign _theResult____h34426 = + bytes_first__h36269 : + bytes_first___1__h36305 ; + assign _theResult____h36454 = (m_pcie_rd_reqGen_intermediateBuffer$D_OUT[141:137] == 5'd0) ? - transfers_total__h34425 : - transfers_total___1__h34434 ; - assign _theResult____h38131 = + transfers_total__h36453 : + transfers_total___1__h36462 ; + assign _theResult____h40144 = (m_fpga_wr_reqGen_incomingBuffer$D_OUT[73:68] == 6'd0) ? - bytes_first__h38130 : - bytes_first___1__h38166 ; - assign _theResult____h38315 = + bytes_first__h40143 : + bytes_first___1__h40179 ; + assign _theResult____h40328 = (m_fpga_wr_reqGen_intermediateBuffer$D_OUT[143:138] == 6'd0) ? - transfers_total__h38314 : - transfers_total___1__h38323 ; - assign _theResult____h41256 = + transfers_total__h40327 : + transfers_total___1__h40336 ; + assign _theResult____h43254 = (m_fpga_wr_task_data_requests_reg[125:68] == 58'd1 && m_fpga_wr_task_data_requests_reg[133:126] != 8'd0) ? - beatsThisRequest___1__h41304 : + beatsThisRequest___1__h43302 : 8'd255 ; - assign _theResult____h53478 = + assign _theResult____h55476 = (m_fpga_rd_reqGen_incomingBuffer$D_OUT[73:68] == 6'd0) ? - bytes_first__h53477 : - bytes_first___1__h53513 ; - assign _theResult____h53662 = + bytes_first__h55475 : + bytes_first___1__h55511 ; + assign _theResult____h55660 = (m_fpga_rd_reqGen_intermediateBuffer$D_OUT[143:138] == 6'd0) ? - transfers_total__h53661 : - transfers_total___1__h53670 ; - assign b__h113489 = + transfers_total__h55659 : + transfers_total___1__h55668 ; + assign b__h115415 = byteAlignerWriter_bytes_left_in_buffer$EN_port0__write ? byteAlignerWriter_bytes_left_in_buffer$port0__write_1 : byteAlignerWriter_bytes_left_in_buffer ; - assign b__h70410 = + assign b__h72232 = byteAlignerReader_bytes_left_in_buffer$EN_port0__write ? byteAlignerReader_bytes_left_in_buffer$port0__write_1 : byteAlignerReader_bytes_left_in_buffer ; - assign beatsThisRequestCntrT__h27936 = + assign beatsThisRequestCntrT__h29964 = m_pcie_wr_beatsThisRequestCntr + 8'd1 ; - assign beatsThisRequestCntrT__h41764 = + assign beatsThisRequestCntrT__h43762 = m_fpga_wr_beatsThisRequestCntr + 8'd1 ; - assign beatsThisRequest___1__h27476 = + assign beatsThisRequest___1__h29504 = m_pcie_wr_task_data_requests_reg[134:127] - 8'd1 ; - assign beatsThisRequest___1__h36662 = + assign beatsThisRequest___1__h38675 = m_pcie_rd_task_data_requests_reg[134:127] - 8'd1 ; - assign beatsThisRequest___1__h41304 = + assign beatsThisRequest___1__h43302 = m_fpga_wr_task_data_requests_reg[133:126] - 8'd1 ; - assign beatsThisRequest___1__h55895 = + assign beatsThisRequest___1__h57878 = m_fpga_rd_task_data_requests_reg[133:126] - 8'd1 ; - assign btt__h100105 = readIn_rv[63:0] + y__h100142 ; - assign btt__h143147 = writeIn_rv[63:0] + y__h143175 ; - assign byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 = + assign btt__h102029 = readIn_rv[63:0] + y__h102066 ; + assign btt__h145135 = writeIn_rv[63:0] + y__h145163 ; + assign byteAlignerReader_bytes_in_430_ULT_byteAligner_ETC___d1432 = byteAlignerReader_bytes_in < byteAlignerReader_bytes_total ; - assign byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 = + assign byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1447 = byteAlignerReader_bytes_left_in_buffer < byteAlignerReader_bytes_out_needed ; - assign byteAlignerWriter_bytes_in_559_ULT_byteAligner_ETC___d1561 = + assign byteAlignerWriter_bytes_in_552_ULT_byteAligner_ETC___d1554 = byteAlignerWriter_bytes_in < byteAlignerWriter_bytes_total ; - assign byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1576 = + assign byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1569 = byteAlignerWriter_bytes_left_in_buffer < byteAlignerWriter_bytes_out_needed ; - assign bytes_first___1__h24323 = 64'd32 - bytes_first__h24287 ; - assign bytes_first___1__h34277 = 64'd32 - bytes_first__h34241 ; - assign bytes_first___1__h38166 = 64'd64 - bytes_first__h38130 ; - assign bytes_first___1__h53513 = 64'd64 - bytes_first__h53477 ; - assign bytes_first__h24287 = + assign bytes_first___1__h26366 = 64'd32 - bytes_first__h26330 ; + assign bytes_first___1__h36305 = 64'd32 - bytes_first__h36269 ; + assign bytes_first___1__h40179 = 64'd64 - bytes_first__h40143 ; + assign bytes_first___1__h55511 = 64'd64 - bytes_first__h55475 ; + assign bytes_first__h26330 = { 59'd0, m_pcie_wr_reqGen_incomingBuffer$D_OUT[72:68] } ; - assign bytes_first__h34241 = + assign bytes_first__h36269 = { 59'd0, m_pcie_rd_reqGen_incomingBuffer$D_OUT[72:68] } ; - assign bytes_first__h38130 = + assign bytes_first__h40143 = { 58'd0, m_fpga_wr_reqGen_incomingBuffer$D_OUT[73:68] } ; - assign bytes_first__h53477 = + assign bytes_first__h55475 = { 58'd0, m_fpga_rd_reqGen_incomingBuffer$D_OUT[73:68] } ; - assign endByte___1__h29551 = - startByte___1__h29550 + + assign endByte___1__h31579 = + startByte___1__h31578 + { 1'd0, m_pcie_wr_task_data_output_reg[74:70] } ; - assign endByte___1__h29577 = + assign endByte___1__h31605 = { 1'd0, m_pcie_wr_task_data_output_reg[69:65] } ; - assign endByte___1__h44787 = - startByte___1__h44786 + + assign endByte___1__h46785 = + startByte___1__h46784 + { 1'd0, m_fpga_wr_task_data_output_reg[76:71] } ; - assign endByte___1__h44813 = + assign endByte___1__h46811 = { 1'd0, m_fpga_wr_task_data_output_reg[70:65] } ; - assign fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672 = + assign fpgaLastCycle_662_AND_m_fpga_rd_task_data_outp_ETC___d1664 = fpgaLastCycle && m_fpga_rd_task_data_output_reg[64:7] == 58'd0 && m_fpga_rd_task_data_requests_reg[125:68] == 58'd0 && m_fpga_wr_task_data_output_reg[64:7] == 58'd0 && m_fpga_wr_task_data_requests_reg[125:68] == 58'd0 ; assign m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6 = - m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h53557 ; - assign m_fpga_wr_beatsThisRequestCntr_13_EQ_m_fpga_wr_ETC___d915 = + m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h55555 ; + assign m_fpga_wr_beatsThisRequestCntr_21_EQ_m_fpga_wr_ETC___d923 = m_fpga_wr_beatsThisRequestCntr == m_fpga_wr_beatsPerRequestFIFO$D_OUT ; assign m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7 = - m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h38210 ; + m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h40223 ; assign m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8 = - m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h34321 ; - assign m_pcie_wr_beatsThisRequestCntr_28_EQ_m_pcie_wr_ETC___d430 = + m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h36349 ; + assign m_pcie_wr_beatsThisRequestCntr_40_EQ_m_pcie_wr_ETC___d442 = m_pcie_wr_beatsThisRequestCntr == m_pcie_wr_beatsPerRequestFIFO$D_OUT ; assign m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9 = - m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h24367 ; - assign pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665 = + m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h26410 ; + assign pc_reqCntr_491_EQ_cycles_between_set_6_BITS_11_ETC___d1673 = + pc_reqCntr == cycles_between_set[11:0] ; + assign pcieLastCycle_655_AND_m_pcie_rd_task_data_outp_ETC___d1657 = pcieLastCycle && m_pcie_rd_task_data_output_reg[64:6] == 59'd0 && m_pcie_rd_task_data_requests_reg[126:68] == 59'd0 && m_pcie_wr_task_data_output_reg[64:6] == 59'd0 && m_pcie_wr_task_data_requests_reg[126:68] == 59'd0 ; - assign request_data_address__h24612 = + assign request_data_address__h26655 = { m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[131:73], 5'd0 } ; - assign request_data_address__h34566 = + assign request_data_address__h36594 = { m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[131:73], 5'd0 } ; - assign request_data_address__h38455 = + assign request_data_address__h40468 = { m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[131:74], 6'd0 } ; - assign request_data_address__h53802 = + assign request_data_address__h55800 = { m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[131:74], 6'd0 } ; - assign request_data_requests_total__h24611 = + assign request_data_requests_total__h26654 = (m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[137:132] == 6'd0) ? - requests_total__h24575 : - requests_total___1__h24637 ; - assign request_data_requests_total__h34565 = + requests_total__h26618 : + requests_total___1__h26680 ; + assign request_data_requests_total__h36593 = (m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[137:132] == 6'd0) ? - requests_total__h34529 : - requests_total___1__h34591 ; - assign request_data_requests_total__h38454 = + requests_total__h36557 : + requests_total___1__h36619 ; + assign request_data_requests_total__h40467 = (m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[139:132] == 8'd0) ? - requests_total__h38418 : - requests_total___1__h38480 ; - assign request_data_requests_total__h53801 = + requests_total__h40431 : + requests_total___1__h40493 ; + assign request_data_requests_total__h55799 = (m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[139:132] == 8'd0) ? - requests_total__h53765 : - requests_total___1__h53827 ; - assign requests_last__h24574 = + requests_total__h55763 : + requests_total___1__h55825 ; + assign requests_last__h26617 = { 2'd0, m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[137:132] } ; - assign requests_last__h34528 = + assign requests_last__h36556 = { 2'd0, m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[137:132] } ; - assign requests_total___1__h24637 = requests_total__h24575 + 59'd1 ; - assign requests_total___1__h34591 = requests_total__h34529 + 59'd1 ; - assign requests_total___1__h38480 = requests_total__h38418 + 58'd1 ; - assign requests_total___1__h53827 = requests_total__h53765 + 58'd1 ; - assign requests_total__h24575 = + assign requests_total___1__h26680 = requests_total__h26618 + 59'd1 ; + assign requests_total___1__h36619 = requests_total__h36557 + 59'd1 ; + assign requests_total___1__h40493 = requests_total__h40431 + 58'd1 ; + assign requests_total___1__h55825 = requests_total__h55763 + 58'd1 ; + assign requests_total__h26618 = m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[190:132] >> 6 ; - assign requests_total__h34529 = + assign requests_total__h36557 = m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[190:132] >> 6 ; - assign requests_total__h38418 = + assign requests_total__h40431 = m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[189:132] >> 8 ; - assign requests_total__h53765 = + assign requests_total__h55763 = m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[189:132] >> 8 ; - assign startByte___1__h29550 = + assign startByte___1__h31578 = { 1'd0, m_pcie_wr_task_data_output_reg[5:1] } ; - assign startByte___1__h44786 = + assign startByte___1__h46784 = { 1'd0, m_fpga_wr_task_data_output_reg[6:1] } ; - assign transfers_total___1__h24480 = transfers_total__h24471 + 64'd1 ; - assign transfers_total___1__h34434 = transfers_total__h34425 + 64'd1 ; - assign transfers_total___1__h38323 = transfers_total__h38314 + 64'd1 ; - assign transfers_total___1__h53670 = transfers_total__h53661 + 64'd1 ; - assign transfers_total__h24471 = (x__h24500 - y__h24501) >> 5 ; - assign transfers_total__h24477 = _theResult____h24472 + 64'd1 ; - assign transfers_total__h34425 = (x__h34454 - y__h34455) >> 5 ; - assign transfers_total__h34431 = _theResult____h34426 + 64'd1 ; - assign transfers_total__h38314 = (x__h38343 - y__h38344) >> 6 ; - assign transfers_total__h38320 = _theResult____h38315 + 64'd1 ; - assign transfers_total__h53661 = (x__h53690 - y__h53691) >> 6 ; - assign transfers_total__h53667 = _theResult____h53662 + 64'd1 ; - assign x__h24293 = + assign transfers_total___1__h26523 = transfers_total__h26514 + 64'd1 ; + assign transfers_total___1__h36462 = transfers_total__h36453 + 64'd1 ; + assign transfers_total___1__h40336 = transfers_total__h40327 + 64'd1 ; + assign transfers_total___1__h55668 = transfers_total__h55659 + 64'd1 ; + assign transfers_total__h26514 = (x__h26543 - y__h26544) >> 5 ; + assign transfers_total__h26520 = _theResult____h26515 + 64'd1 ; + assign transfers_total__h36453 = (x__h36482 - y__h36483) >> 5 ; + assign transfers_total__h36459 = _theResult____h36454 + 64'd1 ; + assign transfers_total__h40327 = (x__h40356 - y__h40357) >> 6 ; + assign transfers_total__h40333 = _theResult____h40328 + 64'd1 ; + assign transfers_total__h55659 = (x__h55688 - y__h55689) >> 6 ; + assign transfers_total__h55665 = _theResult____h55660 + 64'd1 ; + assign x__h26336 = (m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] < - _theResult____h24288 || - _theResult____h24288 == 64'd0 && + _theResult____h26331 || + _theResult____h26331 == 64'd0 && m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] < 64'd32) ? m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] : - _theResult____h24288 ; - assign x__h24474 = + _theResult____h26331 ; + assign x__h26517 = (m_pcie_wr_reqGen_intermediateBuffer$D_OUT[136:132] == 5'd0) ? - _theResult____h24472 : - transfers_total__h24477 ; - assign x__h24500 = - m_pcie_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h24503 ; - assign x__h29537 = + _theResult____h26515 : + transfers_total__h26520 ; + assign x__h26543 = + m_pcie_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h26546 ; + assign x__h31565 = (m_pcie_wr_task_data_output_reg[0] && m_pcie_wr_task_data_output_reg[74:70] != 5'd0) ? - startByte___1__h29550 : + startByte___1__h31578 : 6'd0 ; - assign x__h34247 = + assign x__h36275 = (m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] < - _theResult____h34242 || - _theResult____h34242 == 64'd0 && + _theResult____h36270 || + _theResult____h36270 == 64'd0 && m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] < 64'd32) ? m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] : - _theResult____h34242 ; - assign x__h34428 = + _theResult____h36270 ; + assign x__h36456 = (m_pcie_rd_reqGen_intermediateBuffer$D_OUT[136:132] == 5'd0) ? - _theResult____h34426 : - transfers_total__h34431 ; - assign x__h34454 = - m_pcie_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h34457 ; - assign x__h38136 = + _theResult____h36454 : + transfers_total__h36459 ; + assign x__h36482 = + m_pcie_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h36485 ; + assign x__h40149 = (m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] < - _theResult____h38131 || - _theResult____h38131 == 64'd0 && + _theResult____h40144 || + _theResult____h40144 == 64'd0 && m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] < 64'd64) ? m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] : - _theResult____h38131 ; - assign x__h38317 = + _theResult____h40144 ; + assign x__h40330 = (m_fpga_wr_reqGen_intermediateBuffer$D_OUT[137:132] == 6'd0) ? - _theResult____h38315 : - transfers_total__h38320 ; - assign x__h38343 = - m_fpga_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h38346 ; - assign x__h44773 = + _theResult____h40328 : + transfers_total__h40333 ; + assign x__h40356 = + m_fpga_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h40359 ; + assign x__h46771 = (m_fpga_wr_task_data_output_reg[0] && m_fpga_wr_task_data_output_reg[76:71] != 6'd0) ? - startByte___1__h44786 : + startByte___1__h46784 : 7'd0 ; - assign x__h53483 = + assign x__h55481 = (m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] < - _theResult____h53478 || - _theResult____h53478 == 64'd0 && + _theResult____h55476 || + _theResult____h55476 == 64'd0 && m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] < 64'd64) ? m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] : - _theResult____h53478 ; - assign x__h53664 = + _theResult____h55476 ; + assign x__h55662 = (m_fpga_rd_reqGen_intermediateBuffer$D_OUT[137:132] == 6'd0) ? - _theResult____h53662 : - transfers_total__h53667 ; - assign x__h53690 = - m_fpga_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h53693 ; - assign x_address__h27534 = + _theResult____h55660 : + transfers_total__h55665 ; + assign x__h55688 = + m_fpga_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h55691 ; + assign x_address__h29562 = m_pcie_wr_task_data_requests_reg[67:4] + 64'd2048 ; - assign x_address__h36691 = + assign x_address__h38704 = m_pcie_rd_task_data_requests_reg[67:4] + 64'd2048 ; - assign x_address__h41362 = + assign x_address__h43360 = m_fpga_wr_task_data_requests_reg[67:4] + 64'd16384 ; - assign x_address__h55924 = + assign x_address__h57907 = m_fpga_rd_task_data_requests_reg[67:4] + 64'd16384 ; - assign x_requests_total__h27533 = + assign x_requests_total__h29561 = m_pcie_wr_task_data_requests_reg[126:68] - 59'd1 ; - assign x_requests_total__h36690 = + assign x_requests_total__h38703 = m_pcie_rd_task_data_requests_reg[126:68] - 59'd1 ; - assign x_requests_total__h41361 = + assign x_requests_total__h43359 = m_fpga_wr_task_data_requests_reg[125:68] - 58'd1 ; - assign x_requests_total__h55923 = + assign x_requests_total__h57906 = m_fpga_rd_task_data_requests_reg[125:68] - 58'd1 ; - assign x_strb__h28050 = - { x__h29537 <= 6'd31 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + assign x_strb__h30078 = + { x__h31565 <= 6'd31 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd31, - x__h29537 <= 6'd30 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd30 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd30, - x__h29537 <= 6'd29 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd29 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd29, - x__h29537 <= 6'd28 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd28 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd28, - x__h29537 <= 6'd27 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd27 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd27, - x__h29537 <= 6'd26 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd26 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd26, - x__h29537 <= 6'd25 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd25 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd25, - x__h29537 <= 6'd24 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd24 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd24, - x__h29537 <= 6'd23 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd23 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd23, - x__h29537 <= 6'd22 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd22 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd22, - x__h29537 <= 6'd21 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd21 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd21, - x__h29537 <= 6'd20 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd20 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd20, - x__h29537 <= 6'd19 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd19 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd19, - x__h29537 <= 6'd18 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd18 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd18, - x__h29537 <= 6'd17 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd17 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd17, - x__h29537 <= 6'd16 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd16 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd16, - x__h29537 <= 6'd15 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd15 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd15, - x__h29537 <= 6'd14 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd14 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd14, - x__h29537 <= 6'd13 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd13 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd13, - x__h29537 <= 6'd12 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd12 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd12, - x__h29537 <= 6'd11 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd11 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd11, - x__h29537 <= 6'd10 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd10 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd10, - x__h29537 <= 6'd9 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd9 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd9, - x__h29537 <= 6'd8 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd8 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd8, - x__h29537 <= 6'd7 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd7 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd7, - x__h29537 <= 6'd6 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd6 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd6, - x__h29537 <= 6'd5 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd5 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd5, - x__h29537 <= 6'd4 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd4 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd4, - x__h29537 <= 6'd3 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd3 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd3, - x__h29537 <= 6'd2 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd2 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd2, - x__h29537 <= 6'd1 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 > + x__h31565 <= 6'd1 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > 6'd1, - x__h29537 == 6'd0 && - IF_m_pcie_wr_task_data_output_reg_23_BIT_0_34__ETC___d451 != + x__h31565 == 6'd0 && + IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 != 6'd0 } ; - assign x_strb__h41878 = - { x__h44773 <= 7'd63 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + assign x_strb__h43876 = + { x__h46771 <= 7'd63 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd63, - x__h44773 <= 7'd62 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd62 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd62, - x__h44773 <= 7'd61 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd61 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd61, - x__h44773 <= 7'd60 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd60 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd60, - x__h44773 <= 7'd59 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd59 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd59, - x__h44773 <= 7'd58 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd58 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd58, - x__h44773 <= 7'd57 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd57 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd57, - x__h44773 <= 7'd56 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd56 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd56, - x__h44773 <= 7'd55 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd55 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd55, - x__h44773 <= 7'd54 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd54 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd54, - x__h44773 <= 7'd53 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd53 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd53, - x__h44773 <= 7'd52 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd52 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd52, - x__h44773 <= 7'd51 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd51 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd51, - x__h44773 <= 7'd50 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd50 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd50, - x__h44773 <= 7'd49 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd49 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd49, - x__h44773 <= 7'd48 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd48 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd48, - x__h44773 <= 7'd47 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd47 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd47, - x__h44773 <= 7'd46 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd46 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd46, - x__h44773 <= 7'd45 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd45 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd45, - x__h44773 <= 7'd44 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd44 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd44, - x__h44773 <= 7'd43 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd43 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd43, - x__h44773 <= 7'd42 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd42 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd42, - x__h44773 <= 7'd41 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd41 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd41, - x__h44773 <= 7'd40 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd40 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd40, - x__h44773 <= 7'd39 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd39 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd39, - x__h44773 <= 7'd38 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd38 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd38, - x__h44773 <= 7'd37 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd37 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd37, - x__h44773 <= 7'd36 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd36 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd36, - x__h44773 <= 7'd35 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd35 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd35, - x__h44773 <= 7'd34 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd34 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd34, - x__h44773 <= 7'd33 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd33 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd33, - x__h44773 <= 7'd32 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd32 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd32, - x__h44773 <= 7'd31 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd31 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd31, - x__h44773 <= 7'd30 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd30 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd30, - x__h44773 <= 7'd29 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd29 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd29, - x__h44773 <= 7'd28 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd28 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd28, - x__h44773 <= 7'd27 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd27 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd27, - x__h44773 <= 7'd26 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd26 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd26, - x__h44773 <= 7'd25 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd25 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd25, - x__h44773 <= 7'd24 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd24 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd24, - x__h44773 <= 7'd23 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd23 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd23, - x__h44773 <= 7'd22 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd22 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd22, - x__h44773 <= 7'd21 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd21 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd21, - x__h44773 <= 7'd20 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd20 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd20, - x__h44773 <= 7'd19 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd19 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd19, - x__h44773 <= 7'd18 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd18 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd18, - x__h44773 <= 7'd17 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd17 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd17, - x__h44773 <= 7'd16 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd16 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd16, - x__h44773 <= 7'd15 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd15 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd15, - x__h44773 <= 7'd14 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd14 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd14, - x__h44773 <= 7'd13 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd13 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd13, - x__h44773 <= 7'd12 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd12 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd12, - x__h44773 <= 7'd11 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd11 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd11, - x__h44773 <= 7'd10 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd10 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd10, - x__h44773 <= 7'd9 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd9 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd9, - x__h44773 <= 7'd8 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd8 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd8, - x__h44773 <= 7'd7 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd7 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd7, - x__h44773 <= 7'd6 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd6 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd6, - x__h44773 <= 7'd5 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd5 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd5, - x__h44773 <= 7'd4 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd4 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd4, - x__h44773 <= 7'd3 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd3 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd3, - x__h44773 <= 7'd2 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd2 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd2, - x__h44773 <= 7'd1 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 > + x__h46771 <= 7'd1 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > 7'd1, - x__h44773 == 7'd0 && - IF_m_fpga_wr_task_data_output_reg_08_BIT_0_19__ETC___d936 != + x__h46771 == 7'd0 && + IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 != 7'd0 } ; - assign x_transfers_total__h33560 = + assign x_transfers_total__h35588 = m_pcie_wr_task_data_output_reg[64:6] - 59'd1 ; - assign x_transfers_total__h37140 = + assign x_transfers_total__h39153 = m_pcie_rd_task_data_output_reg[64:6] - 59'd1 ; - assign x_transfers_total__h52796 = + assign x_transfers_total__h54794 = m_fpga_wr_task_data_output_reg[64:7] - 58'd1 ; - assign x_transfers_total__h56373 = + assign x_transfers_total__h58356 = m_fpga_rd_task_data_output_reg[64:7] - 58'd1 ; - assign y__h100142 = { 59'd0, readIn_rv[68:64] } ; - assign y__h143175 = { 59'd0, writeIn_rv[68:64] } ; - assign y__h24367 = { 59'd0, x__h24293[4:0] } ; - assign y__h24501 = + assign y__h102066 = { 59'd0, readIn_rv[68:64] } ; + assign y__h145163 = { 59'd0, writeIn_rv[68:64] } ; + assign y__h26410 = { 59'd0, x__h26336[4:0] } ; + assign y__h26544 = { 59'd0, m_pcie_wr_reqGen_intermediateBuffer$D_OUT[136:132] } ; - assign y__h24503 = + assign y__h26546 = { 59'd0, m_pcie_wr_reqGen_intermediateBuffer$D_OUT[141:137] } ; - assign y__h34321 = { 59'd0, x__h34247[4:0] } ; - assign y__h34455 = + assign y__h36349 = { 59'd0, x__h36275[4:0] } ; + assign y__h36483 = { 59'd0, m_pcie_rd_reqGen_intermediateBuffer$D_OUT[136:132] } ; - assign y__h34457 = + assign y__h36485 = { 59'd0, m_pcie_rd_reqGen_intermediateBuffer$D_OUT[141:137] } ; - assign y__h38210 = { 58'd0, x__h38136[5:0] } ; - assign y__h38344 = + assign y__h40223 = { 58'd0, x__h40149[5:0] } ; + assign y__h40357 = { 58'd0, m_fpga_wr_reqGen_intermediateBuffer$D_OUT[137:132] } ; - assign y__h38346 = + assign y__h40359 = { 58'd0, m_fpga_wr_reqGen_intermediateBuffer$D_OUT[143:138] } ; - assign y__h53557 = { 58'd0, x__h53483[5:0] } ; - assign y__h53691 = + assign y__h55555 = { 58'd0, x__h55481[5:0] } ; + assign y__h55689 = { 58'd0, m_fpga_rd_reqGen_intermediateBuffer$D_OUT[137:132] } ; - assign y__h53693 = + assign y__h55691 = { 58'd0, m_fpga_rd_reqGen_intermediateBuffer$D_OUT[143:138] } ; always@(m_pcie_wr_master_wr_wawcache$wget) begin @@ -5564,15 +5304,20 @@ module mkBlueDMA(CLK_m32_axi_aclk, begin if (RST_N == `BSV_RESET_VALUE) begin - doneInterruptReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + clkCntr <= `BSV_ASSIGNMENT_DELAY 32'd0; + cycles_between <= `BSV_ASSIGNMENT_DELAY 64'd0; + cycles_between_set <= `BSV_ASSIGNMENT_DELAY 64'd0; + cycles_last_request <= `BSV_ASSIGNMENT_DELAY 64'd0; + doneInterruptReg <= `BSV_ASSIGNMENT_DELAY 1'd0; fpga_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; host_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; id <= `BSV_ASSIGNMENT_DELAY 64'h0020FF3F0E5A0023; + isWriteActive <= `BSV_ASSIGNMENT_DELAY 1'd0; opInProgress <= `BSV_ASSIGNMENT_DELAY 1'd0; + pc_reqCntr <= `BSV_ASSIGNMENT_DELAY 12'd0; readIn_rv <= `BSV_ASSIGNMENT_DELAY 193'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; read_requests <= `BSV_ASSIGNMENT_DELAY 64'd0; - reads_faulty <= `BSV_ASSIGNMENT_DELAY 64'd0; s_config_readBusy <= `BSV_ASSIGNMENT_DELAY 1'd0; s_config_writeSlave_addrIn_rv <= `BSV_ASSIGNMENT_DELAY 68'h2AAAAAAAAAAAAAAAA; @@ -5582,22 +5327,31 @@ module mkBlueDMA(CLK_m32_axi_aclk, writeIn_rv <= `BSV_ASSIGNMENT_DELAY 193'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; write_requests <= `BSV_ASSIGNMENT_DELAY 64'd0; - writes_faulty <= `BSV_ASSIGNMENT_DELAY 64'd0; end else begin - if (doneInterruptReg$EN) + if (clkCntr$EN) clkCntr <= `BSV_ASSIGNMENT_DELAY clkCntr$D_IN; + if (cycles_between$EN) + cycles_between <= `BSV_ASSIGNMENT_DELAY cycles_between$D_IN; + if (cycles_between_set$EN) + cycles_between_set <= `BSV_ASSIGNMENT_DELAY cycles_between_set$D_IN; + if (cycles_last_request$EN) + cycles_last_request <= `BSV_ASSIGNMENT_DELAY + cycles_last_request$D_IN; + if (doneInterruptReg$EN) doneInterruptReg <= `BSV_ASSIGNMENT_DELAY doneInterruptReg$D_IN; if (fpga_addr$EN) fpga_addr <= `BSV_ASSIGNMENT_DELAY fpga_addr$D_IN; if (host_addr$EN) host_addr <= `BSV_ASSIGNMENT_DELAY host_addr$D_IN; if (id$EN) id <= `BSV_ASSIGNMENT_DELAY id$D_IN; + if (isWriteActive$EN) + isWriteActive <= `BSV_ASSIGNMENT_DELAY isWriteActive$D_IN; if (opInProgress$EN) opInProgress <= `BSV_ASSIGNMENT_DELAY opInProgress$D_IN; + if (pc_reqCntr$EN) + pc_reqCntr <= `BSV_ASSIGNMENT_DELAY pc_reqCntr$D_IN; if (readIn_rv$EN) readIn_rv <= `BSV_ASSIGNMENT_DELAY readIn_rv$D_IN; if (read_requests$EN) read_requests <= `BSV_ASSIGNMENT_DELAY read_requests$D_IN; - if (reads_faulty$EN) - reads_faulty <= `BSV_ASSIGNMENT_DELAY reads_faulty$D_IN; if (s_config_readBusy$EN) s_config_readBusy <= `BSV_ASSIGNMENT_DELAY s_config_readBusy$D_IN; if (s_config_writeSlave_addrIn_rv$EN) @@ -5612,13 +5366,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, writeIn_rv <= `BSV_ASSIGNMENT_DELAY writeIn_rv$D_IN; if (write_requests$EN) write_requests <= `BSV_ASSIGNMENT_DELAY write_requests$D_IN; - if (writes_faulty$EN) - writes_faulty <= `BSV_ASSIGNMENT_DELAY writes_faulty$D_IN; end - if (fpga_addr_last_req$EN) - fpga_addr_last_req <= `BSV_ASSIGNMENT_DELAY fpga_addr_last_req$D_IN; - if (host_addr_last_req$EN) - host_addr_last_req <= `BSV_ASSIGNMENT_DELAY host_addr_last_req$D_IN; + if (pc_betweenStart$EN) + pc_betweenStart <= `BSV_ASSIGNMENT_DELAY pc_betweenStart$D_IN; + if (pc_start$EN) pc_start <= `BSV_ASSIGNMENT_DELAY pc_start$D_IN; end always@(posedge CLK_m32_axi_aclk) @@ -5830,13 +5581,16 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_bytes_out_needed = 6'h2A; byteAlignerWriter_bytes_total = 64'hAAAAAAAAAAAAAAAA; byteAlignerWriter_fetchedDatum = 1'h0; + clkCntr = 32'hAAAAAAAA; + cycles_between = 64'hAAAAAAAAAAAAAAAA; + cycles_between_set = 64'hAAAAAAAAAAAAAAAA; + cycles_last_request = 64'hAAAAAAAAAAAAAAAA; doneInterruptReg = 1'h0; fpgaLastCycle = 1'h0; fpga_addr = 64'hAAAAAAAAAAAAAAAA; - fpga_addr_last_req = 64'hAAAAAAAAAAAAAAAA; host_addr = 64'hAAAAAAAAAAAAAAAA; - host_addr_last_req = 64'hAAAAAAAAAAAAAAAA; id = 64'hAAAAAAAAAAAAAAAA; + isWriteActive = 1'h0; m_fpga_rd_clkCntr = 32'hAAAAAAAA; m_fpga_rd_lastPut = 32'hAAAAAAAA; m_fpga_rd_putDelay = 32'hAAAAAAAA; @@ -5868,6 +5622,9 @@ module mkBlueDMA(CLK_m32_axi_aclk, 135'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; m_pcie_wr_totalPuts = 32'hAAAAAAAA; opInProgress = 1'h0; + pc_betweenStart = 32'hAAAAAAAA; + pc_reqCntr = 12'hAAA; + pc_start = 32'hAAAAAAAA; pcieLastCycle = 1'h0; readConverter_buffer = 512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -5876,7 +5633,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, readConverter_wordInCntr = 1'h0; readIn_rv = 193'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; read_requests = 64'hAAAAAAAAAAAAAAAA; - reads_faulty = 64'hAAAAAAAAAAAAAAAA; s_config_readBusy = 1'h0; s_config_writeSlave_addrIn_rv = 68'hAAAAAAAAAAAAAAAAA; s_config_writeSlave_dataIn_rv = 73'h0AAAAAAAAAAAAAAAAAA; @@ -5887,7 +5643,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, writeConverter_wordInCntr = 2'h2; writeIn_rv = 193'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; write_requests = 64'hAAAAAAAAAAAAAAAA; - writes_faulty = 64'hAAAAAAAAAAAAAAAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -5900,241 +5655,13 @@ module mkBlueDMA(CLK_m32_axi_aclk, #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_handleRead) - $display("btt org %d, btt after %d", readIn_rv[63:0], btt__h100105); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_4 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4) && - (WILL_FIRE_RL_s_config_axiReadSpecial_5 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_5 || - WILL_FIRE_RL_s_config_axiReadSpecial_6 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 || - WILL_FIRE_RL_s_config_axiReadSpecial_7 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || - WILL_FIRE_RL_s_config_axiReadSpecial_8 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 || - WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4] and [RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8, RL_s_config_axiReadSpecial_9,\n RL_s_config_axiReadSpecialIsHandled_9, RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10, RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_5 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_5) && - (WILL_FIRE_RL_s_config_axiReadSpecial_6 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 || - WILL_FIRE_RL_s_config_axiReadSpecial_7 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || - WILL_FIRE_RL_s_config_axiReadSpecial_8 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 || - WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5] and [RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8, RL_s_config_axiReadSpecial_9,\n RL_s_config_axiReadSpecialIsHandled_9, RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10, RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_6 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6) && - (WILL_FIRE_RL_s_config_axiReadSpecial_7 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || - WILL_FIRE_RL_s_config_axiReadSpecial_8 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 || - WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6] and [RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8, RL_s_config_axiReadSpecial_9,\n RL_s_config_axiReadSpecialIsHandled_9, RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10, RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_8 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8) && - (WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8] and [RL_s_config_axiReadSpecial_9,\n RL_s_config_axiReadSpecialIsHandled_9, RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10, RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); + $display("btt org %d, btt after %d", readIn_rv[63:0], btt__h102029); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_s_config_axiReadSpecial_7 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7) && (WILL_FIRE_RL_s_config_axiReadSpecial_8 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 || - WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7] and [RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8, RL_s_config_axiReadSpecial_9,\n RL_s_config_axiReadSpecialIsHandled_9, RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10, RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9) && - (WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_9,\n RL_s_config_axiReadSpecialIsHandled_9] and [RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10, RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10) && - (WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10] and [RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11) && - (WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11] and [RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12) && - (WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12] and [RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13) && - (WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13] and [RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14) && - (WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14] and [RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15) && - (WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15] and [RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16) && - (WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16] and [RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8)) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7] and [RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled && WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled) @@ -6184,17 +5711,221 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_1_axiWriteSpecial) $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_2 and\n RL_s_config_1_axiWriteSpecial called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 && + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 && WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1) $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_3 and\n RL_s_config_1_axiWriteSpecialIsHandled_2 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 && + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 && WILL_FIRE_RL_s_config_axiReadSpecialIsHandled) $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_3 and\n RL_s_config_1_axiWriteSpecialIsHandled_1 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 && + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 && WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled) $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_3 and\n RL_s_config_1_axiWriteSpecialIsHandled called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_4 and\n RL_s_config_1_axiWriteSpecialIsHandled_3 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_4 and\n RL_s_config_1_axiWriteSpecialIsHandled_2 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_4 and\n RL_s_config_1_axiWriteSpecialIsHandled_1 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_4 and\n RL_s_config_1_axiWriteSpecialIsHandled called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial_3 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial_3 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial_3 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_4 and\n RL_s_config_1_axiWriteSpecial called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_5 and\n RL_s_config_1_axiWriteSpecialIsHandled_4 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_5 and\n RL_s_config_1_axiWriteSpecialIsHandled_3 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_5 and\n RL_s_config_1_axiWriteSpecialIsHandled_2 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_5 and\n RL_s_config_1_axiWriteSpecialIsHandled_1 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_5 and\n RL_s_config_1_axiWriteSpecialIsHandled called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_4 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_4 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_4 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_3 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_3 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_3 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_5 and\n RL_s_config_1_axiWriteSpecial called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_6 and\n RL_s_config_1_axiWriteSpecialIsHandled_5 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_6 and\n RL_s_config_1_axiWriteSpecialIsHandled_4 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_6 and\n RL_s_config_1_axiWriteSpecialIsHandled_3 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_6 and\n RL_s_config_1_axiWriteSpecialIsHandled_2 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_6 and\n RL_s_config_1_axiWriteSpecialIsHandled_1 called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 218, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecialIsHandled_6 and\n RL_s_config_1_axiWriteSpecialIsHandled called conflicting methods wset and\n wset of module instance s_config_writeIsHandled.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_s_config_axiReadSpecial_1 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1) && @@ -6211,26 +5942,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_axiReadSpecial_7 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || WILL_FIRE_RL_s_config_axiReadSpecial_8 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 || - WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_1,\n RL_s_config_axiReadSpecialIsHandled_1] and [RL_s_config_axiReadSpecial_2,\n RL_s_config_axiReadSpecialIsHandled_2, RL_s_config_axiReadSpecial_3,\n RL_s_config_axiReadSpecialIsHandled_3, RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4, RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8, RL_s_config_axiReadSpecial_9,\n RL_s_config_axiReadSpecialIsHandled_9, RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10, RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8)) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_1,\n RL_s_config_axiReadSpecialIsHandled_1] and [RL_s_config_axiReadSpecial_2,\n RL_s_config_axiReadSpecialIsHandled_2, RL_s_config_axiReadSpecial_3,\n RL_s_config_axiReadSpecialIsHandled_3, RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4, RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_s_config_axiReadSpecial_2 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2) && @@ -6245,26 +5958,20 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_axiReadSpecial_7 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || WILL_FIRE_RL_s_config_axiReadSpecial_8 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 || - WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_2,\n RL_s_config_axiReadSpecialIsHandled_2] and [RL_s_config_axiReadSpecial_3,\n RL_s_config_axiReadSpecialIsHandled_3, RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4, RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8, RL_s_config_axiReadSpecial_9,\n RL_s_config_axiReadSpecialIsHandled_9, RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10, RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8)) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_2,\n RL_s_config_axiReadSpecialIsHandled_2] and [RL_s_config_axiReadSpecial_3,\n RL_s_config_axiReadSpecialIsHandled_3, RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4, RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_s_config_axiReadSpecial_4 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4) && + (WILL_FIRE_RL_s_config_axiReadSpecial_5 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_5 || + WILL_FIRE_RL_s_config_axiReadSpecial_6 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 || + WILL_FIRE_RL_s_config_axiReadSpecial_7 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || + WILL_FIRE_RL_s_config_axiReadSpecial_8 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8)) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4] and [RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_s_config_axiReadSpecial_3 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3) && @@ -6277,26 +5984,26 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_axiReadSpecial_7 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || WILL_FIRE_RL_s_config_axiReadSpecial_8 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 || - WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_3,\n RL_s_config_axiReadSpecialIsHandled_3] and [RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4, RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8, RL_s_config_axiReadSpecial_9,\n RL_s_config_axiReadSpecialIsHandled_9, RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10, RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8)) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_3,\n RL_s_config_axiReadSpecialIsHandled_3] and [RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4, RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_s_config_axiReadSpecial_5 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_5) && + (WILL_FIRE_RL_s_config_axiReadSpecial_6 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 || + WILL_FIRE_RL_s_config_axiReadSpecial_7 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || + WILL_FIRE_RL_s_config_axiReadSpecial_8 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8)) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5] and [RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_s_config_axiReadSpecial_6 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6) && + (WILL_FIRE_RL_s_config_axiReadSpecial_7 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || + WILL_FIRE_RL_s_config_axiReadSpecial_8 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8)) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6] and [RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_s_config_axiReadSpecial || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled) && @@ -6315,26 +6022,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_axiReadSpecial_7 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || WILL_FIRE_RL_s_config_axiReadSpecial_8 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 || - WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17)) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial,\n RL_s_config_axiReadSpecialIsHandled] and [RL_s_config_axiReadSpecial_1,\n RL_s_config_axiReadSpecialIsHandled_1, RL_s_config_axiReadSpecial_2,\n RL_s_config_axiReadSpecialIsHandled_2, RL_s_config_axiReadSpecial_3,\n RL_s_config_axiReadSpecialIsHandled_3, RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4, RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8, RL_s_config_axiReadSpecial_9,\n RL_s_config_axiReadSpecialIsHandled_9, RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10, RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] ) fired in the same clock cycle.\n"); + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8)) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial,\n RL_s_config_axiReadSpecialIsHandled] and [RL_s_config_axiReadSpecial_1,\n RL_s_config_axiReadSpecialIsHandled_1, RL_s_config_axiReadSpecial_2,\n RL_s_config_axiReadSpecialIsHandled_2, RL_s_config_axiReadSpecial_3,\n RL_s_config_axiReadSpecialIsHandled_3, RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4, RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_s_config_axiReadSpecial || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled || @@ -6353,63 +6042,81 @@ module mkBlueDMA(CLK_m32_axi_aclk, WILL_FIRE_RL_s_config_axiReadSpecial_7 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 || WILL_FIRE_RL_s_config_axiReadSpecial_8 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 || - WILL_FIRE_RL_s_config_axiReadSpecial_9 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_9 || - WILL_FIRE_RL_s_config_axiReadSpecial_10 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_10 || - WILL_FIRE_RL_s_config_axiReadSpecial_11 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_11 || - WILL_FIRE_RL_s_config_axiReadSpecial_12 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_12 || - WILL_FIRE_RL_s_config_axiReadSpecial_13 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_13 || - WILL_FIRE_RL_s_config_axiReadSpecial_14 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_14 || - WILL_FIRE_RL_s_config_axiReadSpecial_15 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_15 || - WILL_FIRE_RL_s_config_axiReadSpecial_16 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_16 || - WILL_FIRE_RL_s_config_axiReadSpecial_17 || - WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_17) && + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8) && WILL_FIRE_RL_s_config_axiReadFallback) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial,\n RL_s_config_axiReadSpecialIsHandled, RL_s_config_axiReadSpecial_1,\n RL_s_config_axiReadSpecialIsHandled_1, RL_s_config_axiReadSpecial_2,\n RL_s_config_axiReadSpecialIsHandled_2, RL_s_config_axiReadSpecial_3,\n RL_s_config_axiReadSpecialIsHandled_3, RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4, RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8, RL_s_config_axiReadSpecial_9,\n RL_s_config_axiReadSpecialIsHandled_9, RL_s_config_axiReadSpecial_10,\n RL_s_config_axiReadSpecialIsHandled_10, RL_s_config_axiReadSpecial_11,\n RL_s_config_axiReadSpecialIsHandled_11, RL_s_config_axiReadSpecial_12,\n RL_s_config_axiReadSpecialIsHandled_12, RL_s_config_axiReadSpecial_13,\n RL_s_config_axiReadSpecialIsHandled_13, RL_s_config_axiReadSpecial_14,\n RL_s_config_axiReadSpecialIsHandled_14, RL_s_config_axiReadSpecial_15,\n RL_s_config_axiReadSpecialIsHandled_15, RL_s_config_axiReadSpecial_16,\n RL_s_config_axiReadSpecialIsHandled_16, RL_s_config_axiReadSpecial_17,\n RL_s_config_axiReadSpecialIsHandled_17] and [RL_s_config_axiReadFallback] )\n fired in the same clock cycle.\n"); + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 119, column 18: (R0001)\n Mutually exclusive rules (from the ME sets [RL_s_config_axiReadSpecial,\n RL_s_config_axiReadSpecialIsHandled, RL_s_config_axiReadSpecial_1,\n RL_s_config_axiReadSpecialIsHandled_1, RL_s_config_axiReadSpecial_2,\n RL_s_config_axiReadSpecialIsHandled_2, RL_s_config_axiReadSpecial_3,\n RL_s_config_axiReadSpecialIsHandled_3, RL_s_config_axiReadSpecial_4,\n RL_s_config_axiReadSpecialIsHandled_4, RL_s_config_axiReadSpecial_5,\n RL_s_config_axiReadSpecialIsHandled_5, RL_s_config_axiReadSpecial_6,\n RL_s_config_axiReadSpecialIsHandled_6, RL_s_config_axiReadSpecial_7,\n RL_s_config_axiReadSpecialIsHandled_7, RL_s_config_axiReadSpecial_8,\n RL_s_config_axiReadSpecialIsHandled_8] and [RL_s_config_axiReadFallback] )\n fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_5) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_5 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_5) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_5 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_5) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_5 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_4 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_4 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_4 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_3 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_3 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3) + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_3 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && WILL_FIRE_RL_s_config_1_axiWriteSpecial_2) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_2 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial_1 called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && WILL_FIRE_RL_s_config_1_axiWriteSpecial) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial called conflicting methods first and deq of\n module instance s_config_writeSlave_in.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && WILL_FIRE_RL_s_config_1_axiWriteSpecial) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial called conflicting methods deq and deq of\n module instance s_config_writeSlave_in.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 && WILL_FIRE_RL_s_config_1_axiWriteSpecial) - $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_3 and\n RL_s_config_1_axiWriteSpecial called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); + $display("Error: \"../BlueAXI/src/GenericAxi4LiteSlave.bsv\", line 207, column 18: (R0002)\n Conflict-free rules RL_s_config_1_axiWriteSpecial_6 and\n RL_s_config_1_axiWriteSpecial called conflicting methods enq and enq of\n module instance s_config_writeSlave_out.\n"); end // synopsys translate_on @@ -6443,10 +6150,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_wr_reqGen_finishRequest) $display("[WRITE] requests_total: %d", - request_data_requests_total__h38454); + request_data_requests_total__h40467); if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_wr_reqGen_finishRequest) - $display("[WRITE] address: %x", request_data_address__h38455); + $display("[WRITE] address: %x", request_data_address__h40468); if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest) $display("[READ] request:"); @@ -6473,10 +6180,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest) $display("[READ] requests_total: %d", - request_data_requests_total__h53801); + request_data_requests_total__h55799); if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest) - $display("[READ] address: %x", request_data_address__h53802); + $display("[READ] address: %x", request_data_address__h55800); end // synopsys translate_on @@ -6505,14 +6212,14 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[72:68]); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_wr_reqGen_finishRequest) - $display("[WRITE] requests_last: %d", requests_last__h24574); + $display("[WRITE] requests_last: %d", requests_last__h26617); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_wr_reqGen_finishRequest) $display("[WRITE] requests_total: %d", - request_data_requests_total__h24611); + request_data_requests_total__h26654); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_wr_reqGen_finishRequest) - $display("[WRITE] address: %x", request_data_address__h24612); + $display("[WRITE] address: %x", request_data_address__h26655); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest) $display("[READ] request:"); @@ -6534,14 +6241,14 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[72:68]); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest) - $display("[READ] requests_last: %d", requests_last__h34528); + $display("[READ] requests_last: %d", requests_last__h36556); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest) $display("[READ] requests_total: %d", - request_data_requests_total__h34565); + request_data_requests_total__h36593); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest) - $display("[READ] address: %x", request_data_address__h34566); + $display("[READ] address: %x", request_data_address__h36594); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (byteAlignerReader_addr_ff$dEMPTY_N) $display("Init data:"); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) diff --git a/common/ip/BlueDMA/src/mkBlueDMAVivado.v b/common/ip/BlueDMA/src/mkBlueDMAVivado.v index ff067d3f..2f9e18e0 100644 --- a/common/ip/BlueDMA/src/mkBlueDMAVivado.v +++ b/common/ip/BlueDMA/src/mkBlueDMAVivado.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07) // -// On Fri Jul 7 10:38:51 CEST 2017 +// On Fri Jul 7 14:37:18 CEST 2017 // // // Ports: @@ -15,7 +15,6 @@ // S_AXI_bvalid O 1 reg // S_AXI_bresp O 2 // m64_axi_arvalid O 1 reg -// m64_axi_arid O 1 // m64_axi_araddr O 64 // m64_axi_arlen O 8 // m64_axi_arsize O 3 @@ -28,7 +27,6 @@ // m64_axi_aruser O 1 // m64_axi_rready O 1 reg // m64_axi_awvalid O 1 reg -// m64_axi_awid O 1 // m64_axi_awaddr O 64 // m64_axi_awlen O 8 // m64_axi_awsize O 3 @@ -46,7 +44,6 @@ // m64_axi_wuser O 1 // m64_axi_bready O 1 reg // m32_axi_arvalid O 1 reg -// m32_axi_arid O 1 // m32_axi_araddr O 64 // m32_axi_arlen O 8 // m32_axi_arsize O 3 @@ -59,7 +56,6 @@ // m32_axi_aruser O 1 // m32_axi_rready O 1 reg // m32_axi_awvalid O 1 reg -// m32_axi_awid O 1 // m32_axi_awaddr O 64 // m32_axi_awlen O 8 // m32_axi_awsize O 3 @@ -96,7 +92,6 @@ // S_AXI_bready I 1 // m64_axi_arready I 1 // m64_axi_rvalid I 1 -// m64_axi_rid I 1 reg // m64_axi_rdata I 256 reg // m64_axi_rresp I 2 reg // m64_axi_rlast I 1 reg @@ -105,11 +100,9 @@ // m64_axi_wready I 1 // m64_axi_bvalid I 1 // m64_axi_bresp I 2 reg -// m64_axi_bid I 1 reg // m64_axi_buser I 1 reg // m32_axi_arready I 1 // m32_axi_rvalid I 1 -// m32_axi_rid I 1 reg // m32_axi_rdata I 512 reg // m32_axi_rresp I 2 reg // m32_axi_rlast I 1 reg @@ -118,7 +111,6 @@ // m32_axi_wready I 1 // m32_axi_bvalid I 1 // m32_axi_bresp I 2 reg -// m32_axi_bid I 1 reg // m32_axi_buser I 1 reg // // No combinational paths from inputs to outputs @@ -187,8 +179,6 @@ module mkBlueDMAVivado(m32_axi_aclk, m64_axi_arready, - m64_axi_arid, - m64_axi_araddr, m64_axi_arlen, @@ -213,7 +203,6 @@ module mkBlueDMAVivado(m32_axi_aclk, m64_axi_rvalid, - m64_axi_rid, m64_axi_rdata, m64_axi_rresp, m64_axi_rlast, @@ -223,8 +212,6 @@ module mkBlueDMAVivado(m32_axi_aclk, m64_axi_awvalid, - m64_axi_awid, - m64_axi_awaddr, m64_axi_awlen, @@ -262,15 +249,12 @@ module mkBlueDMAVivado(m32_axi_aclk, m64_axi_bready, m64_axi_bresp, - m64_axi_bid, m64_axi_buser, m32_axi_arvalid, m32_axi_arready, - m32_axi_arid, - m32_axi_araddr, m32_axi_arlen, @@ -295,7 +279,6 @@ module mkBlueDMAVivado(m32_axi_aclk, m32_axi_rvalid, - m32_axi_rid, m32_axi_rdata, m32_axi_rresp, m32_axi_rlast, @@ -305,8 +288,6 @@ module mkBlueDMAVivado(m32_axi_aclk, m32_axi_awvalid, - m32_axi_awid, - m32_axi_awaddr, m32_axi_awlen, @@ -344,7 +325,6 @@ module mkBlueDMAVivado(m32_axi_aclk, m32_axi_bready, m32_axi_bresp, - m32_axi_bid, m32_axi_buser, IRQ); @@ -419,7 +399,6 @@ module mkBlueDMAVivado(m32_axi_aclk, input m64_axi_arready; // value method pcie_rd_arid - output m64_axi_arid; // value method pcie_rd_araddr output [63 : 0] m64_axi_araddr; @@ -458,7 +437,6 @@ module mkBlueDMAVivado(m32_axi_aclk, input m64_axi_rvalid; // action method pcie_rd_prchannel - input m64_axi_rid; input [255 : 0] m64_axi_rdata; input [1 : 0] m64_axi_rresp; input m64_axi_rlast; @@ -471,7 +449,6 @@ module mkBlueDMAVivado(m32_axi_aclk, output m64_axi_awvalid; // value method pcie_wr_awid - output m64_axi_awid; // value method pcie_wr_awaddr output [63 : 0] m64_axi_awaddr; @@ -529,7 +506,6 @@ module mkBlueDMAVivado(m32_axi_aclk, // action method pcie_wr_bin input [1 : 0] m64_axi_bresp; - input m64_axi_bid; input m64_axi_buser; // value method fpga_rd_arvalid @@ -539,7 +515,6 @@ module mkBlueDMAVivado(m32_axi_aclk, input m32_axi_arready; // value method fpga_rd_arid - output m32_axi_arid; // value method fpga_rd_araddr output [63 : 0] m32_axi_araddr; @@ -578,7 +553,6 @@ module mkBlueDMAVivado(m32_axi_aclk, input m32_axi_rvalid; // action method fpga_rd_prchannel - input m32_axi_rid; input [511 : 0] m32_axi_rdata; input [1 : 0] m32_axi_rresp; input m32_axi_rlast; @@ -591,7 +565,6 @@ module mkBlueDMAVivado(m32_axi_aclk, output m32_axi_awvalid; // value method fpga_wr_awid - output m32_axi_awid; // value method fpga_wr_awaddr output [63 : 0] m32_axi_awaddr; @@ -649,7 +622,6 @@ module mkBlueDMAVivado(m32_axi_aclk, // action method fpga_wr_bin input [1 : 0] m32_axi_bresp; - input m32_axi_bid; input m32_axi_buser; // value method interrupt @@ -698,11 +670,9 @@ module mkBlueDMAVivado(m32_axi_aclk, S_AXI_bvalid, S_AXI_rvalid, S_AXI_wready, - m32_axi_arid, m32_axi_arlock, m32_axi_aruser, m32_axi_arvalid, - m32_axi_awid, m32_axi_awlock, m32_axi_awuser, m32_axi_awvalid, @@ -711,11 +681,9 @@ module mkBlueDMAVivado(m32_axi_aclk, m32_axi_wlast, m32_axi_wuser, m32_axi_wvalid, - m64_axi_arid, m64_axi_arlock, m64_axi_aruser, m64_axi_arvalid, - m64_axi_awid, m64_axi_awlock, m64_axi_awuser, m64_axi_awvalid, @@ -785,22 +753,18 @@ module mkBlueDMAVivado(m32_axi_aclk, blueDMA$S_AXI_rvalid, blueDMA$S_AXI_wready, blueDMA$S_AXI_wvalid, - blueDMA$fpga_rd_arid, blueDMA$fpga_rd_arlock, blueDMA$fpga_rd_arready, blueDMA$fpga_rd_aruser, blueDMA$fpga_rd_arvalid, - blueDMA$fpga_rd_rid, blueDMA$fpga_rd_rlast, blueDMA$fpga_rd_rready, blueDMA$fpga_rd_ruser, blueDMA$fpga_rd_rvalid, - blueDMA$fpga_wr_awid, blueDMA$fpga_wr_awlock, blueDMA$fpga_wr_awready, blueDMA$fpga_wr_awuser, blueDMA$fpga_wr_awvalid, - blueDMA$fpga_wr_bid, blueDMA$fpga_wr_bready, blueDMA$fpga_wr_buser, blueDMA$fpga_wr_bvalid, @@ -809,22 +773,18 @@ module mkBlueDMAVivado(m32_axi_aclk, blueDMA$fpga_wr_wuser, blueDMA$fpga_wr_wvalid, blueDMA$interrupt, - blueDMA$pcie_rd_arid, blueDMA$pcie_rd_arlock, blueDMA$pcie_rd_arready, blueDMA$pcie_rd_aruser, blueDMA$pcie_rd_arvalid, - blueDMA$pcie_rd_rid, blueDMA$pcie_rd_rlast, blueDMA$pcie_rd_rready, blueDMA$pcie_rd_ruser, blueDMA$pcie_rd_rvalid, - blueDMA$pcie_wr_awid, blueDMA$pcie_wr_awlock, blueDMA$pcie_wr_awready, blueDMA$pcie_wr_awuser, blueDMA$pcie_wr_awvalid, - blueDMA$pcie_wr_bid, blueDMA$pcie_wr_bready, blueDMA$pcie_wr_buser, blueDMA$pcie_wr_bvalid, @@ -860,9 +820,6 @@ module mkBlueDMAVivado(m32_axi_aclk, // value method pcie_rd_arvalid assign m64_axi_arvalid = blueDMA$pcie_rd_arvalid ; - // value method pcie_rd_arid - assign m64_axi_arid = blueDMA$pcie_rd_arid ; - // value method pcie_rd_araddr assign m64_axi_araddr = blueDMA$pcie_rd_araddr ; @@ -906,9 +863,6 @@ module mkBlueDMAVivado(m32_axi_aclk, // value method pcie_wr_awvalid assign m64_axi_awvalid = blueDMA$pcie_wr_awvalid ; - // value method pcie_wr_awid - assign m64_axi_awid = blueDMA$pcie_wr_awid ; - // value method pcie_wr_awaddr assign m64_axi_awaddr = blueDMA$pcie_wr_awaddr ; @@ -967,9 +921,6 @@ module mkBlueDMAVivado(m32_axi_aclk, // value method fpga_rd_arvalid assign m32_axi_arvalid = blueDMA$fpga_rd_arvalid ; - // value method fpga_rd_arid - assign m32_axi_arid = blueDMA$fpga_rd_arid ; - // value method fpga_rd_araddr assign m32_axi_araddr = blueDMA$fpga_rd_araddr ; @@ -1013,9 +964,6 @@ module mkBlueDMAVivado(m32_axi_aclk, // value method fpga_wr_awvalid assign m32_axi_awvalid = blueDMA$fpga_wr_awvalid ; - // value method fpga_wr_awid - assign m32_axi_awid = blueDMA$fpga_wr_awid ; - // value method fpga_wr_awaddr assign m32_axi_awaddr = blueDMA$fpga_wr_awaddr ; @@ -1094,26 +1042,22 @@ module mkBlueDMAVivado(m32_axi_aclk, .S_AXI_wvalid(blueDMA$S_AXI_wvalid), .fpga_rd_arready(blueDMA$fpga_rd_arready), .fpga_rd_rdata(blueDMA$fpga_rd_rdata), - .fpga_rd_rid(blueDMA$fpga_rd_rid), .fpga_rd_rlast(blueDMA$fpga_rd_rlast), .fpga_rd_rresp(blueDMA$fpga_rd_rresp), .fpga_rd_ruser(blueDMA$fpga_rd_ruser), .fpga_rd_rvalid(blueDMA$fpga_rd_rvalid), .fpga_wr_awready(blueDMA$fpga_wr_awready), - .fpga_wr_bid(blueDMA$fpga_wr_bid), .fpga_wr_bresp(blueDMA$fpga_wr_bresp), .fpga_wr_buser(blueDMA$fpga_wr_buser), .fpga_wr_bvalid(blueDMA$fpga_wr_bvalid), .fpga_wr_wready(blueDMA$fpga_wr_wready), .pcie_rd_arready(blueDMA$pcie_rd_arready), .pcie_rd_rdata(blueDMA$pcie_rd_rdata), - .pcie_rd_rid(blueDMA$pcie_rd_rid), .pcie_rd_rlast(blueDMA$pcie_rd_rlast), .pcie_rd_rresp(blueDMA$pcie_rd_rresp), .pcie_rd_ruser(blueDMA$pcie_rd_ruser), .pcie_rd_rvalid(blueDMA$pcie_rd_rvalid), .pcie_wr_awready(blueDMA$pcie_wr_awready), - .pcie_wr_bid(blueDMA$pcie_wr_bid), .pcie_wr_bresp(blueDMA$pcie_wr_bresp), .pcie_wr_buser(blueDMA$pcie_wr_buser), .pcie_wr_bvalid(blueDMA$pcie_wr_bvalid), @@ -1127,7 +1071,6 @@ module mkBlueDMAVivado(m32_axi_aclk, .S_AXI_bvalid(blueDMA$S_AXI_bvalid), .S_AXI_bresp(blueDMA$S_AXI_bresp), .pcie_rd_arvalid(blueDMA$pcie_rd_arvalid), - .pcie_rd_arid(blueDMA$pcie_rd_arid), .pcie_rd_araddr(blueDMA$pcie_rd_araddr), .pcie_rd_arlen(blueDMA$pcie_rd_arlen), .pcie_rd_arsize(blueDMA$pcie_rd_arsize), @@ -1140,7 +1083,6 @@ module mkBlueDMAVivado(m32_axi_aclk, .pcie_rd_aruser(blueDMA$pcie_rd_aruser), .pcie_rd_rready(blueDMA$pcie_rd_rready), .pcie_wr_awvalid(blueDMA$pcie_wr_awvalid), - .pcie_wr_awid(blueDMA$pcie_wr_awid), .pcie_wr_awaddr(blueDMA$pcie_wr_awaddr), .pcie_wr_awlen(blueDMA$pcie_wr_awlen), .pcie_wr_awsize(blueDMA$pcie_wr_awsize), @@ -1158,7 +1100,6 @@ module mkBlueDMAVivado(m32_axi_aclk, .pcie_wr_wuser(blueDMA$pcie_wr_wuser), .pcie_wr_bready(blueDMA$pcie_wr_bready), .fpga_rd_arvalid(blueDMA$fpga_rd_arvalid), - .fpga_rd_arid(blueDMA$fpga_rd_arid), .fpga_rd_araddr(blueDMA$fpga_rd_araddr), .fpga_rd_arlen(blueDMA$fpga_rd_arlen), .fpga_rd_arsize(blueDMA$fpga_rd_arsize), @@ -1171,7 +1112,6 @@ module mkBlueDMAVivado(m32_axi_aclk, .fpga_rd_aruser(blueDMA$fpga_rd_aruser), .fpga_rd_rready(blueDMA$fpga_rd_rready), .fpga_wr_awvalid(blueDMA$fpga_wr_awvalid), - .fpga_wr_awid(blueDMA$fpga_wr_awid), .fpga_wr_awaddr(blueDMA$fpga_wr_awaddr), .fpga_wr_awlen(blueDMA$fpga_wr_awlen), .fpga_wr_awsize(blueDMA$fpga_wr_awsize), @@ -1204,26 +1144,22 @@ module mkBlueDMAVivado(m32_axi_aclk, assign blueDMA$S_AXI_wvalid = S_AXI_wvalid ; assign blueDMA$fpga_rd_arready = m32_axi_arready ; assign blueDMA$fpga_rd_rdata = m32_axi_rdata ; - assign blueDMA$fpga_rd_rid = m32_axi_rid ; assign blueDMA$fpga_rd_rlast = m32_axi_rlast ; assign blueDMA$fpga_rd_rresp = m32_axi_rresp ; assign blueDMA$fpga_rd_ruser = m32_axi_ruser ; assign blueDMA$fpga_rd_rvalid = m32_axi_rvalid ; assign blueDMA$fpga_wr_awready = m32_axi_awready ; - assign blueDMA$fpga_wr_bid = m32_axi_bid ; assign blueDMA$fpga_wr_bresp = m32_axi_bresp ; assign blueDMA$fpga_wr_buser = m32_axi_buser ; assign blueDMA$fpga_wr_bvalid = m32_axi_bvalid ; assign blueDMA$fpga_wr_wready = m32_axi_wready ; assign blueDMA$pcie_rd_arready = m64_axi_arready ; assign blueDMA$pcie_rd_rdata = m64_axi_rdata ; - assign blueDMA$pcie_rd_rid = m64_axi_rid ; assign blueDMA$pcie_rd_rlast = m64_axi_rlast ; assign blueDMA$pcie_rd_rresp = m64_axi_rresp ; assign blueDMA$pcie_rd_ruser = m64_axi_ruser ; assign blueDMA$pcie_rd_rvalid = m64_axi_rvalid ; assign blueDMA$pcie_wr_awready = m64_axi_awready ; - assign blueDMA$pcie_wr_bid = m64_axi_bid ; assign blueDMA$pcie_wr_bresp = m64_axi_bresp ; assign blueDMA$pcie_wr_buser = m64_axi_buser ; assign blueDMA$pcie_wr_bvalid = m64_axi_bvalid ; -- GitLab From 1221cbdccf28c35e098f08483326f8d4ecfa4127 Mon Sep 17 00:00:00 2001 From: Jaco Hofmann Date: Mon, 10 Jul 2017 18:47:34 +0200 Subject: [PATCH 2/2] Adds ID signals back in to avoid Vivado errors --- common/ip/BlueDMA/component.xml | 194 +++- common/ip/BlueDMA/src/mkBlueDMA.v | 1136 ++++++++++++----------- common/ip/BlueDMA/src/mkBlueDMAVivado.v | 66 +- 3 files changed, 853 insertions(+), 543 deletions(-) diff --git a/common/ip/BlueDMA/component.xml b/common/ip/BlueDMA/component.xml index eeaa28d8..f03d3606 100644 --- a/common/ip/BlueDMA/component.xml +++ b/common/ip/BlueDMA/component.xml @@ -175,6 +175,14 @@ + + + AWID + + + m32_axi_awid + + AWADDR @@ -319,6 +327,14 @@ m32_axi_wready + + + BID + + + m32_axi_bid + + BRESP @@ -351,6 +367,14 @@ m32_axi_bready + + + ARID + + + m32_axi_arid + + ARADDR @@ -447,6 +471,14 @@ m32_axi_arready + + + RID + + + m32_axi_rid + + RDATA @@ -519,6 +551,14 @@ + + + AWID + + + m64_axi_awid + + AWADDR @@ -663,6 +703,14 @@ m64_axi_wready + + + BID + + + m64_axi_bid + + BRESP @@ -695,6 +743,14 @@ m64_axi_bready + + + ARID + + + m64_axi_arid + + ARADDR @@ -791,6 +847,14 @@ m64_axi_arready + + + RID + + + m64_axi_rid + + RDATA @@ -1060,7 +1124,7 @@ viewChecksum - d8bbcf6d + 069857fc @@ -1076,7 +1140,7 @@ viewChecksum - d8bbcf6d + 069857fc @@ -1519,6 +1583,19 @@ + + m64_axi_arid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + m64_axi_araddr @@ -1710,6 +1787,22 @@ + + m64_axi_rid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + m64_axi_rdata @@ -1811,6 +1904,19 @@ + + m64_axi_awid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + m64_axi_awaddr @@ -2111,6 +2217,22 @@ + + m64_axi_bid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + m64_axi_buser @@ -2156,6 +2278,19 @@ + + m32_axi_arid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + m32_axi_araddr @@ -2347,6 +2482,22 @@ + + m32_axi_rid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + m32_axi_rdata @@ -2448,6 +2599,19 @@ + + m32_axi_awid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + m32_axi_awaddr @@ -2748,6 +2912,22 @@ + + m32_axi_bid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + m32_axi_buser @@ -2823,7 +3003,7 @@ src/mkBlueDMAVivado.v verilogSource - CHECKSUM_ded56ed9 + CHECKSUM_abab4df6 @@ -2887,18 +3067,18 @@ BlueDMA package_project 1 - 2017-07-07T14:29:44Z + 2017-07-10T16:46:33Z 2016.4 - + - - + + diff --git a/common/ip/BlueDMA/src/mkBlueDMA.v b/common/ip/BlueDMA/src/mkBlueDMA.v index 460dbcbf..c0bfcfe1 100644 --- a/common/ip/BlueDMA/src/mkBlueDMA.v +++ b/common/ip/BlueDMA/src/mkBlueDMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07) // -// On Fri Jul 7 14:37:16 CEST 2017 +// On Mon Jul 10 18:45:53 CEST 2017 // // // Ports: @@ -15,6 +15,7 @@ // S_AXI_bvalid O 1 reg // S_AXI_bresp O 2 // pcie_rd_arvalid O 1 reg +// pcie_rd_arid O 1 // pcie_rd_araddr O 64 // pcie_rd_arlen O 8 // pcie_rd_arsize O 3 @@ -27,6 +28,7 @@ // pcie_rd_aruser O 1 // pcie_rd_rready O 1 reg // pcie_wr_awvalid O 1 reg +// pcie_wr_awid O 1 // pcie_wr_awaddr O 64 // pcie_wr_awlen O 8 // pcie_wr_awsize O 3 @@ -44,6 +46,7 @@ // pcie_wr_wuser O 1 // pcie_wr_bready O 1 reg // fpga_rd_arvalid O 1 reg +// fpga_rd_arid O 1 // fpga_rd_araddr O 64 // fpga_rd_arlen O 8 // fpga_rd_arsize O 3 @@ -56,6 +59,7 @@ // fpga_rd_aruser O 1 // fpga_rd_rready O 1 reg // fpga_wr_awvalid O 1 reg +// fpga_wr_awid O 1 // fpga_wr_awaddr O 64 // fpga_wr_awlen O 8 // fpga_wr_awsize O 3 @@ -92,6 +96,7 @@ // S_AXI_bready I 1 // pcie_rd_arready I 1 // pcie_rd_rvalid I 1 +// pcie_rd_rid I 1 reg // pcie_rd_rdata I 256 reg // pcie_rd_rresp I 2 reg // pcie_rd_rlast I 1 reg @@ -100,9 +105,11 @@ // pcie_wr_wready I 1 // pcie_wr_bvalid I 1 // pcie_wr_bresp I 2 reg +// pcie_wr_bid I 1 reg // pcie_wr_buser I 1 reg // fpga_rd_arready I 1 // fpga_rd_rvalid I 1 +// fpga_rd_rid I 1 reg // fpga_rd_rdata I 512 reg // fpga_rd_rresp I 2 reg // fpga_rd_rlast I 1 reg @@ -111,6 +118,7 @@ // fpga_wr_wready I 1 // fpga_wr_bvalid I 1 // fpga_wr_bresp I 2 reg +// fpga_wr_bid I 1 reg // fpga_wr_buser I 1 reg // // No combinational paths from inputs to outputs @@ -179,6 +187,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, pcie_rd_arready, + pcie_rd_arid, + pcie_rd_araddr, pcie_rd_arlen, @@ -203,6 +213,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, pcie_rd_rvalid, + pcie_rd_rid, pcie_rd_rdata, pcie_rd_rresp, pcie_rd_rlast, @@ -212,6 +223,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, pcie_wr_awvalid, + pcie_wr_awid, + pcie_wr_awaddr, pcie_wr_awlen, @@ -249,12 +262,15 @@ module mkBlueDMA(CLK_m32_axi_aclk, pcie_wr_bready, pcie_wr_bresp, + pcie_wr_bid, pcie_wr_buser, fpga_rd_arvalid, fpga_rd_arready, + fpga_rd_arid, + fpga_rd_araddr, fpga_rd_arlen, @@ -279,6 +295,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_rd_rvalid, + fpga_rd_rid, fpga_rd_rdata, fpga_rd_rresp, fpga_rd_rlast, @@ -288,6 +305,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_wr_awvalid, + fpga_wr_awid, + fpga_wr_awaddr, fpga_wr_awlen, @@ -325,6 +344,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_wr_bready, fpga_wr_bresp, + fpga_wr_bid, fpga_wr_buser, interrupt); @@ -399,6 +419,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, input pcie_rd_arready; // value method pcie_rd_arid + output pcie_rd_arid; // value method pcie_rd_araddr output [63 : 0] pcie_rd_araddr; @@ -437,6 +458,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, input pcie_rd_rvalid; // action method pcie_rd_prchannel + input pcie_rd_rid; input [255 : 0] pcie_rd_rdata; input [1 : 0] pcie_rd_rresp; input pcie_rd_rlast; @@ -449,6 +471,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, output pcie_wr_awvalid; // value method pcie_wr_awid + output pcie_wr_awid; // value method pcie_wr_awaddr output [63 : 0] pcie_wr_awaddr; @@ -506,6 +529,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // action method pcie_wr_bin input [1 : 0] pcie_wr_bresp; + input pcie_wr_bid; input pcie_wr_buser; // value method fpga_rd_arvalid @@ -515,6 +539,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, input fpga_rd_arready; // value method fpga_rd_arid + output fpga_rd_arid; // value method fpga_rd_araddr output [63 : 0] fpga_rd_araddr; @@ -553,6 +578,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, input fpga_rd_rvalid; // action method fpga_rd_prchannel + input fpga_rd_rid; input [511 : 0] fpga_rd_rdata; input [1 : 0] fpga_rd_rresp; input fpga_rd_rlast; @@ -565,6 +591,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, output fpga_wr_awvalid; // value method fpga_wr_awid + output fpga_wr_awid; // value method fpga_wr_awaddr output [63 : 0] fpga_wr_awaddr; @@ -622,6 +649,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // action method fpga_wr_bin input [1 : 0] fpga_wr_bresp; + input fpga_wr_bid; input fpga_wr_buser; // value method interrupt @@ -669,10 +697,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, S_AXI_bvalid, S_AXI_rvalid, S_AXI_wready, + fpga_rd_arid, fpga_rd_arlock, fpga_rd_aruser, fpga_rd_arvalid, fpga_rd_rready, + fpga_wr_awid, fpga_wr_awlock, fpga_wr_awuser, fpga_wr_awvalid, @@ -681,10 +711,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_wr_wuser, fpga_wr_wvalid, interrupt, + pcie_rd_arid, pcie_rd_arlock, pcie_rd_aruser, pcie_rd_arvalid, pcie_rd_rready, + pcie_wr_awid, pcie_wr_awlock, pcie_wr_awuser, pcie_wr_awvalid, @@ -698,7 +730,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_master_wr_wawcache$wget, m_pcie_rd_master_rd_warcache$wget, m_pcie_wr_master_wr_wawcache$wget; - wire [515 : 0] m_fpga_rd_master_rd_rinpkg$wget; + wire [516 : 0] m_fpga_rd_master_rd_rinpkg$wget; wire [511 : 0] byteAlignerReader_buffer$port0__write_1, byteAlignerReader_buffer$port1__read, byteAlignerReader_buffer$port1__write_1, @@ -707,7 +739,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_buffer$port1__read, byteAlignerWriter_buffer$port1__write_1, byteAlignerWriter_buffer$port2__read; - wire [259 : 0] m_pcie_rd_master_rd_rinpkg$wget; + wire [260 : 0] m_pcie_rd_master_rd_rinpkg$wget; wire [192 : 0] readIn_rv$port1__read, readIn_rv$port1__write_1, readIn_rv$port2__read, @@ -725,7 +757,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_bytes_left_in_buffer$port0__write_1, byteAlignerWriter_bytes_left_in_buffer$port1__write_1, byteAlignerWriter_bytes_left_in_buffer$port2__read; - wire [2 : 0] m_fpga_wr_master_wr_rinpkg$wget, + wire [3 : 0] m_fpga_wr_master_wr_rinpkg$wget, m_pcie_wr_master_wr_rinpkg$wget; wire byteAlignerReader_buffer$EN_port0__write, byteAlignerReader_bytes_left_in_buffer$EN_port0__write, @@ -1166,7 +1198,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, fpga_response_converter$sFULL_N; // ports of submodule m_fpga_rd_master_rd_in - wire [93 : 0] m_fpga_rd_master_rd_in$D_IN, m_fpga_rd_master_rd_in$D_OUT; + wire [94 : 0] m_fpga_rd_master_rd_in$D_IN, m_fpga_rd_master_rd_in$D_OUT; wire m_fpga_rd_master_rd_in$CLR, m_fpga_rd_master_rd_in$DEQ, m_fpga_rd_master_rd_in$EMPTY_N, @@ -1174,7 +1206,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_rd_master_rd_in$FULL_N; // ports of submodule m_fpga_rd_master_rd_out - wire [515 : 0] m_fpga_rd_master_rd_out$D_IN, m_fpga_rd_master_rd_out$D_OUT; + wire [516 : 0] m_fpga_rd_master_rd_out$D_IN, m_fpga_rd_master_rd_out$D_OUT; wire m_fpga_rd_master_rd_out$CLR, m_fpga_rd_master_rd_out$DEQ, m_fpga_rd_master_rd_out$EMPTY_N, @@ -1245,7 +1277,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_incomingBuffer$FULL_N; // ports of submodule m_fpga_wr_master_wr_in_addr - wire [93 : 0] m_fpga_wr_master_wr_in_addr$D_IN, + wire [94 : 0] m_fpga_wr_master_wr_in_addr$D_IN, m_fpga_wr_master_wr_in_addr$D_OUT; wire m_fpga_wr_master_wr_in_addr$CLR, m_fpga_wr_master_wr_in_addr$DEQ, @@ -1263,7 +1295,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_master_wr_in_data$FULL_N; // ports of submodule m_fpga_wr_master_wr_out - wire [2 : 0] m_fpga_wr_master_wr_out$D_IN; + wire [3 : 0] m_fpga_wr_master_wr_out$D_IN; wire m_fpga_wr_master_wr_out$CLR, m_fpga_wr_master_wr_out$DEQ, m_fpga_wr_master_wr_out$EMPTY_N, @@ -1307,7 +1339,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_fpga_wr_reqGen_outgoingBuffer$FULL_N; // ports of submodule m_pcie_rd_master_rd_in - wire [93 : 0] m_pcie_rd_master_rd_in$D_IN, m_pcie_rd_master_rd_in$D_OUT; + wire [94 : 0] m_pcie_rd_master_rd_in$D_IN, m_pcie_rd_master_rd_in$D_OUT; wire m_pcie_rd_master_rd_in$CLR, m_pcie_rd_master_rd_in$DEQ, m_pcie_rd_master_rd_in$EMPTY_N, @@ -1315,7 +1347,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_rd_master_rd_in$FULL_N; // ports of submodule m_pcie_rd_master_rd_out - wire [259 : 0] m_pcie_rd_master_rd_out$D_IN, m_pcie_rd_master_rd_out$D_OUT; + wire [260 : 0] m_pcie_rd_master_rd_out$D_IN, m_pcie_rd_master_rd_out$D_OUT; wire m_pcie_rd_master_rd_out$CLR, m_pcie_rd_master_rd_out$DEQ, m_pcie_rd_master_rd_out$EMPTY_N, @@ -1386,7 +1418,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_wr_incomingBuffer$FULL_N; // ports of submodule m_pcie_wr_master_wr_in_addr - wire [93 : 0] m_pcie_wr_master_wr_in_addr$D_IN, + wire [94 : 0] m_pcie_wr_master_wr_in_addr$D_IN, m_pcie_wr_master_wr_in_addr$D_OUT; wire m_pcie_wr_master_wr_in_addr$CLR, m_pcie_wr_master_wr_in_addr$DEQ, @@ -1404,7 +1436,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_wr_master_wr_in_data$FULL_N; // ports of submodule m_pcie_wr_master_wr_out - wire [2 : 0] m_pcie_wr_master_wr_out$D_IN; + wire [3 : 0] m_pcie_wr_master_wr_out$D_IN; wire m_pcie_wr_master_wr_out$CLR, m_pcie_wr_master_wr_out$DEQ, m_pcie_wr_master_wr_out$EMPTY_N, @@ -1651,126 +1683,126 @@ module mkBlueDMA(CLK_m32_axi_aclk, CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q2; wire [63 : 0] _theResult____h26331, _theResult____h26515, - _theResult____h36270, - _theResult____h36454, - _theResult____h40144, - _theResult____h40328, - _theResult____h55476, - _theResult____h55660, - btt__h102029, - btt__h145135, + _theResult____h36285, + _theResult____h36469, + _theResult____h40174, + _theResult____h40358, + _theResult____h55521, + _theResult____h55705, + btt__h102089, + btt__h145195, bytes_first___1__h26366, - bytes_first___1__h36305, - bytes_first___1__h40179, - bytes_first___1__h55511, + bytes_first___1__h36320, + bytes_first___1__h40209, + bytes_first___1__h55556, bytes_first__h26330, - bytes_first__h36269, - bytes_first__h40143, - bytes_first__h55475, + bytes_first__h36284, + bytes_first__h40173, + bytes_first__h55520, m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6, m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7, m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8, m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9, request_data_address__h26655, - request_data_address__h36594, - request_data_address__h40468, - request_data_address__h55800, + request_data_address__h36609, + request_data_address__h40498, + request_data_address__h55845, transfers_total___1__h26523, - transfers_total___1__h36462, - transfers_total___1__h40336, - transfers_total___1__h55668, + transfers_total___1__h36477, + transfers_total___1__h40366, + transfers_total___1__h55713, transfers_total__h26514, transfers_total__h26520, - transfers_total__h36453, - transfers_total__h36459, - transfers_total__h40327, - transfers_total__h40333, - transfers_total__h55659, - transfers_total__h55665, + transfers_total__h36468, + transfers_total__h36474, + transfers_total__h40357, + transfers_total__h40363, + transfers_total__h55704, + transfers_total__h55710, x__h26336, x__h26517, x__h26543, - x__h36275, - x__h36456, - x__h36482, - x__h40149, - x__h40330, - x__h40356, - x__h55481, - x__h55662, - x__h55688, - x_address__h29562, - x_address__h38704, - x_address__h43360, - x_address__h57907, - x_strb__h43876, - y__h102066, - y__h145163, + x__h36290, + x__h36471, + x__h36497, + x__h40179, + x__h40360, + x__h40386, + x__h55526, + x__h55707, + x__h55733, + x_address__h29577, + x_address__h38734, + x_address__h43405, + x_address__h57967, + x_strb__h43921, + y__h102126, + y__h145223, y__h26410, y__h26544, y__h26546, - y__h36349, - y__h36483, - y__h36485, - y__h40223, - y__h40357, - y__h40359, - y__h55555, - y__h55689, - y__h55691; + y__h36364, + y__h36498, + y__h36500, + y__h40253, + y__h40387, + y__h40389, + y__h55600, + y__h55734, + y__h55736; wire [58 : 0] request_data_requests_total__h26654, - request_data_requests_total__h36593, + request_data_requests_total__h36608, requests_total___1__h26680, - requests_total___1__h36619, + requests_total___1__h36634, requests_total__h26618, - requests_total__h36557, - x_requests_total__h29561, - x_requests_total__h38703, - x_transfers_total__h35588, - x_transfers_total__h39153; - wire [57 : 0] request_data_requests_total__h40467, - request_data_requests_total__h55799, - requests_total___1__h40493, - requests_total___1__h55825, - requests_total__h40431, - requests_total__h55763, - x_requests_total__h43359, - x_requests_total__h57906, - x_transfers_total__h54794, - x_transfers_total__h58356; - wire [31 : 0] x_strb__h30078; - wire [7 : 0] _theResult____h29456, - _theResult____h43254, - beatsThisRequestCntrT__h29964, - beatsThisRequestCntrT__h43762, - beatsThisRequest___1__h29504, - beatsThisRequest___1__h38675, - beatsThisRequest___1__h43302, - beatsThisRequest___1__h57878, + requests_total__h36572, + x_requests_total__h29576, + x_requests_total__h38733, + x_transfers_total__h35603, + x_transfers_total__h39183; + wire [57 : 0] request_data_requests_total__h40497, + request_data_requests_total__h55844, + requests_total___1__h40523, + requests_total___1__h55870, + requests_total__h40461, + requests_total__h55808, + x_requests_total__h43404, + x_requests_total__h57966, + x_transfers_total__h54839, + x_transfers_total__h58416; + wire [31 : 0] x_strb__h30093; + wire [7 : 0] _theResult____h29471, + _theResult____h43299, + beatsThisRequestCntrT__h29979, + beatsThisRequestCntrT__h43807, + beatsThisRequest___1__h29519, + beatsThisRequest___1__h38705, + beatsThisRequest___1__h43347, + beatsThisRequest___1__h57938, requests_last__h26617, - requests_last__h36556; - wire [6 : 0] IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944, - endByte___1__h46785, - endByte___1__h46811, - startByte___1__h46784, - x__h46771; - wire [5 : 0] IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463, - b__h115415, - b__h72232, - endByte___1__h31579, - endByte___1__h31605, - startByte___1__h31578, - x__h31565; + requests_last__h36571; + wire [6 : 0] IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950, + endByte___1__h46830, + endByte___1__h46856, + startByte___1__h46829, + x__h46816; + wire [5 : 0] IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465, + b__h115475, + b__h72292, + endByte___1__h31594, + endByte___1__h31620, + startByte___1__h31593, + x__h31580; wire [1 : 0] IF_0_CONCAT_readConverter_wordInCntr_EQ_1_OR_r_ETC__q1; - wire byteAlignerReader_bytes_in_430_ULT_byteAligner_ETC___d1432, - byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1447, - byteAlignerWriter_bytes_in_552_ULT_byteAligner_ETC___d1554, - byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1569, - fpgaLastCycle_662_AND_m_fpga_rd_task_data_outp_ETC___d1664, - m_fpga_wr_beatsThisRequestCntr_21_EQ_m_fpga_wr_ETC___d923, - m_pcie_wr_beatsThisRequestCntr_40_EQ_m_pcie_wr_ETC___d442, - pc_reqCntr_491_EQ_cycles_between_set_6_BITS_11_ETC___d1673, - pcieLastCycle_655_AND_m_pcie_rd_task_data_outp_ETC___d1657; + wire byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440, + byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455, + byteAlignerWriter_bytes_in_560_ULT_byteAligner_ETC___d1562, + byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1577, + fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672, + m_fpga_wr_beatsThisRequestCntr_27_EQ_m_fpga_wr_ETC___d929, + m_pcie_wr_beatsThisRequestCntr_42_EQ_m_pcie_wr_ETC___d444, + pc_reqCntr_499_EQ_cycles_between_set_6_BITS_11_ETC___d1681, + pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665; // value method s_rd_arready assign S_AXI_arready = s_config_readSlave_in$FULL_N ; @@ -1808,6 +1840,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, // value method pcie_rd_arvalid assign pcie_rd_arvalid = m_pcie_rd_master_rd_in$EMPTY_N ; + // value method pcie_rd_arid + assign pcie_rd_arid = + m_pcie_rd_master_rd_in$EMPTY_N && + m_pcie_rd_master_rd_in$D_OUT[94] ; + // value method pcie_rd_araddr assign pcie_rd_araddr = m_pcie_rd_master_rd_in$EMPTY_N ? @@ -1873,6 +1910,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, // value method pcie_wr_awvalid assign pcie_wr_awvalid = m_pcie_wr_master_wr_in_addr$EMPTY_N ; + // value method pcie_wr_awid + assign pcie_wr_awid = + m_pcie_wr_master_wr_in_addr$EMPTY_N && + m_pcie_wr_master_wr_in_addr$D_OUT[94] ; + // value method pcie_wr_awaddr assign pcie_wr_awaddr = m_pcie_wr_master_wr_in_addr$EMPTY_N ? @@ -1963,6 +2005,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, // value method fpga_rd_arvalid assign fpga_rd_arvalid = m_fpga_rd_master_rd_in$EMPTY_N ; + // value method fpga_rd_arid + assign fpga_rd_arid = + m_fpga_rd_master_rd_in$EMPTY_N && + m_fpga_rd_master_rd_in$D_OUT[94] ; + // value method fpga_rd_araddr assign fpga_rd_araddr = m_fpga_rd_master_rd_in$EMPTY_N ? @@ -2028,6 +2075,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, // value method fpga_wr_awvalid assign fpga_wr_awvalid = m_fpga_wr_master_wr_in_addr$EMPTY_N ; + // value method fpga_wr_awid + assign fpga_wr_awid = + m_fpga_wr_master_wr_in_addr$EMPTY_N && + m_fpga_wr_master_wr_in_addr$D_OUT[94] ; + // value method fpga_wr_awaddr assign fpga_wr_awaddr = m_fpga_wr_master_wr_in_addr$EMPTY_N ? @@ -2237,7 +2289,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .dD_OUT(fpga_response_converter$dD_OUT)); // submodule m_fpga_rd_master_rd_in - SizedFIFO #(.p1width(32'd94), + SizedFIFO #(.p1width(32'd95), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) m_fpga_rd_master_rd_in(.RST(RST_N_m32_axi_arestn), @@ -2251,7 +2303,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_fpga_rd_master_rd_in$EMPTY_N)); // submodule m_fpga_rd_master_rd_out - FIFO2 #(.width(32'd516), + FIFO2 #(.width(32'd517), .guarded(32'd1)) m_fpga_rd_master_rd_out(.RST(RST_N_m32_axi_arestn), .CLK(CLK_m32_axi_aclk), .D_IN(m_fpga_rd_master_rd_out$D_IN), @@ -2349,7 +2401,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_fpga_wr_incomingBuffer$EMPTY_N)); // submodule m_fpga_wr_master_wr_in_addr - SizedFIFO #(.p1width(32'd94), + SizedFIFO #(.p1width(32'd95), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) m_fpga_wr_master_wr_in_addr(.RST(RST_N_m32_axi_arestn), @@ -2375,7 +2427,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_fpga_wr_master_wr_in_data$EMPTY_N)); // submodule m_fpga_wr_master_wr_out - FIFO2 #(.width(32'd3), + FIFO2 #(.width(32'd4), .guarded(32'd1)) m_fpga_wr_master_wr_out(.RST(RST_N_m32_axi_arestn), .CLK(CLK_m32_axi_aclk), .D_IN(m_fpga_wr_master_wr_out$D_IN), @@ -2435,7 +2487,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_fpga_wr_reqGen_outgoingBuffer$EMPTY_N)); // submodule m_pcie_rd_master_rd_in - SizedFIFO #(.p1width(32'd94), + SizedFIFO #(.p1width(32'd95), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) m_pcie_rd_master_rd_in(.RST(RST_N_m64_axi_arestn), @@ -2449,7 +2501,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_pcie_rd_master_rd_in$EMPTY_N)); // submodule m_pcie_rd_master_rd_out - FIFO2 #(.width(32'd260), + FIFO2 #(.width(32'd261), .guarded(32'd1)) m_pcie_rd_master_rd_out(.RST(RST_N_m64_axi_arestn), .CLK(CLK_m64_axi_aclk), .D_IN(m_pcie_rd_master_rd_out$D_IN), @@ -2547,7 +2599,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_pcie_wr_incomingBuffer$EMPTY_N)); // submodule m_pcie_wr_master_wr_in_addr - SizedFIFO #(.p1width(32'd94), + SizedFIFO #(.p1width(32'd95), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) m_pcie_wr_master_wr_in_addr(.RST(RST_N_m64_axi_arestn), @@ -2573,7 +2625,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, .EMPTY_N(m_pcie_wr_master_wr_in_data$EMPTY_N)); // submodule m_pcie_wr_master_wr_out - FIFO2 #(.width(32'd3), + FIFO2 #(.width(32'd4), .guarded(32'd1)) m_pcie_wr_master_wr_out(.RST(RST_N_m64_axi_arestn), .CLK(CLK_m64_axi_aclk), .D_IN(m_pcie_wr_master_wr_out$D_IN), @@ -3063,7 +3115,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerReader_outgoing$FULL_N && !byteAlignerReader_addr_ff$dEMPTY_N && byteAlignerReader_fetchedDatum && - !byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1447 && + !byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 && !byteAlignerReader_addr_ff$dEMPTY_N ; // rule RL_byteAlignerReader_fetchNewData @@ -3071,7 +3123,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerReader_incoming$EMPTY_N && !byteAlignerReader_addr_ff$dEMPTY_N && !byteAlignerReader_fetchedDatum$port1__read && - byteAlignerReader_bytes_in_430_ULT_byteAligner_ETC___d1432 && + byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 && !byteAlignerReader_addr_ff$dEMPTY_N ; // rule RL_byteAlignerReader_forwardOutputLast @@ -3079,7 +3131,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerReader_outgoing$FULL_N && !byteAlignerReader_addr_ff$dEMPTY_N && !byteAlignerReader_fetchedDatum && - !byteAlignerReader_bytes_in_430_ULT_byteAligner_ETC___d1432 && + !byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 && byteAlignerReader_bytes_out < byteAlignerReader_bytes_total ; assign WILL_FIRE_RL_byteAlignerReader_forwardOutputLast = CAN_FIRE_RL_byteAlignerReader_forwardOutputLast && @@ -3096,7 +3148,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_outgoing$FULL_N && !byteAlignerWriter_addr_ff$dEMPTY_N && byteAlignerWriter_fetchedDatum && - !byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1569 && + !byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1577 && !byteAlignerWriter_addr_ff$dEMPTY_N ; // rule RL_byteAlignerWriter_fetchNewData @@ -3104,7 +3156,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_incoming$EMPTY_N && !byteAlignerWriter_addr_ff$dEMPTY_N && !byteAlignerWriter_fetchedDatum$port1__read && - byteAlignerWriter_bytes_in_552_ULT_byteAligner_ETC___d1554 && + byteAlignerWriter_bytes_in_560_ULT_byteAligner_ETC___d1562 && !byteAlignerWriter_addr_ff$dEMPTY_N ; // rule RL_byteAlignerWriter_forwardOutputLast @@ -3112,7 +3164,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, byteAlignerWriter_outgoing$FULL_N && !byteAlignerWriter_addr_ff$dEMPTY_N && !byteAlignerWriter_fetchedDatum && - !byteAlignerWriter_bytes_in_552_ULT_byteAligner_ETC___d1554 && + !byteAlignerWriter_bytes_in_560_ULT_byteAligner_ETC___d1562 && byteAlignerWriter_bytes_out < byteAlignerWriter_bytes_total ; assign WILL_FIRE_RL_byteAlignerWriter_forwardOutputLast = CAN_FIRE_RL_byteAlignerWriter_forwardOutputLast && @@ -3121,7 +3173,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // inputs to muxes for submodule ports assign MUX_cycles_between$write_1__SEL_1 = WILL_FIRE_RL_setInterrupt && - pc_reqCntr_491_EQ_cycles_between_set_6_BITS_11_ETC___d1673 ; + pc_reqCntr_499_EQ_cycles_between_set_6_BITS_11_ETC___d1681 ; assign MUX_opInProgress$write_1__SEL_2 = WILL_FIRE_RL_handleRead || WILL_FIRE_RL_handleWrite ; assign MUX_byteAlignerReader_buffer$port0__write_1__VAL_1 = @@ -3208,49 +3260,49 @@ module mkBlueDMA(CLK_m32_axi_aclk, cycles_last_request[7:0] } ; assign MUX_m_fpga_rd_task_data_output_reg$write_1__VAL_1 = { m_fpga_rd_task_data_output_reg[76:65], - x_transfers_total__h58356, + x_transfers_total__h58416, m_fpga_rd_task_data_output_reg[6:0] } ; assign MUX_m_fpga_rd_task_data_requests_reg$write_1__VAL_1 = { m_fpga_rd_task_data_requests_reg[133:126], - x_requests_total__h57906, - x_address__h57907, + x_requests_total__h57966, + x_address__h57967, m_fpga_rd_task_data_requests_reg[3:0] } ; assign MUX_m_fpga_wr_beatsThisRequestCntr$write_1__VAL_1 = - m_fpga_wr_beatsThisRequestCntr_21_EQ_m_fpga_wr_ETC___d923 ? + m_fpga_wr_beatsThisRequestCntr_27_EQ_m_fpga_wr_ETC___d929 ? 8'd0 : - beatsThisRequestCntrT__h43762 ; + beatsThisRequestCntrT__h43807 ; assign MUX_m_fpga_wr_task_data_output_reg$write_1__VAL_1 = { m_fpga_wr_task_data_output_reg[76:65], - x_transfers_total__h54794, + x_transfers_total__h54839, m_fpga_wr_task_data_output_reg[6:1], 1'd0 } ; assign MUX_m_fpga_wr_task_data_requests_reg$write_1__VAL_1 = { m_fpga_wr_task_data_requests_reg[133:126], - x_requests_total__h43359, - x_address__h43360, + x_requests_total__h43404, + x_address__h43405, m_fpga_wr_task_data_requests_reg[3:0] } ; assign MUX_m_pcie_rd_task_data_output_reg$write_1__VAL_1 = { m_pcie_rd_task_data_output_reg[74:65], - x_transfers_total__h39153, + x_transfers_total__h39183, m_pcie_rd_task_data_output_reg[5:0] } ; assign MUX_m_pcie_rd_task_data_requests_reg$write_1__VAL_1 = { m_pcie_rd_task_data_requests_reg[134:127], - x_requests_total__h38703, - x_address__h38704, + x_requests_total__h38733, + x_address__h38734, m_pcie_rd_task_data_requests_reg[3:0] } ; assign MUX_m_pcie_wr_beatsThisRequestCntr$write_1__VAL_1 = - m_pcie_wr_beatsThisRequestCntr_40_EQ_m_pcie_wr_ETC___d442 ? + m_pcie_wr_beatsThisRequestCntr_42_EQ_m_pcie_wr_ETC___d444 ? 8'd0 : - beatsThisRequestCntrT__h29964 ; + beatsThisRequestCntrT__h29979 ; assign MUX_m_pcie_wr_task_data_output_reg$write_1__VAL_1 = { m_pcie_wr_task_data_output_reg[74:65], - x_transfers_total__h35588, + x_transfers_total__h35603, m_pcie_wr_task_data_output_reg[5:1], 1'd0 } ; assign MUX_m_pcie_wr_task_data_requests_reg$write_1__VAL_1 = { m_pcie_wr_task_data_requests_reg[134:127], - x_requests_total__h29561, - x_address__h29562, + x_requests_total__h29576, + x_address__h29577, m_pcie_wr_task_data_requests_reg[3:0] } ; assign MUX_readConverter_byteCntr$write_1__VAL_2 = readConverter_byteCntr - 64'd32 ; @@ -3330,12 +3382,22 @@ module mkBlueDMA(CLK_m32_axi_aclk, default: m_fpga_rd_master_rd_warcache$wget = 4'd11; endcase end - assign m_pcie_wr_master_wr_rinpkg$wget = { pcie_wr_bresp, pcie_wr_buser } ; + assign m_pcie_wr_master_wr_rinpkg$wget = + { pcie_wr_bid, pcie_wr_bresp, pcie_wr_buser } ; assign m_pcie_rd_master_rd_rinpkg$wget = - { pcie_rd_rdata, pcie_rd_rresp, pcie_rd_rlast, pcie_rd_ruser } ; - assign m_fpga_wr_master_wr_rinpkg$wget = { fpga_wr_bresp, fpga_wr_buser } ; + { pcie_rd_rid, + pcie_rd_rdata, + pcie_rd_rresp, + pcie_rd_rlast, + pcie_rd_ruser } ; + assign m_fpga_wr_master_wr_rinpkg$wget = + { fpga_wr_bid, fpga_wr_bresp, fpga_wr_buser } ; assign m_fpga_rd_master_rd_rinpkg$wget = - { fpga_rd_rdata, fpga_rd_rresp, fpga_rd_rlast, fpga_rd_ruser } ; + { fpga_rd_rid, + fpga_rd_rdata, + fpga_rd_rresp, + fpga_rd_rlast, + fpga_rd_ruser } ; assign s_config_writeSlave_addrIn_rv$EN_port0__write = !s_config_writeSlave_addrIn_rv[67] && S_AXI_awvalid ; assign s_config_writeSlave_addrIn_rv$port0__write_1 = @@ -3429,16 +3491,16 @@ module mkBlueDMA(CLK_m32_axi_aclk, MUX_byteAlignerReader_bytes_left_in_buffer$port0__write_1__VAL_1 : 6'd0 ; assign byteAlignerReader_bytes_left_in_buffer$port1__write_1 = - b__h72232 + 6'd32 ; + b__h72292 + 6'd32 ; assign byteAlignerReader_bytes_left_in_buffer$port2__read = WILL_FIRE_RL_byteAlignerReader_fetchNewData ? byteAlignerReader_bytes_left_in_buffer$port1__write_1 : - b__h72232 ; + b__h72292 ; assign byteAlignerReader_fetchedDatum$EN_port0__write = byteAlignerReader_addr_ff$dEMPTY_N || !byteAlignerReader_addr_ff$dEMPTY_N && byteAlignerReader_fetchedDatum && - byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1447 || + byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 || WILL_FIRE_RL_byteAlignerReader_forwardOutput ; assign byteAlignerReader_fetchedDatum$port1__read = !byteAlignerReader_fetchedDatum$EN_port0__write && @@ -3472,16 +3534,16 @@ module mkBlueDMA(CLK_m32_axi_aclk, MUX_byteAlignerWriter_bytes_left_in_buffer$port0__write_1__VAL_1 : 6'd0 ; assign byteAlignerWriter_bytes_left_in_buffer$port1__write_1 = - b__h115415 + 6'd32 ; + b__h115475 + 6'd32 ; assign byteAlignerWriter_bytes_left_in_buffer$port2__read = WILL_FIRE_RL_byteAlignerWriter_fetchNewData ? byteAlignerWriter_bytes_left_in_buffer$port1__write_1 : - b__h115415 ; + b__h115475 ; assign byteAlignerWriter_fetchedDatum$EN_port0__write = byteAlignerWriter_addr_ff$dEMPTY_N || !byteAlignerWriter_addr_ff$dEMPTY_N && byteAlignerWriter_fetchedDatum && - byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1569 || + byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1577 || WILL_FIRE_RL_byteAlignerWriter_forwardOutput ; assign byteAlignerWriter_fetchedDatum$port1__read = !byteAlignerWriter_fetchedDatum$EN_port0__write && @@ -3629,7 +3691,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, MUX_cycles_between$write_1__VAL_2 ; assign cycles_between$EN = WILL_FIRE_RL_setInterrupt && - pc_reqCntr_491_EQ_cycles_between_set_6_BITS_11_ETC___d1673 || + pc_reqCntr_499_EQ_cycles_between_set_6_BITS_11_ETC___d1681 || WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 ; // register cycles_between_set @@ -3912,7 +3974,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // register pc_reqCntr assign pc_reqCntr$D_IN = - pc_reqCntr_491_EQ_cycles_between_set_6_BITS_11_ETC___d1673 ? + pc_reqCntr_499_EQ_cycles_between_set_6_BITS_11_ETC___d1681 ? 12'd0 : pc_reqCntr + 12'd1 ; assign pc_reqCntr$EN = WILL_FIRE_RL_setInterrupt ; @@ -4090,7 +4152,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign fpgaDone$sD_IN = 1'd1 ; assign fpgaDone$sENQ = fpgaDone$sFULL_N && - fpgaLastCycle_662_AND_m_fpga_rd_task_data_outp_ETC___d1664 ; + fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672 ; assign fpgaDone$dDEQ = WILL_FIRE_RL_setInterrupt ; // submodule fpga_request_converter @@ -4111,10 +4173,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_rd_master_rd_in assign m_fpga_rd_master_rd_in$D_IN = - { m_fpga_rd_task_data_requests_reg[67:4], + { 1'd0, + m_fpga_rd_task_data_requests_reg[67:4], (m_fpga_rd_task_data_requests_reg[125:68] == 58'd1 && m_fpga_rd_task_data_requests_reg[133:126] != 8'd0) ? - beatsThisRequest___1__h57878 : + beatsThisRequest___1__h57938 : 8'd255, 17'd102784, m_fpga_rd_task_data_requests_reg[3:0], @@ -4153,7 +4216,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_rd_reqGen_intermediateBuffer assign m_fpga_rd_reqGen_intermediateBuffer$D_IN = - { x__h55481[5:0], + { x__h55526[5:0], m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6[5:0], m_fpga_rd_reqGen_incomingBuffer$D_OUT } ; assign m_fpga_rd_reqGen_intermediateBuffer$ENQ = @@ -4167,7 +4230,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_rd_reqGen_intermediateBuffer2 assign m_fpga_rd_reqGen_intermediateBuffer2$D_IN = { m_fpga_rd_reqGen_intermediateBuffer$D_OUT[143:132], - x__h55662[57:0], + x__h55707[57:0], m_fpga_rd_reqGen_intermediateBuffer$D_OUT[131:0] } ; assign m_fpga_rd_reqGen_intermediateBuffer2$ENQ = m_fpga_rd_reqGen_intermediateBuffer$EMPTY_N && @@ -4179,8 +4242,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_rd_reqGen_outgoingBuffer assign m_fpga_rd_reqGen_outgoingBuffer$D_IN = { m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[139:132], - request_data_requests_total__h55799, - request_data_address__h55800, + request_data_requests_total__h55844, + request_data_address__h55845, m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[3:0], m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[201:132], m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[73:68], @@ -4192,12 +4255,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_fpga_rd_reqGen_outgoingBuffer$CLR = 1'b0 ; // submodule m_fpga_wr_beatsPerRequestFIFO - assign m_fpga_wr_beatsPerRequestFIFO$D_IN = _theResult____h43254 ; + assign m_fpga_wr_beatsPerRequestFIFO$D_IN = _theResult____h43299 ; assign m_fpga_wr_beatsPerRequestFIFO$ENQ = WILL_FIRE_RL_m_fpga_wr_placeRequest ; assign m_fpga_wr_beatsPerRequestFIFO$DEQ = WILL_FIRE_RL_m_fpga_wr_forwardData && - m_fpga_wr_beatsThisRequestCntr_21_EQ_m_fpga_wr_ETC___d923 ; + m_fpga_wr_beatsThisRequestCntr_27_EQ_m_fpga_wr_ETC___d929 ; assign m_fpga_wr_beatsPerRequestFIFO$CLR = 1'b0 ; // submodule m_fpga_wr_incomingBuffer @@ -4210,8 +4273,9 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_master_wr_in_addr assign m_fpga_wr_master_wr_in_addr$D_IN = - { m_fpga_wr_task_data_requests_reg[67:4], - _theResult____h43254, + { 1'd0, + m_fpga_wr_task_data_requests_reg[67:4], + _theResult____h43299, 17'd102784, m_fpga_wr_task_data_requests_reg[3:0], 1'd0 } ; @@ -4224,8 +4288,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_master_wr_in_data assign m_fpga_wr_master_wr_in_data$D_IN = { m_fpga_wr_incomingBuffer$D_OUT, - x_strb__h43876, - m_fpga_wr_beatsThisRequestCntr_21_EQ_m_fpga_wr_ETC___d923, + x_strb__h43921, + m_fpga_wr_beatsThisRequestCntr_27_EQ_m_fpga_wr_ETC___d929, 1'd0 } ; assign m_fpga_wr_master_wr_in_data$ENQ = WILL_FIRE_RL_m_fpga_wr_forwardData ; @@ -4253,7 +4317,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_reqGen_intermediateBuffer assign m_fpga_wr_reqGen_intermediateBuffer$D_IN = - { x__h40149[5:0], + { x__h40179[5:0], m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7[5:0], m_fpga_wr_reqGen_incomingBuffer$D_OUT } ; assign m_fpga_wr_reqGen_intermediateBuffer$ENQ = @@ -4267,7 +4331,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_reqGen_intermediateBuffer2 assign m_fpga_wr_reqGen_intermediateBuffer2$D_IN = { m_fpga_wr_reqGen_intermediateBuffer$D_OUT[143:132], - x__h40330[57:0], + x__h40360[57:0], m_fpga_wr_reqGen_intermediateBuffer$D_OUT[131:0] } ; assign m_fpga_wr_reqGen_intermediateBuffer2$ENQ = m_fpga_wr_reqGen_intermediateBuffer$EMPTY_N && @@ -4279,8 +4343,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_fpga_wr_reqGen_outgoingBuffer assign m_fpga_wr_reqGen_outgoingBuffer$D_IN = { m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[139:132], - request_data_requests_total__h40467, - request_data_address__h40468, + request_data_requests_total__h40497, + request_data_address__h40498, m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[3:0], m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[201:132], m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[73:68], @@ -4293,10 +4357,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_master_rd_in assign m_pcie_rd_master_rd_in$D_IN = - { m_pcie_rd_task_data_requests_reg[67:4], + { 1'd0, + m_pcie_rd_task_data_requests_reg[67:4], (m_pcie_rd_task_data_requests_reg[126:68] == 59'd1 && m_pcie_rd_task_data_requests_reg[134:127] != 8'd0) ? - beatsThisRequest___1__h38675 : + beatsThisRequest___1__h38705 : 8'd63, 17'd86400, m_pcie_rd_task_data_requests_reg[3:0], @@ -4333,7 +4398,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_reqGen_intermediateBuffer assign m_pcie_rd_reqGen_intermediateBuffer$D_IN = - { x__h36275[4:0], + { x__h36290[4:0], m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8[4:0], m_pcie_rd_reqGen_incomingBuffer$D_OUT } ; assign m_pcie_rd_reqGen_intermediateBuffer$ENQ = @@ -4347,7 +4412,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_reqGen_intermediateBuffer2 assign m_pcie_rd_reqGen_intermediateBuffer2$D_IN = { m_pcie_rd_reqGen_intermediateBuffer$D_OUT[141:132], - x__h36456[58:0], + x__h36471[58:0], m_pcie_rd_reqGen_intermediateBuffer$D_OUT[131:0] } ; assign m_pcie_rd_reqGen_intermediateBuffer2$ENQ = m_pcie_rd_reqGen_intermediateBuffer$EMPTY_N && @@ -4358,9 +4423,9 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_rd_reqGen_outgoingBuffer assign m_pcie_rd_reqGen_outgoingBuffer$D_IN = - { requests_last__h36556, - request_data_requests_total__h36593, - request_data_address__h36594, + { requests_last__h36571, + request_data_requests_total__h36608, + request_data_address__h36609, m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[3:0], m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[200:132], m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[72:68], @@ -4372,12 +4437,12 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign m_pcie_rd_reqGen_outgoingBuffer$CLR = 1'b0 ; // submodule m_pcie_wr_beatsPerRequestFIFO - assign m_pcie_wr_beatsPerRequestFIFO$D_IN = _theResult____h29456 ; + assign m_pcie_wr_beatsPerRequestFIFO$D_IN = _theResult____h29471 ; assign m_pcie_wr_beatsPerRequestFIFO$ENQ = WILL_FIRE_RL_m_pcie_wr_placeRequest ; assign m_pcie_wr_beatsPerRequestFIFO$DEQ = WILL_FIRE_RL_m_pcie_wr_forwardData && - m_pcie_wr_beatsThisRequestCntr_40_EQ_m_pcie_wr_ETC___d442 ; + m_pcie_wr_beatsThisRequestCntr_42_EQ_m_pcie_wr_ETC___d444 ; assign m_pcie_wr_beatsPerRequestFIFO$CLR = 1'b0 ; // submodule m_pcie_wr_incomingBuffer @@ -4394,8 +4459,9 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_wr_master_wr_in_addr assign m_pcie_wr_master_wr_in_addr$D_IN = - { m_pcie_wr_task_data_requests_reg[67:4], - _theResult____h29456, + { 1'd0, + m_pcie_wr_task_data_requests_reg[67:4], + _theResult____h29471, 17'd86400, m_pcie_wr_task_data_requests_reg[3:0], 1'd0 } ; @@ -4408,8 +4474,8 @@ module mkBlueDMA(CLK_m32_axi_aclk, // submodule m_pcie_wr_master_wr_in_data assign m_pcie_wr_master_wr_in_data$D_IN = { m_pcie_wr_incomingBuffer$D_OUT, - x_strb__h30078, - m_pcie_wr_beatsThisRequestCntr_40_EQ_m_pcie_wr_ETC___d442, + x_strb__h30093, + m_pcie_wr_beatsThisRequestCntr_42_EQ_m_pcie_wr_ETC___d444, 1'd0 } ; assign m_pcie_wr_master_wr_in_data$ENQ = WILL_FIRE_RL_m_pcie_wr_forwardData ; @@ -4509,11 +4575,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign pcieDone$sD_IN = 1'd1 ; assign pcieDone$sENQ = pcieDone$sFULL_N && - pcieLastCycle_655_AND_m_pcie_rd_task_data_outp_ETC___d1657 ; + pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665 ; assign pcieDone$dDEQ = WILL_FIRE_RL_setInterrupt ; // submodule readConvBTT_ff - assign readConvBTT_ff$sD_IN = { btt__h102029, readIn_rv[69] } ; + assign readConvBTT_ff$sD_IN = { btt__h102089, readIn_rv[69] } ; assign readConvBTT_ff$sENQ = WILL_FIRE_RL_handleRead ; assign readConvBTT_ff$dDEQ = readConvBTT_ff$dEMPTY_N ; @@ -4640,7 +4706,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, assign s_config_writeSlave_out$CLR = 1'b0 ; // submodule writeConvBTT_ff - assign writeConvBTT_ff$sD_IN = { btt__h145135, writeIn_rv[69] } ; + assign writeConvBTT_ff$sD_IN = { btt__h145195, writeIn_rv[69] } ; assign writeConvBTT_ff$sENQ = WILL_FIRE_RL_handleWrite ; assign writeConvBTT_ff$dDEQ = writeConvBTT_ff$dEMPTY_N ; @@ -4667,23 +4733,23 @@ module mkBlueDMA(CLK_m32_axi_aclk, readConverter_byteCntr <= 64'd32) ? 2'd0 : { 1'd0, readConverter_wordInCntr } + 2'd1 ; - assign IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 = + assign IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 = (m_fpga_wr_task_data_output_reg[0] && m_fpga_wr_task_data_output_reg[76:71] != 6'd0) ? - endByte___1__h46785 : + endByte___1__h46830 : ((m_fpga_wr_task_data_output_reg[64:7] == 58'd1) ? ((m_fpga_wr_task_data_output_reg[70:65] == 6'd0) ? 7'd64 : - endByte___1__h46811) : + endByte___1__h46856) : 7'd64) ; - assign IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 = + assign IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 = (m_pcie_wr_task_data_output_reg[0] && m_pcie_wr_task_data_output_reg[74:70] != 5'd0) ? - endByte___1__h31579 : + endByte___1__h31594 : ((m_pcie_wr_task_data_output_reg[64:6] == 59'd1) ? ((m_pcie_wr_task_data_output_reg[69:65] == 5'd0) ? 6'd32 : - endByte___1__h31605) : + endByte___1__h31620) : 6'd32) ; assign _theResult____h26331 = (m_pcie_wr_reqGen_incomingBuffer$D_OUT[72:68] == 5'd0) ? @@ -4693,176 +4759,176 @@ module mkBlueDMA(CLK_m32_axi_aclk, (m_pcie_wr_reqGen_intermediateBuffer$D_OUT[141:137] == 5'd0) ? transfers_total__h26514 : transfers_total___1__h26523 ; - assign _theResult____h29456 = + assign _theResult____h29471 = (m_pcie_wr_task_data_requests_reg[126:68] == 59'd1 && m_pcie_wr_task_data_requests_reg[134:127] != 8'd0) ? - beatsThisRequest___1__h29504 : + beatsThisRequest___1__h29519 : 8'd63 ; - assign _theResult____h36270 = + assign _theResult____h36285 = (m_pcie_rd_reqGen_incomingBuffer$D_OUT[72:68] == 5'd0) ? - bytes_first__h36269 : - bytes_first___1__h36305 ; - assign _theResult____h36454 = + bytes_first__h36284 : + bytes_first___1__h36320 ; + assign _theResult____h36469 = (m_pcie_rd_reqGen_intermediateBuffer$D_OUT[141:137] == 5'd0) ? - transfers_total__h36453 : - transfers_total___1__h36462 ; - assign _theResult____h40144 = + transfers_total__h36468 : + transfers_total___1__h36477 ; + assign _theResult____h40174 = (m_fpga_wr_reqGen_incomingBuffer$D_OUT[73:68] == 6'd0) ? - bytes_first__h40143 : - bytes_first___1__h40179 ; - assign _theResult____h40328 = + bytes_first__h40173 : + bytes_first___1__h40209 ; + assign _theResult____h40358 = (m_fpga_wr_reqGen_intermediateBuffer$D_OUT[143:138] == 6'd0) ? - transfers_total__h40327 : - transfers_total___1__h40336 ; - assign _theResult____h43254 = + transfers_total__h40357 : + transfers_total___1__h40366 ; + assign _theResult____h43299 = (m_fpga_wr_task_data_requests_reg[125:68] == 58'd1 && m_fpga_wr_task_data_requests_reg[133:126] != 8'd0) ? - beatsThisRequest___1__h43302 : + beatsThisRequest___1__h43347 : 8'd255 ; - assign _theResult____h55476 = + assign _theResult____h55521 = (m_fpga_rd_reqGen_incomingBuffer$D_OUT[73:68] == 6'd0) ? - bytes_first__h55475 : - bytes_first___1__h55511 ; - assign _theResult____h55660 = + bytes_first__h55520 : + bytes_first___1__h55556 ; + assign _theResult____h55705 = (m_fpga_rd_reqGen_intermediateBuffer$D_OUT[143:138] == 6'd0) ? - transfers_total__h55659 : - transfers_total___1__h55668 ; - assign b__h115415 = + transfers_total__h55704 : + transfers_total___1__h55713 ; + assign b__h115475 = byteAlignerWriter_bytes_left_in_buffer$EN_port0__write ? byteAlignerWriter_bytes_left_in_buffer$port0__write_1 : byteAlignerWriter_bytes_left_in_buffer ; - assign b__h72232 = + assign b__h72292 = byteAlignerReader_bytes_left_in_buffer$EN_port0__write ? byteAlignerReader_bytes_left_in_buffer$port0__write_1 : byteAlignerReader_bytes_left_in_buffer ; - assign beatsThisRequestCntrT__h29964 = + assign beatsThisRequestCntrT__h29979 = m_pcie_wr_beatsThisRequestCntr + 8'd1 ; - assign beatsThisRequestCntrT__h43762 = + assign beatsThisRequestCntrT__h43807 = m_fpga_wr_beatsThisRequestCntr + 8'd1 ; - assign beatsThisRequest___1__h29504 = + assign beatsThisRequest___1__h29519 = m_pcie_wr_task_data_requests_reg[134:127] - 8'd1 ; - assign beatsThisRequest___1__h38675 = + assign beatsThisRequest___1__h38705 = m_pcie_rd_task_data_requests_reg[134:127] - 8'd1 ; - assign beatsThisRequest___1__h43302 = + assign beatsThisRequest___1__h43347 = m_fpga_wr_task_data_requests_reg[133:126] - 8'd1 ; - assign beatsThisRequest___1__h57878 = + assign beatsThisRequest___1__h57938 = m_fpga_rd_task_data_requests_reg[133:126] - 8'd1 ; - assign btt__h102029 = readIn_rv[63:0] + y__h102066 ; - assign btt__h145135 = writeIn_rv[63:0] + y__h145163 ; - assign byteAlignerReader_bytes_in_430_ULT_byteAligner_ETC___d1432 = + assign btt__h102089 = readIn_rv[63:0] + y__h102126 ; + assign btt__h145195 = writeIn_rv[63:0] + y__h145223 ; + assign byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 = byteAlignerReader_bytes_in < byteAlignerReader_bytes_total ; - assign byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1447 = + assign byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 = byteAlignerReader_bytes_left_in_buffer < byteAlignerReader_bytes_out_needed ; - assign byteAlignerWriter_bytes_in_552_ULT_byteAligner_ETC___d1554 = + assign byteAlignerWriter_bytes_in_560_ULT_byteAligner_ETC___d1562 = byteAlignerWriter_bytes_in < byteAlignerWriter_bytes_total ; - assign byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1569 = + assign byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1577 = byteAlignerWriter_bytes_left_in_buffer < byteAlignerWriter_bytes_out_needed ; assign bytes_first___1__h26366 = 64'd32 - bytes_first__h26330 ; - assign bytes_first___1__h36305 = 64'd32 - bytes_first__h36269 ; - assign bytes_first___1__h40179 = 64'd64 - bytes_first__h40143 ; - assign bytes_first___1__h55511 = 64'd64 - bytes_first__h55475 ; + assign bytes_first___1__h36320 = 64'd32 - bytes_first__h36284 ; + assign bytes_first___1__h40209 = 64'd64 - bytes_first__h40173 ; + assign bytes_first___1__h55556 = 64'd64 - bytes_first__h55520 ; assign bytes_first__h26330 = { 59'd0, m_pcie_wr_reqGen_incomingBuffer$D_OUT[72:68] } ; - assign bytes_first__h36269 = + assign bytes_first__h36284 = { 59'd0, m_pcie_rd_reqGen_incomingBuffer$D_OUT[72:68] } ; - assign bytes_first__h40143 = + assign bytes_first__h40173 = { 58'd0, m_fpga_wr_reqGen_incomingBuffer$D_OUT[73:68] } ; - assign bytes_first__h55475 = + assign bytes_first__h55520 = { 58'd0, m_fpga_rd_reqGen_incomingBuffer$D_OUT[73:68] } ; - assign endByte___1__h31579 = - startByte___1__h31578 + + assign endByte___1__h31594 = + startByte___1__h31593 + { 1'd0, m_pcie_wr_task_data_output_reg[74:70] } ; - assign endByte___1__h31605 = + assign endByte___1__h31620 = { 1'd0, m_pcie_wr_task_data_output_reg[69:65] } ; - assign endByte___1__h46785 = - startByte___1__h46784 + + assign endByte___1__h46830 = + startByte___1__h46829 + { 1'd0, m_fpga_wr_task_data_output_reg[76:71] } ; - assign endByte___1__h46811 = + assign endByte___1__h46856 = { 1'd0, m_fpga_wr_task_data_output_reg[70:65] } ; - assign fpgaLastCycle_662_AND_m_fpga_rd_task_data_outp_ETC___d1664 = + assign fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672 = fpgaLastCycle && m_fpga_rd_task_data_output_reg[64:7] == 58'd0 && m_fpga_rd_task_data_requests_reg[125:68] == 58'd0 && m_fpga_wr_task_data_output_reg[64:7] == 58'd0 && m_fpga_wr_task_data_requests_reg[125:68] == 58'd0 ; assign m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6 = - m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h55555 ; - assign m_fpga_wr_beatsThisRequestCntr_21_EQ_m_fpga_wr_ETC___d923 = + m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h55600 ; + assign m_fpga_wr_beatsThisRequestCntr_27_EQ_m_fpga_wr_ETC___d929 = m_fpga_wr_beatsThisRequestCntr == m_fpga_wr_beatsPerRequestFIFO$D_OUT ; assign m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7 = - m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h40223 ; + m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h40253 ; assign m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8 = - m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h36349 ; - assign m_pcie_wr_beatsThisRequestCntr_40_EQ_m_pcie_wr_ETC___d442 = + m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h36364 ; + assign m_pcie_wr_beatsThisRequestCntr_42_EQ_m_pcie_wr_ETC___d444 = m_pcie_wr_beatsThisRequestCntr == m_pcie_wr_beatsPerRequestFIFO$D_OUT ; assign m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9 = m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h26410 ; - assign pc_reqCntr_491_EQ_cycles_between_set_6_BITS_11_ETC___d1673 = + assign pc_reqCntr_499_EQ_cycles_between_set_6_BITS_11_ETC___d1681 = pc_reqCntr == cycles_between_set[11:0] ; - assign pcieLastCycle_655_AND_m_pcie_rd_task_data_outp_ETC___d1657 = + assign pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665 = pcieLastCycle && m_pcie_rd_task_data_output_reg[64:6] == 59'd0 && m_pcie_rd_task_data_requests_reg[126:68] == 59'd0 && m_pcie_wr_task_data_output_reg[64:6] == 59'd0 && m_pcie_wr_task_data_requests_reg[126:68] == 59'd0 ; assign request_data_address__h26655 = { m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[131:73], 5'd0 } ; - assign request_data_address__h36594 = + assign request_data_address__h36609 = { m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[131:73], 5'd0 } ; - assign request_data_address__h40468 = + assign request_data_address__h40498 = { m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[131:74], 6'd0 } ; - assign request_data_address__h55800 = + assign request_data_address__h55845 = { m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[131:74], 6'd0 } ; assign request_data_requests_total__h26654 = (m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[137:132] == 6'd0) ? requests_total__h26618 : requests_total___1__h26680 ; - assign request_data_requests_total__h36593 = + assign request_data_requests_total__h36608 = (m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[137:132] == 6'd0) ? - requests_total__h36557 : - requests_total___1__h36619 ; - assign request_data_requests_total__h40467 = + requests_total__h36572 : + requests_total___1__h36634 ; + assign request_data_requests_total__h40497 = (m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[139:132] == 8'd0) ? - requests_total__h40431 : - requests_total___1__h40493 ; - assign request_data_requests_total__h55799 = + requests_total__h40461 : + requests_total___1__h40523 ; + assign request_data_requests_total__h55844 = (m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[139:132] == 8'd0) ? - requests_total__h55763 : - requests_total___1__h55825 ; + requests_total__h55808 : + requests_total___1__h55870 ; assign requests_last__h26617 = { 2'd0, m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[137:132] } ; - assign requests_last__h36556 = + assign requests_last__h36571 = { 2'd0, m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[137:132] } ; assign requests_total___1__h26680 = requests_total__h26618 + 59'd1 ; - assign requests_total___1__h36619 = requests_total__h36557 + 59'd1 ; - assign requests_total___1__h40493 = requests_total__h40431 + 58'd1 ; - assign requests_total___1__h55825 = requests_total__h55763 + 58'd1 ; + assign requests_total___1__h36634 = requests_total__h36572 + 59'd1 ; + assign requests_total___1__h40523 = requests_total__h40461 + 58'd1 ; + assign requests_total___1__h55870 = requests_total__h55808 + 58'd1 ; assign requests_total__h26618 = m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[190:132] >> 6 ; - assign requests_total__h36557 = + assign requests_total__h36572 = m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[190:132] >> 6 ; - assign requests_total__h40431 = + assign requests_total__h40461 = m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[189:132] >> 8 ; - assign requests_total__h55763 = + assign requests_total__h55808 = m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[189:132] >> 8 ; - assign startByte___1__h31578 = + assign startByte___1__h31593 = { 1'd0, m_pcie_wr_task_data_output_reg[5:1] } ; - assign startByte___1__h46784 = + assign startByte___1__h46829 = { 1'd0, m_fpga_wr_task_data_output_reg[6:1] } ; assign transfers_total___1__h26523 = transfers_total__h26514 + 64'd1 ; - assign transfers_total___1__h36462 = transfers_total__h36453 + 64'd1 ; - assign transfers_total___1__h40336 = transfers_total__h40327 + 64'd1 ; - assign transfers_total___1__h55668 = transfers_total__h55659 + 64'd1 ; + assign transfers_total___1__h36477 = transfers_total__h36468 + 64'd1 ; + assign transfers_total___1__h40366 = transfers_total__h40357 + 64'd1 ; + assign transfers_total___1__h55713 = transfers_total__h55704 + 64'd1 ; assign transfers_total__h26514 = (x__h26543 - y__h26544) >> 5 ; assign transfers_total__h26520 = _theResult____h26515 + 64'd1 ; - assign transfers_total__h36453 = (x__h36482 - y__h36483) >> 5 ; - assign transfers_total__h36459 = _theResult____h36454 + 64'd1 ; - assign transfers_total__h40327 = (x__h40356 - y__h40357) >> 6 ; - assign transfers_total__h40333 = _theResult____h40328 + 64'd1 ; - assign transfers_total__h55659 = (x__h55688 - y__h55689) >> 6 ; - assign transfers_total__h55665 = _theResult____h55660 + 64'd1 ; + assign transfers_total__h36468 = (x__h36497 - y__h36498) >> 5 ; + assign transfers_total__h36474 = _theResult____h36469 + 64'd1 ; + assign transfers_total__h40357 = (x__h40386 - y__h40387) >> 6 ; + assign transfers_total__h40363 = _theResult____h40358 + 64'd1 ; + assign transfers_total__h55704 = (x__h55733 - y__h55734) >> 6 ; + assign transfers_total__h55710 = _theResult____h55705 + 64'd1 ; assign x__h26336 = (m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] < _theResult____h26331 || @@ -4876,390 +4942,390 @@ module mkBlueDMA(CLK_m32_axi_aclk, transfers_total__h26520 ; assign x__h26543 = m_pcie_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h26546 ; - assign x__h31565 = + assign x__h31580 = (m_pcie_wr_task_data_output_reg[0] && m_pcie_wr_task_data_output_reg[74:70] != 5'd0) ? - startByte___1__h31578 : + startByte___1__h31593 : 6'd0 ; - assign x__h36275 = + assign x__h36290 = (m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] < - _theResult____h36270 || - _theResult____h36270 == 64'd0 && + _theResult____h36285 || + _theResult____h36285 == 64'd0 && m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] < 64'd32) ? m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] : - _theResult____h36270 ; - assign x__h36456 = + _theResult____h36285 ; + assign x__h36471 = (m_pcie_rd_reqGen_intermediateBuffer$D_OUT[136:132] == 5'd0) ? - _theResult____h36454 : - transfers_total__h36459 ; - assign x__h36482 = - m_pcie_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h36485 ; - assign x__h40149 = + _theResult____h36469 : + transfers_total__h36474 ; + assign x__h36497 = + m_pcie_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h36500 ; + assign x__h40179 = (m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] < - _theResult____h40144 || - _theResult____h40144 == 64'd0 && + _theResult____h40174 || + _theResult____h40174 == 64'd0 && m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] < 64'd64) ? m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] : - _theResult____h40144 ; - assign x__h40330 = + _theResult____h40174 ; + assign x__h40360 = (m_fpga_wr_reqGen_intermediateBuffer$D_OUT[137:132] == 6'd0) ? - _theResult____h40328 : - transfers_total__h40333 ; - assign x__h40356 = - m_fpga_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h40359 ; - assign x__h46771 = + _theResult____h40358 : + transfers_total__h40363 ; + assign x__h40386 = + m_fpga_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h40389 ; + assign x__h46816 = (m_fpga_wr_task_data_output_reg[0] && m_fpga_wr_task_data_output_reg[76:71] != 6'd0) ? - startByte___1__h46784 : + startByte___1__h46829 : 7'd0 ; - assign x__h55481 = + assign x__h55526 = (m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] < - _theResult____h55476 || - _theResult____h55476 == 64'd0 && + _theResult____h55521 || + _theResult____h55521 == 64'd0 && m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] < 64'd64) ? m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] : - _theResult____h55476 ; - assign x__h55662 = + _theResult____h55521 ; + assign x__h55707 = (m_fpga_rd_reqGen_intermediateBuffer$D_OUT[137:132] == 6'd0) ? - _theResult____h55660 : - transfers_total__h55665 ; - assign x__h55688 = - m_fpga_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h55691 ; - assign x_address__h29562 = + _theResult____h55705 : + transfers_total__h55710 ; + assign x__h55733 = + m_fpga_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h55736 ; + assign x_address__h29577 = m_pcie_wr_task_data_requests_reg[67:4] + 64'd2048 ; - assign x_address__h38704 = + assign x_address__h38734 = m_pcie_rd_task_data_requests_reg[67:4] + 64'd2048 ; - assign x_address__h43360 = + assign x_address__h43405 = m_fpga_wr_task_data_requests_reg[67:4] + 64'd16384 ; - assign x_address__h57907 = + assign x_address__h57967 = m_fpga_rd_task_data_requests_reg[67:4] + 64'd16384 ; - assign x_requests_total__h29561 = + assign x_requests_total__h29576 = m_pcie_wr_task_data_requests_reg[126:68] - 59'd1 ; - assign x_requests_total__h38703 = + assign x_requests_total__h38733 = m_pcie_rd_task_data_requests_reg[126:68] - 59'd1 ; - assign x_requests_total__h43359 = + assign x_requests_total__h43404 = m_fpga_wr_task_data_requests_reg[125:68] - 58'd1 ; - assign x_requests_total__h57906 = + assign x_requests_total__h57966 = m_fpga_rd_task_data_requests_reg[125:68] - 58'd1 ; - assign x_strb__h30078 = - { x__h31565 <= 6'd31 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + assign x_strb__h30093 = + { x__h31580 <= 6'd31 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd31, - x__h31565 <= 6'd30 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd30 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd30, - x__h31565 <= 6'd29 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd29 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd29, - x__h31565 <= 6'd28 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd28 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd28, - x__h31565 <= 6'd27 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd27 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd27, - x__h31565 <= 6'd26 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd26 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd26, - x__h31565 <= 6'd25 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd25 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd25, - x__h31565 <= 6'd24 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd24 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd24, - x__h31565 <= 6'd23 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd23 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd23, - x__h31565 <= 6'd22 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd22 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd22, - x__h31565 <= 6'd21 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd21 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd21, - x__h31565 <= 6'd20 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd20 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd20, - x__h31565 <= 6'd19 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd19 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd19, - x__h31565 <= 6'd18 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd18 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd18, - x__h31565 <= 6'd17 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd17 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd17, - x__h31565 <= 6'd16 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd16 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd16, - x__h31565 <= 6'd15 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd15 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd15, - x__h31565 <= 6'd14 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd14 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd14, - x__h31565 <= 6'd13 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd13 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd13, - x__h31565 <= 6'd12 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd12 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd12, - x__h31565 <= 6'd11 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd11 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd11, - x__h31565 <= 6'd10 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd10 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd10, - x__h31565 <= 6'd9 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd9 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd9, - x__h31565 <= 6'd8 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd8 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd8, - x__h31565 <= 6'd7 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd7 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd7, - x__h31565 <= 6'd6 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd6 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd6, - x__h31565 <= 6'd5 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd5 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd5, - x__h31565 <= 6'd4 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd4 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd4, - x__h31565 <= 6'd3 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd3 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd3, - x__h31565 <= 6'd2 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd2 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd2, - x__h31565 <= 6'd1 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 > + x__h31580 <= 6'd1 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 > 6'd1, - x__h31565 == 6'd0 && - IF_m_pcie_wr_task_data_output_reg_35_BIT_0_46__ETC___d463 != + x__h31580 == 6'd0 && + IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 != 6'd0 } ; - assign x_strb__h43876 = - { x__h46771 <= 7'd63 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + assign x_strb__h43921 = + { x__h46816 <= 7'd63 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd63, - x__h46771 <= 7'd62 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd62 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd62, - x__h46771 <= 7'd61 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd61 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd61, - x__h46771 <= 7'd60 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd60 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd60, - x__h46771 <= 7'd59 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd59 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd59, - x__h46771 <= 7'd58 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd58 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd58, - x__h46771 <= 7'd57 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd57 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd57, - x__h46771 <= 7'd56 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd56 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd56, - x__h46771 <= 7'd55 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd55 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd55, - x__h46771 <= 7'd54 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd54 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd54, - x__h46771 <= 7'd53 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd53 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd53, - x__h46771 <= 7'd52 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd52 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd52, - x__h46771 <= 7'd51 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd51 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd51, - x__h46771 <= 7'd50 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd50 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd50, - x__h46771 <= 7'd49 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd49 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd49, - x__h46771 <= 7'd48 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd48 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd48, - x__h46771 <= 7'd47 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd47 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd47, - x__h46771 <= 7'd46 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd46 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd46, - x__h46771 <= 7'd45 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd45 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd45, - x__h46771 <= 7'd44 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd44 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd44, - x__h46771 <= 7'd43 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd43 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd43, - x__h46771 <= 7'd42 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd42 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd42, - x__h46771 <= 7'd41 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd41 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd41, - x__h46771 <= 7'd40 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd40 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd40, - x__h46771 <= 7'd39 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd39 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd39, - x__h46771 <= 7'd38 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd38 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd38, - x__h46771 <= 7'd37 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd37 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd37, - x__h46771 <= 7'd36 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd36 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd36, - x__h46771 <= 7'd35 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd35 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd35, - x__h46771 <= 7'd34 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd34 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd34, - x__h46771 <= 7'd33 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd33 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd33, - x__h46771 <= 7'd32 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd32 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd32, - x__h46771 <= 7'd31 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd31 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd31, - x__h46771 <= 7'd30 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd30 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd30, - x__h46771 <= 7'd29 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd29 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd29, - x__h46771 <= 7'd28 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd28 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd28, - x__h46771 <= 7'd27 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd27 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd27, - x__h46771 <= 7'd26 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd26 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd26, - x__h46771 <= 7'd25 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd25 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd25, - x__h46771 <= 7'd24 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd24 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd24, - x__h46771 <= 7'd23 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd23 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd23, - x__h46771 <= 7'd22 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd22 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd22, - x__h46771 <= 7'd21 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd21 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd21, - x__h46771 <= 7'd20 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd20 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd20, - x__h46771 <= 7'd19 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd19 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd19, - x__h46771 <= 7'd18 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd18 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd18, - x__h46771 <= 7'd17 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd17 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd17, - x__h46771 <= 7'd16 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd16 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd16, - x__h46771 <= 7'd15 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd15 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd15, - x__h46771 <= 7'd14 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd14 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd14, - x__h46771 <= 7'd13 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd13 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd13, - x__h46771 <= 7'd12 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd12 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd12, - x__h46771 <= 7'd11 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd11 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd11, - x__h46771 <= 7'd10 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd10 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd10, - x__h46771 <= 7'd9 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd9 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd9, - x__h46771 <= 7'd8 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd8 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd8, - x__h46771 <= 7'd7 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd7 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd7, - x__h46771 <= 7'd6 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd6 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd6, - x__h46771 <= 7'd5 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd5 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd5, - x__h46771 <= 7'd4 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd4 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd4, - x__h46771 <= 7'd3 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd3 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd3, - x__h46771 <= 7'd2 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd2 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd2, - x__h46771 <= 7'd1 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 > + x__h46816 <= 7'd1 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 > 7'd1, - x__h46771 == 7'd0 && - IF_m_fpga_wr_task_data_output_reg_16_BIT_0_27__ETC___d944 != + x__h46816 == 7'd0 && + IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 != 7'd0 } ; - assign x_transfers_total__h35588 = + assign x_transfers_total__h35603 = m_pcie_wr_task_data_output_reg[64:6] - 59'd1 ; - assign x_transfers_total__h39153 = + assign x_transfers_total__h39183 = m_pcie_rd_task_data_output_reg[64:6] - 59'd1 ; - assign x_transfers_total__h54794 = + assign x_transfers_total__h54839 = m_fpga_wr_task_data_output_reg[64:7] - 58'd1 ; - assign x_transfers_total__h58356 = + assign x_transfers_total__h58416 = m_fpga_rd_task_data_output_reg[64:7] - 58'd1 ; - assign y__h102066 = { 59'd0, readIn_rv[68:64] } ; - assign y__h145163 = { 59'd0, writeIn_rv[68:64] } ; + assign y__h102126 = { 59'd0, readIn_rv[68:64] } ; + assign y__h145223 = { 59'd0, writeIn_rv[68:64] } ; assign y__h26410 = { 59'd0, x__h26336[4:0] } ; assign y__h26544 = { 59'd0, m_pcie_wr_reqGen_intermediateBuffer$D_OUT[136:132] } ; assign y__h26546 = { 59'd0, m_pcie_wr_reqGen_intermediateBuffer$D_OUT[141:137] } ; - assign y__h36349 = { 59'd0, x__h36275[4:0] } ; - assign y__h36483 = + assign y__h36364 = { 59'd0, x__h36290[4:0] } ; + assign y__h36498 = { 59'd0, m_pcie_rd_reqGen_intermediateBuffer$D_OUT[136:132] } ; - assign y__h36485 = + assign y__h36500 = { 59'd0, m_pcie_rd_reqGen_intermediateBuffer$D_OUT[141:137] } ; - assign y__h40223 = { 58'd0, x__h40149[5:0] } ; - assign y__h40357 = + assign y__h40253 = { 58'd0, x__h40179[5:0] } ; + assign y__h40387 = { 58'd0, m_fpga_wr_reqGen_intermediateBuffer$D_OUT[137:132] } ; - assign y__h40359 = + assign y__h40389 = { 58'd0, m_fpga_wr_reqGen_intermediateBuffer$D_OUT[143:138] } ; - assign y__h55555 = { 58'd0, x__h55481[5:0] } ; - assign y__h55689 = + assign y__h55600 = { 58'd0, x__h55526[5:0] } ; + assign y__h55734 = { 58'd0, m_fpga_rd_reqGen_intermediateBuffer$D_OUT[137:132] } ; - assign y__h55691 = + assign y__h55736 = { 58'd0, m_fpga_rd_reqGen_intermediateBuffer$D_OUT[143:138] } ; always@(m_pcie_wr_master_wr_wawcache$wget) begin @@ -5655,7 +5721,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_handleRead) - $display("btt org %d, btt after %d", readIn_rv[63:0], btt__h102029); + $display("btt org %d, btt after %d", readIn_rv[63:0], btt__h102089); if (RST_N != `BSV_RESET_VALUE) if ((WILL_FIRE_RL_s_config_axiReadSpecial_7 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7) && @@ -6150,10 +6216,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_wr_reqGen_finishRequest) $display("[WRITE] requests_total: %d", - request_data_requests_total__h40467); + request_data_requests_total__h40497); if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_wr_reqGen_finishRequest) - $display("[WRITE] address: %x", request_data_address__h40468); + $display("[WRITE] address: %x", request_data_address__h40498); if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest) $display("[READ] request:"); @@ -6180,10 +6246,10 @@ module mkBlueDMA(CLK_m32_axi_aclk, if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest) $display("[READ] requests_total: %d", - request_data_requests_total__h55799); + request_data_requests_total__h55844); if (RST_N_m32_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest) - $display("[READ] address: %x", request_data_address__h55800); + $display("[READ] address: %x", request_data_address__h55845); end // synopsys translate_on @@ -6241,14 +6307,14 @@ module mkBlueDMA(CLK_m32_axi_aclk, m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[72:68]); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest) - $display("[READ] requests_last: %d", requests_last__h36556); + $display("[READ] requests_last: %d", requests_last__h36571); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest) $display("[READ] requests_total: %d", - request_data_requests_total__h36593); + request_data_requests_total__h36608); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest) - $display("[READ] address: %x", request_data_address__h36594); + $display("[READ] address: %x", request_data_address__h36609); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) if (byteAlignerReader_addr_ff$dEMPTY_N) $display("Init data:"); if (RST_N_m64_axi_arestn != `BSV_RESET_VALUE) diff --git a/common/ip/BlueDMA/src/mkBlueDMAVivado.v b/common/ip/BlueDMA/src/mkBlueDMAVivado.v index 2f9e18e0..824a2f9d 100644 --- a/common/ip/BlueDMA/src/mkBlueDMAVivado.v +++ b/common/ip/BlueDMA/src/mkBlueDMAVivado.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07) // -// On Fri Jul 7 14:37:18 CEST 2017 +// On Mon Jul 10 18:45:54 CEST 2017 // // // Ports: @@ -15,6 +15,7 @@ // S_AXI_bvalid O 1 reg // S_AXI_bresp O 2 // m64_axi_arvalid O 1 reg +// m64_axi_arid O 1 // m64_axi_araddr O 64 // m64_axi_arlen O 8 // m64_axi_arsize O 3 @@ -27,6 +28,7 @@ // m64_axi_aruser O 1 // m64_axi_rready O 1 reg // m64_axi_awvalid O 1 reg +// m64_axi_awid O 1 // m64_axi_awaddr O 64 // m64_axi_awlen O 8 // m64_axi_awsize O 3 @@ -44,6 +46,7 @@ // m64_axi_wuser O 1 // m64_axi_bready O 1 reg // m32_axi_arvalid O 1 reg +// m32_axi_arid O 1 // m32_axi_araddr O 64 // m32_axi_arlen O 8 // m32_axi_arsize O 3 @@ -56,6 +59,7 @@ // m32_axi_aruser O 1 // m32_axi_rready O 1 reg // m32_axi_awvalid O 1 reg +// m32_axi_awid O 1 // m32_axi_awaddr O 64 // m32_axi_awlen O 8 // m32_axi_awsize O 3 @@ -92,6 +96,7 @@ // S_AXI_bready I 1 // m64_axi_arready I 1 // m64_axi_rvalid I 1 +// m64_axi_rid I 1 reg // m64_axi_rdata I 256 reg // m64_axi_rresp I 2 reg // m64_axi_rlast I 1 reg @@ -100,9 +105,11 @@ // m64_axi_wready I 1 // m64_axi_bvalid I 1 // m64_axi_bresp I 2 reg +// m64_axi_bid I 1 reg // m64_axi_buser I 1 reg // m32_axi_arready I 1 // m32_axi_rvalid I 1 +// m32_axi_rid I 1 reg // m32_axi_rdata I 512 reg // m32_axi_rresp I 2 reg // m32_axi_rlast I 1 reg @@ -111,6 +118,7 @@ // m32_axi_wready I 1 // m32_axi_bvalid I 1 // m32_axi_bresp I 2 reg +// m32_axi_bid I 1 reg // m32_axi_buser I 1 reg // // No combinational paths from inputs to outputs @@ -179,6 +187,8 @@ module mkBlueDMAVivado(m32_axi_aclk, m64_axi_arready, + m64_axi_arid, + m64_axi_araddr, m64_axi_arlen, @@ -203,6 +213,7 @@ module mkBlueDMAVivado(m32_axi_aclk, m64_axi_rvalid, + m64_axi_rid, m64_axi_rdata, m64_axi_rresp, m64_axi_rlast, @@ -212,6 +223,8 @@ module mkBlueDMAVivado(m32_axi_aclk, m64_axi_awvalid, + m64_axi_awid, + m64_axi_awaddr, m64_axi_awlen, @@ -249,12 +262,15 @@ module mkBlueDMAVivado(m32_axi_aclk, m64_axi_bready, m64_axi_bresp, + m64_axi_bid, m64_axi_buser, m32_axi_arvalid, m32_axi_arready, + m32_axi_arid, + m32_axi_araddr, m32_axi_arlen, @@ -279,6 +295,7 @@ module mkBlueDMAVivado(m32_axi_aclk, m32_axi_rvalid, + m32_axi_rid, m32_axi_rdata, m32_axi_rresp, m32_axi_rlast, @@ -288,6 +305,8 @@ module mkBlueDMAVivado(m32_axi_aclk, m32_axi_awvalid, + m32_axi_awid, + m32_axi_awaddr, m32_axi_awlen, @@ -325,6 +344,7 @@ module mkBlueDMAVivado(m32_axi_aclk, m32_axi_bready, m32_axi_bresp, + m32_axi_bid, m32_axi_buser, IRQ); @@ -399,6 +419,7 @@ module mkBlueDMAVivado(m32_axi_aclk, input m64_axi_arready; // value method pcie_rd_arid + output m64_axi_arid; // value method pcie_rd_araddr output [63 : 0] m64_axi_araddr; @@ -437,6 +458,7 @@ module mkBlueDMAVivado(m32_axi_aclk, input m64_axi_rvalid; // action method pcie_rd_prchannel + input m64_axi_rid; input [255 : 0] m64_axi_rdata; input [1 : 0] m64_axi_rresp; input m64_axi_rlast; @@ -449,6 +471,7 @@ module mkBlueDMAVivado(m32_axi_aclk, output m64_axi_awvalid; // value method pcie_wr_awid + output m64_axi_awid; // value method pcie_wr_awaddr output [63 : 0] m64_axi_awaddr; @@ -506,6 +529,7 @@ module mkBlueDMAVivado(m32_axi_aclk, // action method pcie_wr_bin input [1 : 0] m64_axi_bresp; + input m64_axi_bid; input m64_axi_buser; // value method fpga_rd_arvalid @@ -515,6 +539,7 @@ module mkBlueDMAVivado(m32_axi_aclk, input m32_axi_arready; // value method fpga_rd_arid + output m32_axi_arid; // value method fpga_rd_araddr output [63 : 0] m32_axi_araddr; @@ -553,6 +578,7 @@ module mkBlueDMAVivado(m32_axi_aclk, input m32_axi_rvalid; // action method fpga_rd_prchannel + input m32_axi_rid; input [511 : 0] m32_axi_rdata; input [1 : 0] m32_axi_rresp; input m32_axi_rlast; @@ -565,6 +591,7 @@ module mkBlueDMAVivado(m32_axi_aclk, output m32_axi_awvalid; // value method fpga_wr_awid + output m32_axi_awid; // value method fpga_wr_awaddr output [63 : 0] m32_axi_awaddr; @@ -622,6 +649,7 @@ module mkBlueDMAVivado(m32_axi_aclk, // action method fpga_wr_bin input [1 : 0] m32_axi_bresp; + input m32_axi_bid; input m32_axi_buser; // value method interrupt @@ -670,9 +698,11 @@ module mkBlueDMAVivado(m32_axi_aclk, S_AXI_bvalid, S_AXI_rvalid, S_AXI_wready, + m32_axi_arid, m32_axi_arlock, m32_axi_aruser, m32_axi_arvalid, + m32_axi_awid, m32_axi_awlock, m32_axi_awuser, m32_axi_awvalid, @@ -681,9 +711,11 @@ module mkBlueDMAVivado(m32_axi_aclk, m32_axi_wlast, m32_axi_wuser, m32_axi_wvalid, + m64_axi_arid, m64_axi_arlock, m64_axi_aruser, m64_axi_arvalid, + m64_axi_awid, m64_axi_awlock, m64_axi_awuser, m64_axi_awvalid, @@ -753,18 +785,22 @@ module mkBlueDMAVivado(m32_axi_aclk, blueDMA$S_AXI_rvalid, blueDMA$S_AXI_wready, blueDMA$S_AXI_wvalid, + blueDMA$fpga_rd_arid, blueDMA$fpga_rd_arlock, blueDMA$fpga_rd_arready, blueDMA$fpga_rd_aruser, blueDMA$fpga_rd_arvalid, + blueDMA$fpga_rd_rid, blueDMA$fpga_rd_rlast, blueDMA$fpga_rd_rready, blueDMA$fpga_rd_ruser, blueDMA$fpga_rd_rvalid, + blueDMA$fpga_wr_awid, blueDMA$fpga_wr_awlock, blueDMA$fpga_wr_awready, blueDMA$fpga_wr_awuser, blueDMA$fpga_wr_awvalid, + blueDMA$fpga_wr_bid, blueDMA$fpga_wr_bready, blueDMA$fpga_wr_buser, blueDMA$fpga_wr_bvalid, @@ -773,18 +809,22 @@ module mkBlueDMAVivado(m32_axi_aclk, blueDMA$fpga_wr_wuser, blueDMA$fpga_wr_wvalid, blueDMA$interrupt, + blueDMA$pcie_rd_arid, blueDMA$pcie_rd_arlock, blueDMA$pcie_rd_arready, blueDMA$pcie_rd_aruser, blueDMA$pcie_rd_arvalid, + blueDMA$pcie_rd_rid, blueDMA$pcie_rd_rlast, blueDMA$pcie_rd_rready, blueDMA$pcie_rd_ruser, blueDMA$pcie_rd_rvalid, + blueDMA$pcie_wr_awid, blueDMA$pcie_wr_awlock, blueDMA$pcie_wr_awready, blueDMA$pcie_wr_awuser, blueDMA$pcie_wr_awvalid, + blueDMA$pcie_wr_bid, blueDMA$pcie_wr_bready, blueDMA$pcie_wr_buser, blueDMA$pcie_wr_bvalid, @@ -820,6 +860,9 @@ module mkBlueDMAVivado(m32_axi_aclk, // value method pcie_rd_arvalid assign m64_axi_arvalid = blueDMA$pcie_rd_arvalid ; + // value method pcie_rd_arid + assign m64_axi_arid = blueDMA$pcie_rd_arid ; + // value method pcie_rd_araddr assign m64_axi_araddr = blueDMA$pcie_rd_araddr ; @@ -863,6 +906,9 @@ module mkBlueDMAVivado(m32_axi_aclk, // value method pcie_wr_awvalid assign m64_axi_awvalid = blueDMA$pcie_wr_awvalid ; + // value method pcie_wr_awid + assign m64_axi_awid = blueDMA$pcie_wr_awid ; + // value method pcie_wr_awaddr assign m64_axi_awaddr = blueDMA$pcie_wr_awaddr ; @@ -921,6 +967,9 @@ module mkBlueDMAVivado(m32_axi_aclk, // value method fpga_rd_arvalid assign m32_axi_arvalid = blueDMA$fpga_rd_arvalid ; + // value method fpga_rd_arid + assign m32_axi_arid = blueDMA$fpga_rd_arid ; + // value method fpga_rd_araddr assign m32_axi_araddr = blueDMA$fpga_rd_araddr ; @@ -964,6 +1013,9 @@ module mkBlueDMAVivado(m32_axi_aclk, // value method fpga_wr_awvalid assign m32_axi_awvalid = blueDMA$fpga_wr_awvalid ; + // value method fpga_wr_awid + assign m32_axi_awid = blueDMA$fpga_wr_awid ; + // value method fpga_wr_awaddr assign m32_axi_awaddr = blueDMA$fpga_wr_awaddr ; @@ -1042,22 +1094,26 @@ module mkBlueDMAVivado(m32_axi_aclk, .S_AXI_wvalid(blueDMA$S_AXI_wvalid), .fpga_rd_arready(blueDMA$fpga_rd_arready), .fpga_rd_rdata(blueDMA$fpga_rd_rdata), + .fpga_rd_rid(blueDMA$fpga_rd_rid), .fpga_rd_rlast(blueDMA$fpga_rd_rlast), .fpga_rd_rresp(blueDMA$fpga_rd_rresp), .fpga_rd_ruser(blueDMA$fpga_rd_ruser), .fpga_rd_rvalid(blueDMA$fpga_rd_rvalid), .fpga_wr_awready(blueDMA$fpga_wr_awready), + .fpga_wr_bid(blueDMA$fpga_wr_bid), .fpga_wr_bresp(blueDMA$fpga_wr_bresp), .fpga_wr_buser(blueDMA$fpga_wr_buser), .fpga_wr_bvalid(blueDMA$fpga_wr_bvalid), .fpga_wr_wready(blueDMA$fpga_wr_wready), .pcie_rd_arready(blueDMA$pcie_rd_arready), .pcie_rd_rdata(blueDMA$pcie_rd_rdata), + .pcie_rd_rid(blueDMA$pcie_rd_rid), .pcie_rd_rlast(blueDMA$pcie_rd_rlast), .pcie_rd_rresp(blueDMA$pcie_rd_rresp), .pcie_rd_ruser(blueDMA$pcie_rd_ruser), .pcie_rd_rvalid(blueDMA$pcie_rd_rvalid), .pcie_wr_awready(blueDMA$pcie_wr_awready), + .pcie_wr_bid(blueDMA$pcie_wr_bid), .pcie_wr_bresp(blueDMA$pcie_wr_bresp), .pcie_wr_buser(blueDMA$pcie_wr_buser), .pcie_wr_bvalid(blueDMA$pcie_wr_bvalid), @@ -1071,6 +1127,7 @@ module mkBlueDMAVivado(m32_axi_aclk, .S_AXI_bvalid(blueDMA$S_AXI_bvalid), .S_AXI_bresp(blueDMA$S_AXI_bresp), .pcie_rd_arvalid(blueDMA$pcie_rd_arvalid), + .pcie_rd_arid(blueDMA$pcie_rd_arid), .pcie_rd_araddr(blueDMA$pcie_rd_araddr), .pcie_rd_arlen(blueDMA$pcie_rd_arlen), .pcie_rd_arsize(blueDMA$pcie_rd_arsize), @@ -1083,6 +1140,7 @@ module mkBlueDMAVivado(m32_axi_aclk, .pcie_rd_aruser(blueDMA$pcie_rd_aruser), .pcie_rd_rready(blueDMA$pcie_rd_rready), .pcie_wr_awvalid(blueDMA$pcie_wr_awvalid), + .pcie_wr_awid(blueDMA$pcie_wr_awid), .pcie_wr_awaddr(blueDMA$pcie_wr_awaddr), .pcie_wr_awlen(blueDMA$pcie_wr_awlen), .pcie_wr_awsize(blueDMA$pcie_wr_awsize), @@ -1100,6 +1158,7 @@ module mkBlueDMAVivado(m32_axi_aclk, .pcie_wr_wuser(blueDMA$pcie_wr_wuser), .pcie_wr_bready(blueDMA$pcie_wr_bready), .fpga_rd_arvalid(blueDMA$fpga_rd_arvalid), + .fpga_rd_arid(blueDMA$fpga_rd_arid), .fpga_rd_araddr(blueDMA$fpga_rd_araddr), .fpga_rd_arlen(blueDMA$fpga_rd_arlen), .fpga_rd_arsize(blueDMA$fpga_rd_arsize), @@ -1112,6 +1171,7 @@ module mkBlueDMAVivado(m32_axi_aclk, .fpga_rd_aruser(blueDMA$fpga_rd_aruser), .fpga_rd_rready(blueDMA$fpga_rd_rready), .fpga_wr_awvalid(blueDMA$fpga_wr_awvalid), + .fpga_wr_awid(blueDMA$fpga_wr_awid), .fpga_wr_awaddr(blueDMA$fpga_wr_awaddr), .fpga_wr_awlen(blueDMA$fpga_wr_awlen), .fpga_wr_awsize(blueDMA$fpga_wr_awsize), @@ -1144,22 +1204,26 @@ module mkBlueDMAVivado(m32_axi_aclk, assign blueDMA$S_AXI_wvalid = S_AXI_wvalid ; assign blueDMA$fpga_rd_arready = m32_axi_arready ; assign blueDMA$fpga_rd_rdata = m32_axi_rdata ; + assign blueDMA$fpga_rd_rid = m32_axi_rid ; assign blueDMA$fpga_rd_rlast = m32_axi_rlast ; assign blueDMA$fpga_rd_rresp = m32_axi_rresp ; assign blueDMA$fpga_rd_ruser = m32_axi_ruser ; assign blueDMA$fpga_rd_rvalid = m32_axi_rvalid ; assign blueDMA$fpga_wr_awready = m32_axi_awready ; + assign blueDMA$fpga_wr_bid = m32_axi_bid ; assign blueDMA$fpga_wr_bresp = m32_axi_bresp ; assign blueDMA$fpga_wr_buser = m32_axi_buser ; assign blueDMA$fpga_wr_bvalid = m32_axi_bvalid ; assign blueDMA$fpga_wr_wready = m32_axi_wready ; assign blueDMA$pcie_rd_arready = m64_axi_arready ; assign blueDMA$pcie_rd_rdata = m64_axi_rdata ; + assign blueDMA$pcie_rd_rid = m64_axi_rid ; assign blueDMA$pcie_rd_rlast = m64_axi_rlast ; assign blueDMA$pcie_rd_rresp = m64_axi_rresp ; assign blueDMA$pcie_rd_ruser = m64_axi_ruser ; assign blueDMA$pcie_rd_rvalid = m64_axi_rvalid ; assign blueDMA$pcie_wr_awready = m64_axi_awready ; + assign blueDMA$pcie_wr_bid = m64_axi_bid ; assign blueDMA$pcie_wr_bresp = m64_axi_bresp ; assign blueDMA$pcie_wr_buser = m64_axi_buser ; assign blueDMA$pcie_wr_bvalid = m64_axi_bvalid ; -- GitLab