Closed
Milestone
2017.1
Features, bugfixes and improvements due for the 2017.1 release.
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
48
- itapasco does not start
- Add CLI log tracking switch
- Implement support for PEs with .xci IPs
- Add short command to dump example configuration
- Fix bug concerning clock association in netlist for PEs
- Add 'Coming Soon' notice to master branch
- Do not run HLS in DSE for existing cores
- Alternatives are not built prior to DSE
- Write unit tests for parser
- VC709: MSI-X controller
- BlueDMA
- Tapasco API: Backport Capabilities calls
- Rename platform_api.h to platform.h
- Rename tapasco_api.h/hpp to tapasco.h/hpp
- Automate SD card preparation
- Rename or remove [tapasco::get_generate_mode]
- Acknowledgement for Bluespec
- PyNQ: Fix base clock
- Rename .bit file
- Rename "baseline" to "axi4mm"
- PyNQ Platform
- Composer.Result should contain UtilizationReport
- Composition directory structure: Target first?
- ComposerLog: PlacerError not recognized
- DSE: Synthesis report is empty, but utilization.txt exists
- DSE: False positives for double enqueues of ConcreteRuns
- iTaPaSCo: Add log chasing patterns for Vivado
- Platform: Remove supportedFrequencies
- Platform: Remove slotCount
- Slurm DSE: squeue causes RuntimeException
- Vivado HLS 2016.4+ crashes during HLS
- Platform: Make board part optional
- Tapasco return code is wrong
- Import: Check re-run condition for task
- OOC: Parse component.xml to exclude Verilog includes
- Timing Report: Reports false max delay path
- Improve CommandLineParser error messages
- Man pages
- New Platform: PyNQ
- Check Vivado Compatibility
- Slurm DSE: Retrieve `Compose` reports
- OOC: Do not delete files on error
- Platform Benchmark: Add latency function
- Rename Composition Directories
- Rename Descriptions to extension ".json"
- Examples for Json syntax of Jobs
- VC709: Support multiple FPGAs in JTAG chain
- Fix number of threads in Compose
