esa.informatik.tu-darmstadt.de user BlueDMA 1.0 S_AXI AWADDR S_AXI_awaddr AWPROT S_AXI_awprot AWVALID S_AXI_awvalid AWREADY S_AXI_awready WDATA S_AXI_wdata WSTRB S_AXI_wstrb WVALID S_AXI_wvalid WREADY S_AXI_wready BRESP S_AXI_bresp BVALID S_AXI_bvalid BREADY S_AXI_bready ARADDR S_AXI_araddr ARPROT S_AXI_arprot ARVALID S_AXI_arvalid ARREADY S_AXI_arready RDATA S_AXI_rdata RRESP S_AXI_rresp RVALID S_AXI_rvalid RREADY S_AXI_rready m32_axi AWID m32_axi_awid AWADDR m32_axi_awaddr AWLEN m32_axi_awlen AWSIZE m32_axi_awsize AWBURST m32_axi_awburst AWLOCK m32_axi_awlock AWCACHE m32_axi_awcache AWPROT m32_axi_awprot AWREGION m32_axi_awregion AWQOS m32_axi_awqos AWUSER m32_axi_awuser AWVALID m32_axi_awvalid AWREADY m32_axi_awready WDATA m32_axi_wdata WSTRB m32_axi_wstrb WLAST m32_axi_wlast WUSER m32_axi_wuser WVALID m32_axi_wvalid WREADY m32_axi_wready BID m32_axi_bid BRESP m32_axi_bresp BUSER m32_axi_buser BVALID m32_axi_bvalid BREADY m32_axi_bready ARID m32_axi_arid ARADDR m32_axi_araddr ARLEN m32_axi_arlen ARSIZE m32_axi_arsize ARBURST m32_axi_arburst ARLOCK m32_axi_arlock ARCACHE m32_axi_arcache ARPROT m32_axi_arprot ARREGION m32_axi_arregion ARQOS m32_axi_arqos ARUSER m32_axi_aruser ARVALID m32_axi_arvalid ARREADY m32_axi_arready RID m32_axi_rid RDATA m32_axi_rdata RRESP m32_axi_rresp RLAST m32_axi_rlast RUSER m32_axi_ruser RVALID m32_axi_rvalid RREADY m32_axi_rready SUPPORTS_NARROW_BURST 0 NUM_READ_OUTSTANDING 8 NUM_WRITE_OUTSTANDING 8 m64_axi AWID m64_axi_awid AWADDR m64_axi_awaddr AWLEN m64_axi_awlen AWSIZE m64_axi_awsize AWBURST m64_axi_awburst AWLOCK m64_axi_awlock AWCACHE m64_axi_awcache AWPROT m64_axi_awprot AWREGION m64_axi_awregion AWQOS m64_axi_awqos AWUSER m64_axi_awuser AWVALID m64_axi_awvalid AWREADY m64_axi_awready WDATA m64_axi_wdata WSTRB m64_axi_wstrb WLAST m64_axi_wlast WUSER m64_axi_wuser WVALID m64_axi_wvalid WREADY m64_axi_wready BID m64_axi_bid BRESP m64_axi_bresp BUSER m64_axi_buser BVALID m64_axi_bvalid BREADY m64_axi_bready ARID m64_axi_arid ARADDR m64_axi_araddr ARLEN m64_axi_arlen ARSIZE m64_axi_arsize ARBURST m64_axi_arburst ARLOCK m64_axi_arlock ARCACHE m64_axi_arcache ARPROT m64_axi_arprot ARREGION m64_axi_arregion ARQOS m64_axi_arqos ARUSER m64_axi_aruser ARVALID m64_axi_arvalid ARREADY m64_axi_arready RID m64_axi_rid RDATA m64_axi_rdata RRESP m64_axi_rresp RLAST m64_axi_rlast RUSER m64_axi_ruser RVALID m64_axi_rvalid RREADY m64_axi_rready SUPPORTS_NARROW_BURST 0 NUM_READ_OUTSTANDING 8 NUM_WRITE_OUTSTANDING 8 s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW m64_axi_aresetn RST m64_axi_aresetn POLARITY ACTIVE_LOW m32_axi_aresetn RST m32_axi_aresetn POLARITY ACTIVE_LOW s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET s_axi_aresetn m64_axi_aclk CLK m64_axi_aclk ASSOCIATED_BUSIF m64_axi ASSOCIATED_RESET m64_axi_aresetn m32_axi_aclk CLK m32_axi_aclk ASSOCIATED_BUSIF m32_axi ASSOCIATED_RESET m32_axi_aresetn IRQ INTERRUPT IRQ SENSITIVITY LEVEL_HIGH m32_axi 16777216T 512 m64_axi 16777216T 256 S_AXI reg0 0 16777216T 64 register xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog mkBlueDMAVivado xilinx_anylanguagesynthesis_view_fileset viewChecksum 6dca3063 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog mkBlueDMAVivado xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 6dca3063 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 m32_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_arready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_araddr in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_rvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_rdata out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_rresp out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_awready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_awaddr in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_wready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_wdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_wstrb in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 S_AXI_bvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_bresp out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_arvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_arready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_arid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_araddr out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_arlen out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_arsize out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_arburst out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_arlock out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_arcache out 3 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_arprot out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_arqos out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_arregion out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_aruser out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_rready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_rvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_rid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_rdata in 255 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_ruser in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_awready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_awvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_awid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_awaddr out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_awlen out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_awsize out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_awburst out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_awlock out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_awcache out 3 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_awprot out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_awqos out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_awregion out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_awuser out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_wvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_wdata out 255 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_wstrb out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_wlast out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_wuser out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_bvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_bready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m64_axi_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_bid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m64_axi_buser in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_arvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_arready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_arid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_araddr out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_arlen out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_arsize out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_arburst out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_arlock out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_arcache out 3 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_arprot out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_arqos out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_arregion out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_aruser out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_rready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_rvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_rid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_rdata in 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_ruser in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_awready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_awvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_awid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_awaddr out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_awlen out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_awsize out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_awburst out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_awlock out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_awcache out 3 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_awprot out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_awqos out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_awregion out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_awuser out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_wvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_wdata out 511 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_wstrb out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_wlast out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_wuser out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_bvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_bready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m32_axi_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_bid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m32_axi_buser in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 IRQ out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation choice_list_99a1d2b9 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset src/SyncHandshake.v verilogSource src/SyncFIFO1.v verilogSource src/SyncRegister.v verilogSource src/FIFO1.v verilogSource src/FIFO2.v verilogSource src/SizedFIFO.v verilogSource src/SyncFIFO.v verilogSource src/mkBlueDMA.v verilogSource src/mkBlueDMAVivado.v verilogSource CHECKSUM_031e6e27 xilinx_anylanguagebehavioralsimulation_view_fileset src/SyncHandshake.v verilogSource src/SyncFIFO1.v verilogSource src/SyncRegister.v verilogSource src/FIFO1.v verilogSource src/FIFO2.v verilogSource src/SizedFIFO.v verilogSource src/SyncFIFO.v verilogSource src/mkBlueDMA.v verilogSource src/mkBlueDMAVivado.v verilogSource xilinx_xpgui_view_fileset xgui/BlueDMA_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 BlueDMA Component_Name mkBlueDMAVivado_v1_0 zynq virtex7 kintexu /UserIP BlueDMA package_project 1 2017-07-07T08:39:29Z 2016.4