• Jens Korinth's avatar
    Bugfix: Remove netlist replacement for cores · 3c810860
    Jens Korinth authored
    * netlist-only IP cores lead to problems with the clock constraints
      regarding the bus interfaces: Vivado could no longer infer the clock
      for each AXI interface automatically, leading to broken cores
    * removed netlist creation; deactivation of OOC builds in 2016.4+ fixes
      the core problem of synthesizing the same core dozens of times
    3c810860
Import.scala 6 KB