Commit 1ce272eb authored by Jens Korinth's avatar Jens Korinth

PyNQ: Fix DDR parameters, PS parameters

* since PyNQ does not have a board definition file, DDR and general PS
  parameters (e.g., APU freq) have to be set manually
* overridden createZynqPS in pynq.tcl takes care of that and also
  replaces the missing board automation for DDR, FIXED_IO
parent 5bfe0e82
......@@ -95,29 +95,11 @@ namespace eval tapasco {
variable stdcomps
puts "Creating Zynq-7000 series IP core ..."
puts " VLNV: [dict get $stdcomps ps vlnv]"
set paramlist [list \
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {800} \
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ $freq_mhz \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
CONFIG.PCW_IRQ_F2P_INTR {1} \
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_USE_M_AXI_GP0 {1}\
CONFIG.PCW_USE_M_AXI_GP1 {1}\
CONFIG.PCW_USE_S_AXI_HP0 {1}\
CONFIG.PCW_USE_S_AXI_HP1 {0}\
CONFIG.PCW_USE_S_AXI_HP2 {1}\
CONFIG.PCW_USE_S_AXI_HP3 {0}\
CONFIG.PCW_USE_S_AXI_ACP {1}\
CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64}\
CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64}\
]
puts " Preset: $preset"
puts " FCLK0 : $freq_mhz"
set ps [create_bd_cell -type ip -vlnv [dict get $stdcomps ps vlnv] $name]
if {$preset != {}} {
if {$preset != {} && $preset != ""} {
set_property -dict [list CONFIG.preset $preset] $ps
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } $ps
} {
......
......@@ -18,7 +18,7 @@
#
# @file clock_constraint.tcl
# @brief Plugin to constraint the sys_clk to the right pin on PyNQ.
# Workaround: PyNQ does not have a Vivado board definition fil
# Workaround: PyNQ does not have a Vivado board definition file.
# @author J. Korinth, TU Darmstadt (jk@esa.cs.tu-darmstadt.de)
#
namespace eval clock_constraint {
......
This diff is collapsed.
......@@ -130,8 +130,8 @@ class VivadoComposer()(implicit cfg: Configuration, maxThreads: Option[Int]) ext
"TESTBENCH_MODULE" -> target.pd.testbenchTemplate.toString,
"PRELOAD_FILES" -> "",
"PART" -> target.pd.part,
"BOARD_PART" -> (target.pd.boardPart getOrElse "{}"),
"BOARD_PRESET" -> (target.pd.boardPreset getOrElse "{}"),
"BOARD_PART" -> (target.pd.boardPart getOrElse ""),
"BOARD_PRESET" -> (target.pd.boardPreset getOrElse ""),
"PLATFORM_TCL" -> target.pd.tclLibrary.toString,
"ARCHITECTURE_TCL" -> target.ad.tclLibrary.toString,
"COMPOSITION" -> composition
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment