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Commit 3c810860 authored by Jens Korinth's avatar Jens Korinth
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Bugfix: Remove netlist replacement for cores

* netlist-only IP cores lead to problems with the clock constraints
  regarding the bus interfaces: Vivado could no longer infer the clock
  for each AXI interface automatically, leading to broken cores
* removed netlist creation; deactivation of OOC builds in 2016.4+ fixes
  the core problem of synthesizing the same core dozens of times
parent 99e50066
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