Commit 3c934e05 authored by Jaco Hofmann's avatar Jaco Hofmann

Optimize NetFPGA SUME DDR timings

parent 08de6f0c
Pipeline #1279 passed with stages
in 106 minutes and 3 seconds
--- nf_sume_ddr3A.prj 2019-05-28 14:25:57.000039000 +0200
+++ nfsume-axiddr3.prj 2019-05-28 14:08:48.000007000 +0200
@@ -1,7 +1,7 @@
<?xml version='1.0' encoding='UTF-8'?>
-+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
- <ModuleName>nf_sume_ddr3A</ModuleName>
+ <ModuleName>nfsume_ddr3a</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
@@ -9,10 +9,10 @@
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7vx690t-ffg1761/-3</TargetFPGA>
- <Version>4.0</Version>
- <SystemClock>Differential</SystemClock>
- <ReferenceClock>Differential</ReferenceClock>
- <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
+ <Version>2.4</Version>
+ <SystemClock>No Buffer</SystemClock>
+ <ReferenceClock>Use System Clock</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>0</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
@@ -22,7 +22,7 @@
<TimePeriod>1250</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
- <InputClkFreq>233.1</InputClkFreq>
+ <InputClkFreq>200</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>800</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
@@ -160,12 +160,6 @@
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="A15" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H20" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
- <Reference_Clock>
- <Pin PADName="H19/G18(CC_P/N)" Bank="38" name="clk_ref_p/n" />
- </Reference_Clock>
- <System_Clock>
- <Pin PADName="E34/E35(CC_P/N)" Bank="35" name="sys_clk_p/n" />
- </System_Clock>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
......@@ -27,15 +27,19 @@ namespace eval platform {
proc create_mig_core {name} {
puts "Creating MIG core for DDR ..."
if { ! [file exists [get_property DIRECTORY [current_project]]/nf_sume_ddr3A.prj]} {
puts "Copying MIG configuration to project directory"
file copy "$::env(TAPASCO_HOME)/platform/netfpga_sume/nf_sume_ddr3A.prj" "[get_property DIRECTORY [current_project]]/nf_sume_ddr3A.prj"
set copy_to "[get_property DIRECTORY [current_project]]/nf_sume_ddr3A.prj"
if { [file exists $copy_to] == 1} {
puts "Delete MIG configuration to project directory"
file delete $copy_to
}
puts "Copying MIG configuration to project directory"
file copy "$::env(TAPASCO_HOME)/platform/netfpga_sume/nf_sume_ddr3A.prj" $copy_to
# create the IP core itself
set mig_7series_0 [tapasco::ip::create_mig_core $name]
puts "Initializing MIG settings"
# set MIG properties
set_property -dict [ list \
CONFIG.XML_INPUT_FILE "[get_property DIRECTORY [current_project]]/nf_sume_ddr3A.prj" \
CONFIG.XML_INPUT_FILE $copy_to \
CONFIG.RESET_BOARD_INTERFACE {Custom} \
CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \
CONFIG.BOARD_MIG_PARAM {Custom}] $mig_7series_0
......
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......@@ -6,5 +6,5 @@
"TargetUtilization" : 90,
"Benchmark" : "netfpga_sume.benchmark",
"HostFrequency": 250.0,
"MemFrequency": 233.0
"MemFrequency": 200.0
}
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