Commit 5bfe0e82 authored by Jens Korinth's avatar Jens Korinth

Closes #55 - Platform: Make board part optional

* making it optional was trivial, but support in PyNQ was not
* noticed that the board part of the ZedBoard and the support files for
the ZedBoard were used, this does not work (completely different board)
* had to pull the master XDC to find the clock pin and fix that
* Platforms can implement platform::create_clock_port to generate their
own clock ports
* plugin is used to generated the constraints "post-synth"
* Zedboard and PyNQ bitstreams build, but cannot be tested
parent e38d3aef
......@@ -113,12 +113,16 @@ namespace eval tapasco {
CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64}\
]
set ps [create_bd_cell -type ip -vlnv [dict get $stdcomps ps vlnv] $name]
puts " Preset: $preset"
puts " FCLK0 : $freq_mhz"
set_property -dict [list CONFIG.preset $preset] $ps
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } $ps
set_property -dict $paramlist $ps
set ps [create_bd_cell -type ip -vlnv [dict get $stdcomps ps vlnv] $name]
if {$preset != {}} {
set_property -dict [list CONFIG.preset $preset] $ps
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } $ps
} {
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "0" Master "Disable" Slave "Disable" } $ps
}
return $ps
}
......@@ -487,8 +491,8 @@ namespace eval tapasco {
# Returns the board preset selected by the user.
# Default: ZC706
proc get_board_preset {} {
global TAPASCO_BOARD_PRESET
if {[info exists ::env(TAPASCO_BOARD_PRESET)]} {return $::env(TAPASCO_BOARD_PRESET)} {return $TAPASCO_BOARD_PRESET}
global tapasco_board_preset
if {[info exists tapasco_board_preset]} {return $tapasco_board_preset} {return {}}
}
# Returns an array of lists consisting of VLNV and instance count of kernels in
......@@ -806,7 +810,16 @@ namespace eval tapasco {
set cport [get_bd_pins -filter {DIR == I} -of_objects $clk]
}
puts " clk: $clk, cport: $cport"
apply_bd_automation -rule xilinx.com:bd_rule:board -config "Board_Interface $clk_mode" $cport
if {$cport != {}} {
# apply board automation
apply_bd_automation -rule xilinx.com:bd_rule:board -config "Board_Interface $clk_mode" $cport
puts "board automation worked, moving on"
} {
# last resort: try to call platform::create_clock_port
set clk_mode "sys_clk"
set cport [platform::create_clock_port $clk_mode]
connect_bd_net $cport [get_bd_pins -filter {TYPE == clk && DIR == I} -of_objects $clk]
}
}
for {set i 0; set clkn 1} {$i < [llength $freqs]} {incr i 2} {
......
......@@ -52,7 +52,9 @@ set bitstreamname @@BITSTREAM_NAME@@
# setup the project
create_project @@PROJECT_NAME@@ [pwd]/@@PROJECT_NAME@@ -part {@@PART@@} -force
set_property board_part {@@BOARD_PART@@} [current_project]
if {"@@BOARD_PART@@" != ""} {
set_property board_part {@@BOARD_PART@@} [current_project]
}
# configure message limits:
# suppress messages about no matching pins/ports
......
......@@ -3,14 +3,8 @@
"Description" : "PyNQ-Z1 Python Productivity for Zynq",
"TclLibrary" : "pynq.tcl",
"Part" : "xc7z020clg400-1",
"Harness" : "../zynq/include/platform-harness.svh",
"API" : "../zynq/include/platform-api.svh",
"TestbenchTemplate" : "../zynq/sv/platform-dpi.sv",
"BoardPart" : "em.avnet.com:zed:part0:1.2",
"BoardPreset" : "zedboard",
"TargetUtilization" : 99,
"SlotCount" : 128,
"ValueArgTemplate" : "../zynq/valueargs.directives.template",
"ReferenceArgTemplate" : "../zynq/referenceargs.directives.template",
"Benchmark" : "pynq.benchmark"
"ReferenceArgTemplate" : "../zynq/referenceargs.directives.template"
}
#
# Copyright (C) 2017 Jens Korinth, TU Darmstadt
#
# This file is part of Tapasco (TPC).
#
# Tapasco is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Tapasco is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
# @file clock_constraint.tcl
# @brief Plugin to constraint the sys_clk to the right pin on PyNQ.
# Workaround: PyNQ does not have a Vivado board definition fil
# @author J. Korinth, TU Darmstadt (jk@esa.cs.tu-darmstadt.de)
#
namespace eval clock_constraint {
# Constraints the input pins called 'sys_clk'
proc create_clock_constraint {} {
set clk [get_ports "sys_clk"]
set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } $clk
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} $clk
}
}
tapasco::register_plugin "platform::clock_constraint::create_clock_constraint" "post-synth"
......@@ -22,6 +22,7 @@ namespace eval platform {
namespace export create
namespace export generate
namespace export max_masters
namespace export create_clock_port
foreach f [glob -nocomplain -directory "$::env(TAPASCO_HOME)/platform/pynq/plugins" "*.tcl"] {
puts "Found plugin: $f"
......@@ -39,4 +40,8 @@ namespace eval platform {
proc generate {} {
return [zynq::generate]
}
proc create_clock_port {{name "clk"}} {
set clk [create_bd_port -dir I $name]
}
}
......@@ -294,9 +294,11 @@ namespace eval platform {
exit 1
}
}
if {[tapasco::get_board_preset] != {}} {
set_property -dict [list CONFIG.preset [tapasco::get_board_preset]] $ps
}
# activate ACP, HP0, HP2 and GP0/1 (+ FCLK1 @10MHz)
set_property -dict [list \
CONFIG.preset [tapasco::get_board_preset] \
CONFIG.PCW_USE_M_AXI_GP0 {1} \
CONFIG.PCW_USE_M_AXI_GP1 {1} \
CONFIG.PCW_USE_S_AXI_HP0 {1} \
......
......@@ -130,8 +130,8 @@ class VivadoComposer()(implicit cfg: Configuration, maxThreads: Option[Int]) ext
"TESTBENCH_MODULE" -> target.pd.testbenchTemplate.toString,
"PRELOAD_FILES" -> "",
"PART" -> target.pd.part,
"BOARD_PART" -> target.pd.boardPart,
"BOARD_PRESET" -> target.pd.boardPreset,
"BOARD_PART" -> (target.pd.boardPart getOrElse "{}"),
"BOARD_PRESET" -> (target.pd.boardPreset getOrElse "{}"),
"PLATFORM_TCL" -> target.pd.tclLibrary.toString,
"ARCHITECTURE_TCL" -> target.ad.tclLibrary.toString,
"COMPOSITION" -> composition
......@@ -187,7 +187,7 @@ class VivadoComposer()(implicit cfg: Configuration, maxThreads: Option[Int]) ext
"set TAPASCO_PLATFORM_HEADER {" + target.pd.harness.getOrElse("missing") + " " +
target. pd.api.getOrElse("missing") + "}" + NL +
"set TAPASCO_SIM_MODULE " + target.pd.testbenchTemplate.getOrElse("missing") + NL +
"set TAPASCO_BOARD_PRESET " + target.pd.boardPreset + NL +
(target.pd.boardPreset map (bp => "set tapasco_board_preset %s%s".format(bp, NL)) getOrElse "") +
(maxThreads map (mt => "set_param general.maxThreads %d%s".format(mt, NL)) getOrElse "") +
(maxThreads map (mt => "set tapasco_jobs %d%s".format(mt, NL)) getOrElse "") +
"set tapasco_freq " + f + NL +
......
......@@ -32,8 +32,8 @@ case class Platform (
name: String,
private val _tclLibrary: Path,
part: String,
boardPart: String,
boardPreset: String,
boardPart: Option[String],
boardPreset: Option[String],
targetUtilization: Int,
supportedFrequencies: Seq[Int],
slotCount: Int,
......
......@@ -277,8 +277,8 @@ package object json {
(JsPath \ "Name").read[String] (minLength[String](1)) ~
(JsPath \ "TclLibrary").read[Path] ~
(JsPath \ "Part").read[String] (minLength[String](1)) ~
(JsPath \ "BoardPart").read[String] (minLength[String](4)) ~
(JsPath \ "BoardPreset").read[String] (minLength[String](4)) ~
(JsPath \ "BoardPart").readNullable[String] (minLength[String](4)) ~
(JsPath \ "BoardPreset").readNullable[String] (minLength[String](4)) ~
(JsPath \ "TargetUtilization").read[Int] (min(5) keepAnd max(100)) ~
(JsPath \ "SupportedFrequencies").readNullable[Seq[Int]] (minLength[Seq[Int]](1)) .map (_ getOrElse (50 to 450 by 5)) ~
(JsPath \ "SlotCount").read[Int] (min(1) keepAnd max(255)) ~
......@@ -294,8 +294,8 @@ package object json {
(JsPath \ "Name").write[String] ~
(JsPath \ "TclLibrary").write[Path] ~
(JsPath \ "Part").write[String] ~
(JsPath \ "BoardPart").write[String] ~
(JsPath \ "BoardPreset").write[String] ~
(JsPath \ "BoardPart").writeNullable[String] ~
(JsPath \ "BoardPreset").writeNullable[String] ~
(JsPath \ "TargetUtilization").write[Int] ~
(JsPath \ "SupportedFrequencies").write[Seq[Int]] ~
(JsPath \ "SlotCount").write[Int] ~
......
......@@ -44,8 +44,8 @@ class PlatformSpec extends FlatSpec with Matchers {
c.name should equal ("zynq")
c.tclLibrary should equal (jsonPath.resolve("zynq.tcl"))
c.part should equal ("xc7z045ffg900-2")
c.boardPart should equal ("xilinx.com:zc706:part0:1.1")
c.boardPreset should equal ("ZC706")
c.boardPart should equal (Some("xilinx.com:zc706:part0:1.1"))
c.boardPreset should equal (Some("ZC706"))
c.targetUtilization should equal (55)
c.supportedFrequencies should contain inOrderOnly (250, 200, 150, 100, 42)
}
......@@ -57,8 +57,8 @@ class PlatformSpec extends FlatSpec with Matchers {
c.name should equal ("zynq")
c.tclLibrary should equal (jsonPath.resolve("zynq.tcl"))
c.part should equal ("xc7z045ffg900-2")
c.boardPart should equal ("xilinx.com:zc706:part0:1.1")
c.boardPreset should equal ("ZC706")
c.boardPart should equal (Some("xilinx.com:zc706:part0:1.1"))
c.boardPreset should equal (Some("ZC706"))
c.targetUtilization should equal (55)
c.supportedFrequencies should contain inOrderOnly (250, 200, 150, 100, 42)
}
......
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