Commit 74fee3f4 authored by Jens Korinth's avatar Jens Korinth

Closes #73 - PyNQ: Fix base clock

* added type clk to the bd pin and a frequency of 125 MHz
* added some debug output
* fixed PS parameters (from PyNQ example design)
parent d32c94ff
......@@ -24,9 +24,10 @@
namespace eval clock_constraint {
# Constraints the input pins called 'sys_clk'
proc create_clock_constraint {} {
puts "clock_constraint: setting sys_clk constraint to 125 MHz, 50% duty cycle"
set clk [get_ports "sys_clk"]
set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } $clk
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} $clk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} $clk
}
}
......
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