Commit a87b16be authored by Jens Korinth's avatar Jens Korinth

Closes #6

* fixes support for 2016.4 and 2017.1
* improved modularity by implementing shared platform::generate
* checking results of runs in Vivado, adding list of logs to check in
  case of error
* cleanup
parent ee529830
# Architecture: baseline
Proof-of-concept implementation of the most simple conceivable hardware
threadpool implementation based on the AXI4-bus. Useful as baseline for future,
optimized architectures as well as for demonstration of the basic implementation
of an Architecture for *Tapasco*.
## Building the TPC API library
Simply type `make` in this directory, and a directory `lib` should be created
which will contain the `.so` files.
This diff is collapsed.
//
// Copyright (C) 2014 Jens Korinth, TU Darmstadt
//
// This file is part of Tapasco (TPC).
//
// Tapasco is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Tapasco is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
//
`ifndef __TEST_API_VH__
`define __TEST_API_VH__ 1
// Simple API to write tests:
`define INTC_BASE 32'h41800000
`define TARGETIP_BASE 32'h43C00000
`define TARGETIP_OFFS 32'h00010000
task pre_load_mem_from_file;
input [(1024*8-1):0] filename;
input [31:0] addr;
input [31:0] no_bytes;
begin
tb.system_i.ps7.inst.ocmc.ocm.pre_load_mem_from_file(
filename,
addr,
no_bytes
);
end
endtask
task setup_system;
input [7:0] no_inst;
output [2:0] resp;
reg [7:0] i;
reg [31:0] data;
begin
// configure slave profiles
system_i.ps7.inst.set_slave_profile("S_AXI_HP0", 2'b00); // best case
system_i.ps7.inst.set_slave_profile("S_AXI_ACP", 2'b00); // best case
// setup AXI interrupt controller to receive all irqs
system_i.ps7.inst.write_data(
`INTC_BASE + 32'h08, 4, 32'hFFFFFFFF, resp
);
system_i.ps7.inst.write_data(
`INTC_BASE + 32'h1C, 4, 32'h3, resp
);
// read ISR
system_i.ps7.inst.read_data(
`INTC_BASE, 4, data, resp
);
for (i = 0; i < no_inst; i = i + 1) begin
// activate interrupts on first instance of target IP
system_i.ps7.inst.write_data(
`TARGETIP_BASE + i * `TARGETIP_OFFS + 32'h04, 4, 32'h1, resp
);
system_i.ps7.inst.write_data(
`TARGETIP_BASE + 32'h08, 4, 32'h1, resp
);
end
$display("--- SYSTEM SETUP FINISHED @ %0d ---", $time);
end
endtask
task launch_kernel;
input [7:0] inst_no;
output [3:0] irqs;
reg [2:0] resp;
begin
// start run
system_i.ps7.inst.write_data(
`TARGETIP_BASE + inst_no * `TARGETIP_OFFS , 4, 32'h1, resp
);
// wait for ap_done
system_i.ps7.inst.wait_interrupt( 0, irqs );
end
endtask
task read_kernel_reg;
input [7:0] inst_no;
input [9:0] register;
output [31:0] data;
output [2:0] resp;
begin
// read register
system_i.ps7.inst.read_data(
`TARGETIP_BASE + inst_no * `TARGETIP_OFFS + (register << 2), 4, data, resp
);
end
endtask
task write_kernel_reg;
input [7:0] inst_no;
input [9:0] register;
input [31:0] data;
output [2:0] resp;
begin
// write register
system_i.ps7.inst.write_data(
`TARGETIP_BASE + inst_no * `TARGETIP_OFFS + (register << 2), 4, data, resp
);
end
endtask
task read_mem;
input [31:0] start_addr;
input [6:0] no_of_bytes;
output [1023:0] data;
begin
system_i.ps7.inst.ocmc.ocm.read_mem(
data,
start_addr,
no_of_bytes
);
end
endtask
`endif /* __TEST_API_VH__ */
//
// Copyright (C) 2014 Jens Korinth, TU Darmstadt
//
// This file is part of Tapasco (TPC).
//
// Tapasco is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Tapasco is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
//
`ifndef __TEST_HARNESS_VH__
`define __TEST_HARNESS_VH__ 1
`define CLK_PERIOD 8
`define TIMEOUT 1000000000 // 1000 ms
`define PROGRESS 100000 // cycles
reg clk;
reg rst;
reg [95:0] progress;
// clock generation
initial clk <= 1;
always #(`CLK_PERIOD >> 1) clk <= ~clk;
// timeout process
initial begin
repeat (`TIMEOUT/`CLK_PERIOD) @(posedge clk);
$display("--- SIMULATION TIMEOUT @ %0d ---", $time);
$display("--- TEST FAILED @ %d ---", $time);
$finish;
end
// progress process
initial progress <= `PROGRESS;
always @(posedge clk) begin
if (rst) begin
progress <= progress - 1;
if (progress == 0) begin
$display("--- PROGRESS: %d cycles @ %0d ---", `PROGRESS, $time);
progress <= `PROGRESS;
end
end
end
// reset generation
initial begin
#100 rst <= 0;
repeat (1000) @(posedge clk);
rst <= 1;
repeat (100) @(posedge clk);
$display("--- RESET PHASE FINISHED @ %0d ---", $time);
end
system system_i(
clk,
rst
);
`endif /* __TEST_HARNESS_VH__ */
......@@ -40,10 +40,8 @@ namespace eval tapasco {
namespace export get_composition
namespace export get_design_frequency
namespace export get_design_period
namespace export get_generate_mode
namespace export get_number_of_processors
namespace export get_platform_header
namespace export get_sim_module
namespace export get_speed_grade
namespace export get_wns_from_timing_report
namespace export create_interconnect_tree
......@@ -454,7 +452,7 @@ namespace eval tapasco {
# Returns the current generation mode selected by the user.
# Default: "sim"
proc get_generate_mode {} {
if {[info exists ::env(TAPASCO_MODE)]} {return $::env(TAPASCO_MODE)} {return "bit"}
return "bit"
}
# Returns the desired design clock frequency (in MHz) selected by the user.
......@@ -484,18 +482,6 @@ namespace eval tapasco {
return $kernels
}
# Returns the file name of the current Platform's SystemVerilog include header.
proc get_platform_header {} {
global TAPASCO_PLATFORM_HEADER
return $TAPASCO_PLATFORM_HEADER
}
# Returns the file name of the current Platform's SystemVerilog testbench module.
proc get_sim_module {} {
global TAPASCO_SIM_MODULE
return $TAPASCO_SIM_MODULE
}
# Returns a list of configured features for the Platform.
proc get_platform_features {} {
global platformfeatures
......@@ -505,7 +491,11 @@ namespace eval tapasco {
# Returns a dictionary with the configuration of given Platform feature.
proc get_platform_feature {feature} {
global platformfeatures
if {[info exists platformfeatures] && [dict exists $platformfeatures $feature]} { return [dict get $platformfeatures $feature] } { return [dict create] }
if {[info exists platformfeatures] && [dict exists $platformfeatures $feature]} {
return [dict get $platformfeatures $feature]
} else {
return [dict create]
}
}
# Returns true, if given feature is configured and enabled.
......@@ -514,8 +504,8 @@ namespace eval tapasco {
if {[info exists platformfeatures]} {
if {[dict exists $platformfeatures $feature]} {
if {[dict get $platformfeatures $feature "enabled"] == "true"} {
return true
}
return true
}
}
}
return false
......
# create a dictionary of compatible VLNVs
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_bfm vlnv "xilinx.com:ip:cdn_axi_bfm:5.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.0"
dict set stdcomps pcie_intr_ctrl vlnv "ESA:user:pcie_intr_ctrl:1.0"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:2.3"
dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:1.1"
dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:user:tapasco_status:1.0"
dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.1"
# create a dictionary of compatible VLNVs
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_bfm vlnv "xilinx.com:ip:cdn_axi_bfm:5.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.1"
dict set stdcomps pcie_intr_ctrl vlnv "ESA:user:pcie_intr_ctrl:1.0"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:2.4"
dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:2.0"
dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:user:tapasco_status:1.0"
dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.2"
# create a dictionary of compatible VLNVs
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_bfm vlnv "xilinx.com:ip:cdn_axi_bfm:5.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.2"
dict set stdcomps pcie_intr_ctrl vlnv "ESA:user:pcie_intr_ctrl:1.0"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:2.4"
dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:2.0"
dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:user:tapasco_status:1.0"
dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.2"
# create a dictionary of compatible VLNVs
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_bfm vlnv "xilinx.com:ip:cdn_axi_bfm:5.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.3"
dict set stdcomps pcie_intr_ctrl vlnv "ESA:user:pcie_intr_ctrl:1.0"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:3.0"
dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:2.1"
dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:user:tapasco_status:1.0"
dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.3"
......@@ -2,7 +2,6 @@
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_bfm vlnv "xilinx.com:ip:cdn_axi_bfm:5.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
......
......@@ -2,7 +2,6 @@
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_bfm vlnv "xilinx.com:ip:cdn_axi_bfm:5.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
......
......@@ -2,7 +2,6 @@
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_bfm vlnv "xilinx.com:ip:cdn_axi_bfm:5.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
......@@ -11,7 +10,7 @@ dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.6"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.7"
dict set stdcomps pcie_intr_ctrl vlnv "ESA:user:pcie_intr_ctrl:1.0"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
......
......@@ -2,7 +2,6 @@
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_bfm vlnv "xilinx.com:ip:cdn_axi_bfm:5.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
......@@ -11,7 +10,7 @@ dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.6"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.8"
dict set stdcomps pcie_intr_ctrl vlnv "ESA:user:pcie_intr_ctrl:1.0"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
......
......@@ -37,16 +37,9 @@ source -notrace "$::env(TAPASCO_HOME)/common/common.tcl"
source -notrace @@ARCHITECTURE_TCL@@
# source platform-specific Tcl scripts
source -notrace "$env(TAPASCO_HOME)/platform/common/platform.tcl"
source -notrace @@PLATFORM_TCL@@
set mode [tapasco::get_generate_mode]
# check COMPILED_SIMLIB env var
if {$mode == "sim" && ![info exists ::env(COMPILED_SIMLIB)]} {
puts "Missing environment variable 'COMPILED_SIMLIB' - point to directory containing Vivado Simlib compiled for ModelSim (see UG900)."
exit 1
}
# name of the bitstream description file
set bitstreamname @@BITSTREAM_NAME@@
......@@ -70,16 +63,6 @@ set_msg_config -suppress -id {[xilinx.com:ip:axi_intc:4.1-7]}
# loadout-specific configuration
@@COMPOSITION@@
# ModelSim
if {$mode == "sim"} {
set_property target_simulator ModelSim [current_project]
set_property compxlib.compiled_library_dir "$::env(COMPILED_SIMLIB)" [current_project]
set_property -name {modelsim.simulate.vlog.more_options} -value {-sv} -objects [current_fileset -simset]
set_property -name {modelsim.simulate.vsim.more_options} -value {-c -keepstdout} -objects [current_fileset -simset]
set_property -name {modelsim.simulate.runtime} -value {-all} -objects [current_fileset -simset]
set_property -name {modelsim.simulate.log_all_signals} -value {true} -objects [current_fileset -simset]
}
# create design
create_bd_design -quiet "system"
......@@ -90,8 +73,8 @@ arch::create
platform::create
# create wrapper
make_wrapper -files [get_files [pwd]/$mode/@@PROJECT_NAME@@.srcs/sources_1/bd/system/system.bd] -top
add_files -norecurse [pwd]/$mode/@@PROJECT_NAME@@.srcs/sources_1/bd/system/hdl/system_wrapper.v
make_wrapper -files [get_files [pwd]/[tapasco::get_generate_mode]/@@PROJECT_NAME@@.srcs/sources_1/bd/system/system.bd] -top
add_files -norecurse [pwd]/[tapasco::get_generate_mode]/@@PROJECT_NAME@@.srcs/sources_1/bd/system/hdl/system_wrapper.v
update_compile_order -fileset sources_1
# generate according to the mode
......@@ -99,4 +82,3 @@ platform::generate
# exit successfully
exit
This diff is collapsed.
OPTION psf_version = 2.1;
BEGIN DRIVER dual_dma
OPTION supported_peripherals = (dual_dma);
OPTION copyfiles = all;
OPTION VERSION = 1.0;
OPTION NAME = dual_dma;
END DRIVER
#
# Copyright (C) 2014 David de la Chevallerie, TU Darmstadt
#
# This file is part of Tapasco (TPC).
#
# Tapasco is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Tapasco is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "dual_dma" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
}
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling dual_dma..."
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}
//
// Copyright (C) 2014 Jens Korinth, TU Darmstadt
// Copyright (C) 2014 David de la Chevallerie, TU Darmstadt
//
// This file is part of Tapasco (TPC).
//
......@@ -16,9 +16,9 @@
// You should have received a copy of the GNU Lesser General Public License
// along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 1 ns / 1 ps
module tb;
`include "platform-harness.svh"
endmodule
/***************************** Include Files *******************************/
#include "dual_dma.h"
/************************** Function Definitions ***************************/
//
// Copyright (C) 2014 David de la Chevallerie, TU Darmstadt
//
// This file is part of Tapasco (TPC).
//
// Tapasco is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Tapasco is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
//
#ifndef DUAL_DMA_H
#define DUAL_DMA_H
/****************** Include Files ********************/
#include "xil_types.h"
#include "xstatus.h"
#define DUAL_DMA_S_AXI_SLV_REG0_OFFSET 0
#define DUAL_DMA_S_AXI_SLV_REG1_OFFSET 4
#define DUAL_DMA_S_AXI_SLV_REG2_OFFSET 8
#define DUAL_DMA_S_AXI_SLV_REG3_OFFSET 12
#define DUAL_DMA_S_AXI_SLV_REG4_OFFSET 16
#define DUAL_DMA_S_AXI_SLV_REG5_OFFSET 20
#define DUAL_DMA_S_AXI_SLV_REG6_OFFSET 24
#define DUAL_DMA_S_AXI_SLV_REG7_OFFSET 28
#define DUAL_DMA_S_AXI_SLV_REG8_OFFSET 32
#define DUAL_DMA_S_AXI_SLV_REG9_OFFSET 36
#define DUAL_DMA_S_AXI_SLV_REG10_OFFSET 40
#define DUAL_DMA_S_AXI_SLV_REG11_OFFSET 44
#define DUAL_DMA_S_AXI_SLV_REG12_OFFSET 48
#define DUAL_DMA_S_AXI_SLV_REG13_OFFSET 52
#define DUAL_DMA_S_AXI_SLV_REG14_OFFSET 56
#define DUAL_DMA_S_AXI_SLV_REG15_OFFSET 60
#define DUAL_DMA_S_AXI_SLV_REG16_OFFSET 64
#define DUAL_DMA_S_AXI_SLV_REG17_OFFSET 68
#define DUAL_DMA_S_AXI_SLV_REG18_OFFSET 72
#define DUAL_DMA_S_AXI_SLV_REG19_OFFSET 76
#define DUAL_DMA_S_AXI_SLV_REG20_OFFSET 80
#define DUAL_DMA_S_AXI_SLV_REG21_OFFSET 84
#define DUAL_DMA_S_AXI_SLV_REG22_OFFSET 88
#define DUAL_DMA_S_AXI_SLV_REG23_OFFSET 92
#define DUAL_DMA_S_AXI_SLV_REG24_OFFSET 96
#define DUAL_DMA_S_AXI_SLV_REG25_OFFSET 100
#define DUAL_DMA_S_AXI_SLV_REG26_OFFSET 104
#define DUAL_DMA_S_AXI_SLV_REG27_OFFSET 108
#define DUAL_DMA_S_AXI_SLV_REG28_OFFSET 112
#define DUAL_DMA_S_AXI_SLV_REG29_OFFSET 116
#define DUAL_DMA_S_AXI_SLV_REG30_OFFSET 120
#define DUAL_DMA_S_AXI_SLV_REG31_OFFSET 124
/**************************** Type Definitions *****************************/
/**
*
* Write a value to a DUAL_DMA register. A 32 bit write is performed.
* If the component is implemented in a smaller width, only the least
* significant data is written.
*
* @param BaseAddress is the base address of the DUAL_DMAdevice.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note
* C-style signature:
* void DUAL_DMA_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
*
*/
#define DUAL_DMA_mWriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/**
*
* Read a value from a DUAL_DMA register. A 32 bit read is performed.
* If the component is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the DUAL_DMA device.
* @param RegOffset is the register offset from the base to write to.
*
* @return Data is the data from the register.
*
* @note
* C-style signature:
* u32 DUAL_DMA_mReadReg(u32 BaseAddress, unsigned RegOffset)
*
*/
#define DUAL_DMA_mReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ****************************/
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the DUAL_DMA instance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.
*
*/
XStatus DUAL_DMA_Reg_SelfTest(void * baseaddr_p);
#endif // DUAL_DMA_H
//
// Copyright (C) 2014 David de la Chevallerie, TU Darmstadt
//
// This file is part of Tapasco (TPC).
//
// Tapasco is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Tapasco is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
//
/***************************** Include Files *******************************/
#include "dual_dma.h"
#include "xparameters.h"
#include "stdio.h"
#include "xil_io.h"
/************************** Constant Definitions ***************************/
#define READ_WRITE_MUL_FACTOR 0x10
/************************** Function Definitions ***************************/
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the DUAL_DMAinstance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.