Commit d9ea378f authored by Jens Korinth's avatar Jens Korinth

Fix bug concerning illegal name of thread pool

* 'Architecture' is illegal, renamed to 'uArch'
* fixed in Platforms
parent 7fdee069
......@@ -40,7 +40,7 @@ namespace eval arch {
# Returns a list of the bd_cells of slave interfaces of the threadpool.
proc get_slaves {} {
set inst [current_bd_instance]
current_bd_instance "Architecture"
current_bd_instance "uArch"
set r [list [get_bd_intf_pins -of [get_bd_cells "in1"] -filter { MODE == "Slave" }]]
current_bd_instance $inst
return $r
......@@ -53,12 +53,12 @@ namespace eval arch {
}
proc get_processing_elements {} {
return [get_bd_cells "Architecture/target*"]
return [get_bd_cells "uArch/target*"]
}
# Returns a list of interrupt lines from the threadpool.
proc get_irqs {} {
return [get_bd_pins -of_objects [get_bd_cells "Architecture"] -filter {TYPE == "intr" && DIR == "O"}]
return [get_bd_pins -of_objects [get_bd_cells "uArch"] -filter {TYPE == "intr" && DIR == "O"}]
}
# Checks, if the current composition can be instantiated. Exits script with
......@@ -376,7 +376,7 @@ namespace eval arch {
}
# create hierarchical group
set group [create_bd_cell -type hier "Architecture"]
set group [create_bd_cell -type hier "uArch"]
set instance [current_bd_instance .]
current_bd_instance $group
......
......@@ -481,7 +481,7 @@ namespace eval platform {
}
# connect user IP
set usrs [lsort [get_bd_addr_segs "/Threadpool/*"]]
set usrs [lsort [get_bd_addr_segs "/uArch/*"]]
set offset 0x02000000
for {set i 0} {$i < [llength $usrs]} {incr i; incr offset 0x10000} {
create_bd_addr_seg -range 64K -offset $offset $master_addr_space [lindex $usrs $i] "USR_SEG$i"
......@@ -499,7 +499,7 @@ namespace eval platform {
create_bd_addr_seg -range 4G -offset 0 $ms $ts "SEG_$ms"
}
# conenct user IP
set usrs [lsort [get_bd_addr_spaces /Threadpool/* -filter { NAME =~ "*m_axi*" || NAME =~ "*M_AXI*" }]]
set usrs [lsort [get_bd_addr_spaces /uArch/* -filter { NAME =~ "*m_axi*" || NAME =~ "*M_AXI*" }]]
set ts [get_bd_addr_segs /Memory/mig/*]
foreach u $usrs {
create_bd_addr_seg -range [get_property RANGE $u] -offset 0 $u $ts "SEG_$u"
......@@ -591,7 +591,7 @@ namespace eval platform {
set design_clk_receivers [list \
[get_bd_pins $ss_mem/design_clk] \
[get_bd_pins $ss_reset/design_aclk] \
[get_bd_pins Threadpool/*aclk] \
[get_bd_pins uArch/*aclk] \
[get_bd_pins $axi_ic_from_host/M00_ACLK] \
]
......@@ -639,7 +639,7 @@ namespace eval platform {
set design_rst_receivers [list \
[get_bd_pins $ss_mem/design_peripheral_aresetn] \
[get_bd_pins Threadpool/*peripheral_aresetn] \
[get_bd_pins uArch/*peripheral_aresetn] \
[get_bd_pins $axi_ic_from_host/M00_ARESETN] \
]
......@@ -651,12 +651,12 @@ namespace eval platform {
connect_bd_net $design_clk_ic_aresetn \
[get_bd_pins $ss_mem/interconnect_aresetn] \
[get_bd_pins Threadpool/*interconnect_aresetn] \
[get_bd_pins uArch/*interconnect_aresetn] \
[get_bd_pins $axi_ic_to_mem/ARESETN]
# connect AXI from host to system
connect_bd_intf_net [get_bd_intf_pins $ss_pcie/m_axi] [get_bd_intf_pins $axi_ic_from_host/S00_AXI]
connect_bd_intf_net [get_bd_intf_pins $axi_ic_from_host/M00_AXI] [get_bd_intf_pins Threadpool/S_AXI]
connect_bd_intf_net [get_bd_intf_pins $axi_ic_from_host/M00_AXI] [get_bd_intf_pins uArch/S_AXI]
connect_bd_intf_net [get_bd_intf_pins $axi_ic_from_host/M01_AXI] [get_bd_intf_pins $ss_int/S_AXI]
connect_bd_intf_net [get_bd_intf_pins $axi_ic_from_host/M02_AXI] [get_bd_intf_pins $ss_mem/s_axi_ddma]
......
......@@ -58,10 +58,10 @@ namespace eval platform {
set ics [get_bd_cells -filter "VLNV =~ *axi_interconnect*"]
set ic_resets [get_bd_pins -of_objects $ics -filter { TYPE == "rst" && NAME == "ARESETN" }]
lappend ic_resets [get_bd_pins Threadpool/interconnect_aresetn]
lappend ic_resets [get_bd_pins uArch/interconnect_aresetn]
set periph_resets [get_bd_pins -of_objects $ics -filter { TYPE == "rst" && NAME != "ARESETN" && DIR == "I" }]
lappend periph_resets [get_bd_pins -filter { TYPE == "rst" && DIR == "I" && NAME != "ARESETN" } -of_objects [get_bd_cells -filter { NAME =~ axi_intc* }]]
lappend periph_resets [get_bd_pins Threadpool/peripheral_aresetn]
lappend periph_resets [get_bd_pins uArch/peripheral_aresetn]
lappend periph_resets [get_bd_pins "tapasco_status/s00_axi_aresetn"]
puts "ic_resets = $ic_resets"
puts "periph_resets = $periph_resets"
......@@ -305,7 +305,7 @@ namespace eval platform {
}
# connect user IP: slaves
set usrs [lsort [get_bd_addr_segs "/Threadpool/*"]]
set usrs [lsort [get_bd_addr_segs "/uArch/*"]]
set offset 0x43C00000
for {set i 0} {$i < [llength $usrs]} {incr i; incr offset 0x10000} {
create_bd_addr_seg -range 64K -offset $offset $host_addr_space [lindex $usrs $i] "USR_SEG$i"
......@@ -345,7 +345,7 @@ namespace eval platform {
foreach clk [list "host" "design" "memory"] {
foreach p [list "aclk" "interconnect_aresetn" "peripheral_aresetn"] {
connect_bd_net [get_bd_pins "$ss_cnr/${clk}_${p}"] [get_bd_pins "Threadpool/${clk}_${p}"]
connect_bd_net [get_bd_pins "$ss_cnr/${clk}_${p}"] [get_bd_pins "uArch/${clk}_${p}"]
}
}
......@@ -360,7 +360,7 @@ namespace eval platform {
set tapasco_status [createTapascoStatus [tapasco::get_composition]]
set gp0_out [tapasco::create_interconnect_tree "gp0_out" 2 false]
connect_bd_intf_net [get_bd_intf_pins "$ss_host/M_AXI_GP0"] [get_bd_intf_pins "$gp0_out/S000_AXI"]
connect_bd_intf_net [get_bd_intf_pins "$gp0_out/M000_AXI"] [get_bd_intf_pins "/Threadpool/S_AXI"]
connect_bd_intf_net [get_bd_intf_pins "$gp0_out/M000_AXI"] [get_bd_intf_pins "/uArch/S_AXI"]
connect_bd_intf_net [get_bd_intf_pins "$gp0_out/M001_AXI"] [get_bd_intf_pins "$tapasco_status/S00_AXI"]
connect_bd_net [get_bd_pins "$ss_cnr/host_aclk"] \
[get_bd_pins -filter {TYPE == clk && DIR == I} -of_objects $tapasco_status] \
......@@ -403,7 +403,7 @@ namespace eval platform {
set host_prefix "system_i/Host"
set ps_prefix "system_i/Host/ps7"
set int_prefix "system_i/InterruptControl_"
set tp_prefix "system_i/Threadpool_"
set tp_prefix "system_i/uArch_"
set ret [list \
"$host_prefix/irq_out*" \
......
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