AXI Interconnect does not handle AXI4 -> AXI4 Lite properly for small transfers
It seems like the AXI interconnect does not handle protocol conversion from AXI4 to AXI4-Lite properly and ignores the strb signal on reads. Accordingly, whenever a request comes e.g. through PCIe that is larger than the AXI4-Lite slave data width it will result in superfluous transactions. That's not a big deal for writes as the strb signal is set properly. However, for reads there is no such signal in AXI4-Lite and if the read has some effect on the state of the device it will result in hard to debug problems. This is known to Xilinx but seems to be wont-fix: https://forums.xilinx.com/t5/Embedded-Development-Tools/AXI4-gt-AXI-Lite-wstrb-behavior/td-p/645535