Partial Reconfiguration: Speed up synthesis
Synthesis of MIG core and PCIe takes very long time, significant amount of overall time for a run. Idea: Use a pre-synthesized design, ideally even placed and routed, for the Platform, and only add the dynamic ThreadPool afterwards.
This approach could be achieved by wiring the Platform first, defining a general address mapping. Then synthesize, place and route the entire design and remove the Threadpool cell afterwards, replacing it with a black box. This design checkpoint could then be loaded and only the Threadpool would be added.
Since Design Checkpoints (DCPs) are specific to each Vivado version, there should be a command to initialize the DCPs once for each Platform.