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Fix bug concerning clock association in netlist for PEs

Since the change to netlist IP, most Vivado HLS PEs are broken: Vivado calls the clock port ap_clk and it cannot automatically infer that this clock is associated with each of the AXI ports, leading in turn to broken clock conversions.

Need to fix this by extending the original component.xml instead of inferring a new one.

Edited by Jens Korinth