Commit 03d74ebf authored by Jens Korinth's avatar Jens Korinth

Closes #71 - Rename baseline to axi4mm

* baseline sounds suboptimal and does not give any idea towards the kind
  of Architecture
* since it is based on AXI4 memory mapped interfaces it is renamed to
  axi4mm
* fixed all occurrences of baseline
parent 766370fb
......@@ -18,7 +18,7 @@ Terminology
* _Architecture_
The basic template for your hardware thread pool, i.e., the organisation
of your _Core instances. Currently there is only one such _Architecture_
called `baseline`.
called `axi4mm`.
* _ThreadPool_
Consists of a number of _Processing Elements (PEs)_, which can all operate
......@@ -253,7 +253,7 @@ logfiles, you can watch them via `tail --follow <FILE>` on a separate shell,
if you like.
If everything went well, there should be a `.bit` file in
`$TAPASCO_HOME/bd/<YOUR BD>/baseline/zedboard` afterwards (refer to the logging
`$TAPASCO_HOME/bd/<YOUR BD>/axi4mm/zedboard` afterwards (refer to the logging
output for the value of `<YOUR BD>` - if you had used an external _Composition_
description file, it would use that name instead of the hash).
......
cmake_minimum_required(VERSION 2.6)
project(arch-baseline)
project(arch-axi4mm)
set(CMAKE_INSTALL_PREFIX "..")
set(CMAKE_SKIP_RPATH true)
......
{
"Name" : "axi4mm",
"Description" : "Architecture based on AXI4 memory-mapped master/slave interfaces.",
"TclLibrary" : "axi4mm.tcl",
"HLSTclTemplate" : "../../common/hls.tcl.template"
}
......@@ -16,12 +16,8 @@
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
# @file baseline.tcl
# @brief Baseline architecture implementation: Connects up to 64 cores
# (resp. 64 master interfaces, 256 slaves interfaces), host
# connection to AXI slaves via GP0 and a two-level interconnect
# hierarchy, memory connection from AXI masters via independent
# interconnects to HP0-2.
# @file axi4mm.tcl
# @brief AXI4 memory mapped master/slave interface based Architectures.
# @author J. Korinth, TU Darmstadt (jk@esa.tu-darmstadt.de)
#
namespace eval arch {
......@@ -37,14 +33,14 @@ namespace eval arch {
set arch_irq_concats [list]
# scan plugin directory
foreach f [glob -nocomplain -directory "$::env(TAPASCO_HOME)/arch/baseline/plugins" "*.tcl"] {
foreach f [glob -nocomplain -directory "$::env(TAPASCO_HOME)/arch/axi4mm/plugins" "*.tcl"] {
source -notrace $f
}
# Returns a list of the bd_cells of slave interfaces of the threadpool.
proc get_slaves {} {
set inst [current_bd_instance]
current_bd_instance "Threadpool"
current_bd_instance "Architecture"
set r [list [get_bd_intf_pins -of [get_bd_cells "in1"] -filter { MODE == "Slave" }]]
current_bd_instance $inst
return $r
......@@ -57,12 +53,12 @@ namespace eval arch {
}
proc get_processing_elements {} {
return [get_bd_cells "Threadpool/target*"]
return [get_bd_cells "Architecture/target*"]
}
# Returns a list of interrupt lines from the threadpool.
proc get_irqs {} {
return [get_bd_pins -of_objects [get_bd_cells "Threadpool"] -filter {TYPE == "intr" && DIR == "O"}]
return [get_bd_pins -of_objects [get_bd_cells "Architecture"] -filter {TYPE == "intr" && DIR == "O"}]
}
# Checks, if the current composition can be instantiated. Exits script with
......@@ -380,7 +376,7 @@ namespace eval arch {
}
# create hierarchical group
set group [create_bd_cell -type hier "Threadpool"]
set group [create_bd_cell -type hier "Architecture"]
set instance [current_bd_instance .]
current_bd_instance $group
......
{
"Name" : "baseline",
"Description" : "Baseline Architecture with SW-based thread pool control.",
"TclLibrary" : "baseline.tcl",
"HLSTclTemplate" : "../../common/hls.tcl.template"
}
......@@ -27,7 +27,7 @@ print('Platform: ' + os.environ['TAPASCO_PLATFORM'])
moddir = '$TAPASCO_HOME/platform/$TAPASCO_PLATFORM/module'
pdir = '$TAPASCO_HOME/platform/$TAPASCO_PLATFORM/build'
adir = '$TAPASCO_HOME/arch/baseline/build'
adir = '$TAPASCO_HOME/arch/axi4mm/build'
tdir = '$TAPASCO_HOME/arch/tests/build'
if clean or args.rebuild:
......
Architecture = baseline
Platform = zynq
Bitstream = arrayinit.bd
Architecture = baseline
Platform = zynq
Bitstream = arraysum.bd
{"Platforms":["zedboard","zc706","vc709"],"Architectures":["baseline"],"DesignSpaceExploration":"freq","Compositions":["basic_test.bd"],"PlatformFeatures":{"LED":{"Enabled":true},"OLED":{"Enabled":true},"Cache":{"Enabled":false,"Size":32768,"Associativity":2},"Debug":{"Enabled":false,"Depth":2048,"Stages":2}}}
{"Platforms":["zedboard","zc706","vc709"],"Architectures":["axi4mm"],"DesignSpaceExploration":"freq","Compositions":["basic_test.bd"],"PlatformFeatures":{"LED":{"Enabled":true},"OLED":{"Enabled":true},"Cache":{"Enabled":false,"Size":32768,"Associativity":2},"Debug":{"Enabled":false,"Depth":2048,"Stages":2}}}
# Example configuration: baseline, zynq, 48 instances of readwrite1.
Architecture = baseline
Platform = zynq
Bitstream = warraw.bd
{
"Name" : "baseline",
"Name" : "axi4mm",
"Description" : "Baseline Architecture with SW-based thread pool control.",
"TestAPI" : "test-api.svh",
"TestHarness" : "test-harness.svh",
"VerilogIncludeAPI" : "test-api.svh",
"VerilogIncludeHarness" : "test-harness.svh",
"TclLibrary" : "baseline.tcl"
"TclLibrary" : "axi4mm.tcl"
}
......@@ -4,7 +4,7 @@
"Version" : "0.1",
"Id" : 42,
"Target": {
"Architecture": "baseline",
"Architecture": "axi4mm",
"Platform": "zedboard"
},
"Description" : "A correct core description.",
......
......@@ -5,6 +5,6 @@
"TestHarness" : "test-harness.svh",
"VerilogIncludeAPI" : "test-api.svh",
"VerilogIncludeHarness" : "test-harness.svh",
"TclLibrary" : "baseline.tcl",
"TclLibrary" : "axi4mm.tcl",
"UnknownKey2" : "should be ignored"
}
......@@ -5,7 +5,7 @@
"Id" : 42,
"Description" : "A correct core description.",
"Target": {
"Architecture": "baseline",
"Architecture": "axi4mm",
"Platform": "zc706"
}
}
......@@ -4,7 +4,7 @@
"Version" : "0.1",
"Description" : "A correct core description.",
"Target": {
"Architecture": "baseline",
"Architecture": "axi4mm",
"Platform": "zc706"
}
}
......@@ -4,7 +4,7 @@
"Id" : 42,
"Description" : "A correct core description.",
"Target": {
"Architecture": "baseline",
"Architecture": "axi4mm",
"Platform": "zc706"
}
}
......@@ -4,7 +4,7 @@
"Id" : 42,
"Description" : "A correct core description.",
"Target": {
"Architecture": "baseline",
"Architecture": "axi4mm",
"Platform": "zc706"
}
}
......@@ -12,7 +12,7 @@
},
"Design Frequency" : 123,
"Implementation" : "Vivado",
"Architectures" : [ "baseline" ],
"Architectures" : [ "axi4mm" ],
"Platforms" : [ "pynq", "zedboard" ],
"DebugMode" : "r"
}
\ No newline at end of file
{
"Job" : "CoreStatistics",
"File Prefix" : "somePrefix_",
"Architectures" : [ "baseline" ],
"Architectures" : [ "axi4mm" ],
"Platforms" : [ "vc709", "zc706" ]
}
\ No newline at end of file
......@@ -19,7 +19,7 @@
"Heuristic" : "Job Throughput",
"Batch Size" : 16,
"Output Path" : "nonstandard/base/path",
"Architectures" : [ "baseline" ],
"Architectures" : [ "axi4mm" ],
"Platforms" : [ "pynq", "vc709" ],
"DebugMode" : "r"
}
\ No newline at end of file
{
"Job" : "HighLevelSynthesis",
"Implementation" : "VivadoHLS",
"Architectures" : [ "baseline" ],
"Architectures" : [ "axi4mm" ],
"Platforms" : [ "zedboard", "zc706" ],
"Kernels" : [ "counter", "arraysum" ]
}
\ No newline at end of file
......@@ -4,6 +4,6 @@
"Id" : 42,
"Description" : "Optional description of the core.",
"Average Clock Cycles" : 13124425,
"Architectures" : [ "baseline" ],
"Architectures" : [ "axi4mm" ],
"Platforms" : [ "zedboard", "zc706" ]
}
\ No newline at end of file
......@@ -15,13 +15,13 @@
},
"Design Frequency" : 123,
"Implementation" : "Vivado",
"Architectures" : [ "baseline" ],
"Architectures" : [ "axi4mm" ],
"Platforms" : [ "pynq", "zedboard" ],
"DebugMode" : "r"
}, {
"Job" : "CoreStatistics",
"File Prefix" : "somePrefix_",
"Architectures" : [ "baseline" ],
"Architectures" : [ "axi4mm" ],
"Platforms" : [ "vc709", "zc706" ]
}, {
"Job" : "DesignSpaceExploration",
......@@ -44,13 +44,13 @@
"Heuristic" : "Job Throughput",
"Batch Size" : 16,
"Output Path" : "nonstandard/base/path",
"Architectures" : [ "baseline" ],
"Architectures" : [ "axi4mm" ],
"Platforms" : [ "pynq", "vc709" ],
"DebugMode" : "r"
}, {
"Job" : "HighLevelSynthesis",
"Implementation" : "VivadoHLS",
"Architectures" : [ "baseline" ],
"Architectures" : [ "axi4mm" ],
"Platforms" : [ "zedboard", "zc706" ],
"Kernels" : [ "counter", "arraysum" ]
}, {
......@@ -59,6 +59,6 @@
"Id" : 42,
"Description" : "Optional description of the core.",
"Average Clock Cycles" : 13124425,
"Architectures" : [ "baseline" ],
"Architectures" : [ "axi4mm" ],
"Platforms" : [ "zedboard", "zc706" ]
} ]
\ No newline at end of file
{
"Name" : "baseline",
"Name" : "axi4mm",
"Description" : "Baseline Architecture with SW-based thread pool control.",
"TestAPI" : "test-api.svh",
"TestHarness" : "test-harness.svh",
......
{
"UnknownKey" : ["Some", "Stuff"],
"Name" : "baseline",
"Name" : "axi4mm",
"Description" : "Baseline Architecture with SW-based thread pool control.",
"TestAPI" : "test-api.svh",
"TestHarness" : "test-harness.svh",
"VerilogIncludeAPI" : "test-api.svh",
"VerilogIncludeHarness" : "test-harness.svh",
"TclLibrary" : "baseline.tcl",
"TclLibrary" : "axi4mm.tcl",
"UnknownKey2" : "should be ignored"
}
......@@ -5,13 +5,13 @@
"Version" : "0.1",
"Id" : 42,
"Target": {
"Architecture": "baseline",
"Architecture": "axi4mm",
"Platform": "vc709"
},
"Description" : "A correct core description.",
"AnotherKey" : 123,
"Target": {
"Architecture": "baseline",
"Architecture": "axi4mm",
"Platform": "vc709"
}
}
......@@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 2.6)
project (rot13)
include_directories("$ENV{TAPASCO_HOME}/arch/common/include" "$ENV{TAPASCO_HOME}/platform/common/include")
link_directories("$ENV{TAPASCO_HOME}/arch/baseline/lib/${CMAKE_SYSTEM_PROCESSOR}" "$ENV{TAPASCO_HOME}/platform/vc709/lib/${CMAKE_SYSTEM_PROCESSOR}")
link_directories("$ENV{TAPASCO_HOME}/arch/axi4mm/lib/${CMAKE_SYSTEM_PROCESSOR}" "$ENV{TAPASCO_HOME}/platform/vc709/lib/${CMAKE_SYSTEM_PROCESSOR}")
add_executable(rot13 rot13.cpp)
add_executable(tapasco-rot13 tapasco_rot13.cpp)
......
......@@ -17,4 +17,4 @@
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
${CROSS_COMPILE}g++ -o sudoku_mt -std=c++11 -Wall -Werror -g -pthread -I/scratch/jk/rcu/arch/common/include -I/scratch/jk/rcu/platform/common/include -L/scratch/jk/rcu/arch/baseline/lib/${ARCH} -L/scratch/jk/rcu/platform/zynq/lib/${ARCH} -lrt -ltapasco -lplatform-client multithreaded.cpp Sudoku.cpp Sudoku_HLS.cpp
${CROSS_COMPILE}g++ -o sudoku_mt -std=c++11 -Wall -Werror -g -pthread -I/scratch/jk/rcu/arch/common/include -I/scratch/jk/rcu/platform/common/include -L/scratch/jk/rcu/arch/axi4mm/lib/${ARCH} -L/scratch/jk/rcu/platform/zynq/lib/${ARCH} -lrt -ltapasco -lplatform-client multithreaded.cpp Sudoku.cpp Sudoku_HLS.cpp
......@@ -83,7 +83,7 @@ The main Tcl script of the Architecture generates a pre-wired cell called the
\'thread pool\' in which all PEs are instantiated and all their interfaces are
wired to macro-cell inputs/outputs.
.PP
Example: The \'baseline\' Architecture uses AXI4Lite interfaces for the control
Example: The \'axi4mm\' Architecture uses AXI4Lite interfaces for the control
registers of the PEs, AXI4-MM master interfaces for memory accesses of the PEs
and single wire, level-sensitive interrupt lines for signaling. The PEs are
connected using AXI Interconnect hierarchies.
......
......@@ -8,7 +8,7 @@ driver_debug = len(sys.argv) > 1 and sys.argv[1] == "driver_debug"
moddir = "$TAPASCO_HOME/platform/zynq/module"
pdir = "$TAPASCO_HOME/platform/zynq/build"
adir = "$TAPASCO_HOME/arch/baseline/build"
adir = "$TAPASCO_HOME/arch/axi4mm/build"
if clean:
subprocess.call(["rm -rf " + pdir], shell=True)
......
#
# Copyright (C) 2014 Jens Korinth, TU Darmstadt
#
# This file is part of Tapasco (TPC).
#
# Tapasco is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Tapasco is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
export ARCH=`uname -m`
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$TAPASCO_HOME/arch/baseline/lib/$ARCH:$TAPASCO_HOME/platform/zynq/lib/$ARCH
export LIBPLATFORM_SERVER_LIB=$TAPASCO_HOME/platform/zynq/lib/$ARCH/libplatform-server
export LIBPLATFORM_DEBUG=0xffffffff
......@@ -52,7 +52,7 @@ trait Configuration {
coreDir.resolve(kernel.name.toString).resolve(target.ad.name).resolve(target.pd.name)
/** Returns the default output directory for the given composition, target and frequency.
* _Example_: `arrayinit__counter/020_042/075.0/baseline/pynq`
* _Example_: `arrayinit__counter/020_042/075.0/axi4mm/pynq`
*/
def outputDir(composition: Composition, target: Target, freq: Heuristics.Frequency): Path = compositionDir
.resolve(target.ad.name)
......
......@@ -19,12 +19,12 @@ object JobExamples {
val composeJob = ComposeJob(composition,
123.0,
"Vivado",
Some(Seq("baseline")),
Some(Seq("axi4mm")),
Some(Seq("pynq", "zedboard")),
None, // FIXME Features missing
Some("r"))
val coreStatisticsJob = CoreStatisticsJob(Some("somePrefix_"),
Some(Seq("baseline")),
Some(Seq("axi4mm")),
Some(Seq("vc709", "zc706")))
val dseJob = DesignSpaceExplorationJob(composition,
123.0,
......@@ -32,19 +32,19 @@ object JobExamples {
Heuristics.ThroughputHeuristic,
16,
Some(Paths.get("nonstandard/base/path")),
Some(Seq("baseline")),
Some(Seq("axi4mm")),
Some(Seq("pynq", "vc709")),
None, // FIXME Features missing
Some("r"))
val hlsJob = HighLevelSynthesisJob("VivadoHLS",
Some(Seq("baseline")),
Some(Seq("axi4mm")),
Some(Seq("zedboard", "zc706")),
Some(Seq("counter", "arraysum")))
val importJob = ImportJob(Paths.get("path/to/ipxact-archive.zip"),
42,
Some("Optional description of the core."),
Some(13124425),
Some(Seq("baseline")),
Some(Seq("axi4mm")),
Some(Seq("zedboard", "zc706")))
val jobs: Seq[Job] = Seq(bulkImportJob, composeJob, coreStatisticsJob, dseJob, hlsJob, importJob)
......
......@@ -41,8 +41,8 @@ class ArchitectureSpec extends FlatSpec with Matchers {
val oc = Architecture.from(jsonPath.resolve("correct-arch.json"))
lazy val c = oc.right.get
assert(oc.isRight)
c.name should equal ("baseline")
c.tclLibrary should equal (jsonPath.resolve("baseline.tcl"))
c.name should equal ("axi4mm")
c.tclLibrary should equal (jsonPath.resolve("axi4mm.tcl"))
c.valueArgTemplate should equal (jsonPath.resolve("valuearg.directives.template"))
c.referenceArgTemplate should equal (jsonPath.resolve("referencearg.directives.template"))
}
......@@ -51,8 +51,8 @@ class ArchitectureSpec extends FlatSpec with Matchers {
val oc = Architecture.from(jsonPath.resolve("unknown-arch.json"))
lazy val c = oc.right.get
assert(oc.isRight)
c.name should equal ("baseline")
c.tclLibrary should equal (jsonPath.resolve("baseline.tcl"))
c.name should equal ("axi4mm")
c.tclLibrary should equal (jsonPath.resolve("axi4mm.tcl"))
c.valueArgTemplate should equal (jsonPath.resolve("valuearg.directives.template"))
c.referenceArgTemplate should equal (jsonPath.resolve("referencearg.directives.template"))
}
......
......@@ -60,11 +60,11 @@ class FileAssetManagerSpec extends FlatSpec with Matchers {
"Creating new core.jsons during runtime" should "be reflected in the caches" in {
val p = Files.createTempDirectory("tapasco-fileassetmanager-")
val d = p.resolve("Test").resolve("baseline").resolve("vc709").resolve("ipcore")
val d = p.resolve("Test").resolve("axi4mm").resolve("vc709").resolve("ipcore")
Files.createDirectories(d)
FileAssetManager.basepath(Entities.Cores).set(p)
assert(FileAssetManager.entities.cores.size == 0)
val zip = d.resolve("test_baseline.zip")
val zip = d.resolve("test_axi4mm.zip")
val cf = d.resolve("core.json")
Files.createFile(zip)
val t = Target(FileAssetManager.entities.architectures.toSeq.head, FileAssetManager.entities.platforms.toSeq.head)
......
......@@ -47,10 +47,10 @@ class ReportManagerSpec extends FlatSpec with Matchers {
}
private def setupStructure(p: Path): (Path, Path, Path, Path) = {
val cosimPath = p.resolve("arraysum").resolve("baseline").resolve("vc709").resolve("ipcore")
val cosimPath = p.resolve("arraysum").resolve("axi4mm").resolve("vc709").resolve("ipcore")
val powerPath = p.resolve("arrayinit").resolve("blueline").resolve("zedboard").resolve("ipcore")
val synthPath = p.resolve("aes").resolve("blackline").resolve("zc706").resolve("ipcore")
val timingPath = p.resolve("test").resolve("baseline").resolve("zc706").resolve("ipcore")
val timingPath = p.resolve("test").resolve("axi4mm").resolve("zc706").resolve("ipcore")
Files.createDirectories(cosimPath)
Files.createDirectories(powerPath)
Files.createDirectories(synthPath)
......@@ -79,7 +79,7 @@ class ReportManagerSpec extends FlatSpec with Matchers {
assert(rc.powerReports.size == 1)
assert(rc.timingReports.size == 1)
val r1 = rc.cosimReport("arraysum", "baseline", "vc709")
val r1 = rc.cosimReport("arraysum", "axi4mm", "vc709")
assert(r1.nonEmpty)
assert(r1.get.latency.avg == 280)
......@@ -92,7 +92,7 @@ class ReportManagerSpec extends FlatSpec with Matchers {
assert(r3.get.area.nonEmpty)
assert(r3.get.area.get.resources.FF == 776)
val r4 = rc.timingReport("test", "baseline", "zc706")
val r4 = rc.timingReport("test", "axi4mm", "zc706")
assert(r4.nonEmpty)
assert(r4.get.worstNegativeSlack == -5.703)
......@@ -116,7 +116,7 @@ class ReportManagerSpec extends FlatSpec with Matchers {
assert(rc.powerReports.size == 1)
assert(rc.timingReports.size == 1)
val r1 = rc.cosimReport("arraysum", "baseline", "vc709")
val r1 = rc.cosimReport("arraysum", "axi4mm", "vc709")
assert(r1.nonEmpty)
assert(r1.get.latency.avg == 280)
......@@ -125,7 +125,7 @@ class ReportManagerSpec extends FlatSpec with Matchers {
StandardCopyOption.REPLACE_EXISTING)
Thread.sleep(FS_SLEEP)
val r2 = rc.cosimReport("arraysum", "baseline", "vc709")
val r2 = rc.cosimReport("arraysum", "axi4mm", "vc709")
assert(r2.nonEmpty)
assert(r2.get.latency.avg == 2279)
......
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