Commits · master · tapasco / tapasco

12 Jul, 2019 1 commit
- Re-add mig.prj for NetFPGA SUME · 70a56084
  Carsten Heinz authored Jul 12, 2019
```
Includes changes from 3c934e05
```
  70a56084
03 Jul, 2019 2 commits
- Remove sublimes temporary files · 4d392df5
  Jaco Hofmann authored Jul 03, 2019
  
  4d392df5
- Adds Rust to gitignore and remove temp files · 237ec8bb
  Jaco Hofmann authored Jun 26, 2019
  
  237ec8bb
18 Jun, 2019 1 commit
- WIP: Switch Scala build system to Gradle; · a441895b
  Lukas Sommer authored Jun 18, 2019
  
  a441895b
29 Oct, 2018 1 commit
- Modify ProcessIO to capture output instead of closing pipe; · f736501a
  Lukas Sommer authored Oct 29, 2018
  
  f736501a
19 Sep, 2018 1 commit
- Ignore changes for NetFPGA SUME DDR project file · 466f1db8
  Jaco Hofmann authored Sep 19, 2018
  
  466f1db8
31 Jul, 2018 1 commit
- Add welbtalk stuff to gitignore · be62cb27
  Jaco Hofmann authored Jul 31, 2018
  
  be62cb27
02 Jul, 2018 1 commit

Fixes most of the build error introduced by unified driver merge · 545cb37e

Jaco Hofmann authored Jul 02, 2018

    - Not yet tested, there seem to be a lot of new errors introduced
    by premature merge
    - Further tests needed to ensure everything's working
    - Examples not yet fixed

545cb37e

04 May, 2018 3 commits
- Remove deprecated directories from gitignore · badfb81b
  Jaco Hofmann authored May 04, 2018
  
  badfb81b
- Changes build libs script to fit new cmake structure! · 92f999ff
  Jaco Hofmann authored May 04, 2018
  
  92f999ff
- Changes build libs script to fit new cmake structure! · ab369527
  Jaco Hofmann authored May 04, 2018
  
  ab369527
05 Mar, 2018 1 commit

Squash-merge 'pe-local-memories' feature · 17f0d672

Jens Korinth authored Mar 05, 2018

Squashed commit of the following:

commit 13fdb518
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Mar 2 22:34:38 2018 +0100

    Recognize Tcl errors in Vivado logs

commit 90b74d7c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Mar 2 15:04:11 2018 +0100

    Make ILA debug feature generic for all platforms

    * only get_debug_nets depends on the platform
    * rest moved to platform/common/plugins
    * supporting platforms implement wrapper plugin, see
      platform/zynq/plugins/debug.tcl
    * fixed several other issues, e.g., clock selection
    * closes #132 - no master compositions

commit cc8a2df2
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Mar 2 10:57:10 2018 +0100

    Bugfixes in Debug feature

    * added ILA implementation feature on VC709
    * fixed SILA implementation feature on axi4mm
    * fixed renamed post-bd event to pre-wrapper in several plugins
    * fixed wrong VLNV for SILA in 2017.4

commit 11efaf52
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Mar 1 17:16:13 2018 +0100

    Added another limitation to pe-local-memories.md

commit c3fc21fa
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Mar 1 17:11:55 2018 +0100

    Typo

commit 78bf5409
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Mar 1 17:08:06 2018 +0100

    Software support for PE-local memories

    * alpha version of software API: supports PE-local memories in transfers
      and job executions
    * see documentation/pe-local-memories.md for more details

commit 7a8b1f16
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Mar 1 11:08:53 2018 +0100

    Implement ultra-primitive first-fit memory allocator

    * does not actually manage memory, only addresses
    * for use in pe local memories

commit 1b5c8286
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Feb 28 14:09:55 2018 +0100

    Implement top-level API for job-attached transfers

    * top-level API is tapasco_device_job_set_transfer, which in turn uses
      tapasco_job level functions

commit 277dd3dd
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Feb 28 14:09:55 2018 +0100

    Implement API for job-attached transfers

    * tapasco_jobs now define functions to attach memory transfers to jobs
      to be executed just-in-time before execution by the scheduler
    * scheduler supports new constructs: if transfer length is marked > 0
      for an argument, it will allocate memory, transfer the data and
      updated the argument with the corresponding handle, as well as copy
      back and free the memory after return
    * no top-level API is implemented yet, only tapasco_job level
    * no malloc for local memories is implemented yet

commit 37972c5a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 18:23:11 2018 +0100

    Bugfix in common_2017.4.tcl: Did not source common_ip

commit 1c136d11
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 18:17:46 2018 +0100

    Fix bug in O0 of evaluate

commit 8dc75212
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 18:08:33 2018 +0100

    Add common/ip to evaluate projects

commit 971e3874
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 17:37:07 2018 +0100

    Deactivate debug logging

commit ccd8a4f3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 17:32:23 2018 +0100

    Reactivate warnings in evaluate logs

commit d660cb7a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 15:19:11 2018 +0100

    Another fix for construct_address_map

    * must also query master for expected base address

commit d54ced58
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 15:11:17 2018 +0100

    Fix bug in construct_address_map

    * must take into account range of both slave and master, and only use
      lesser one
    * fix was necessary for MicroBlaze

commit 56b77300
Merge: a2ce13bb 76275656
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 12:58:42 2018 +0100

    Merge branch '2018.1' into pe-local-memories

commit a2ce13bb
Merge: cd079c31 3d912101
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Feb 8 10:49:31 2018 +0100

    Merge branch '2018.1' of git:tapasco/tapasco into pe-local-memories

commit cd079c31
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Fri Feb 2 15:17:30 2018 +0100

    Revert "Recognize separate IAR status and IAR ACK registers"

        * Turns out Vivado changed the interrupt ack register back to 0x0c

    This reverts commit e63deaf5.

commit e63deaf5
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Fri Feb 2 10:57:58 2018 +0100

    Recognize separate IAR status and IAR ACK registers

commit 4f219431
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Feb 1 15:51:22 2018 +0100

    Properly align interrupts for VC709

commit a39a13f8
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 21:31:18 2018 +0100

    Reverts back to old dual_dma.xdc to fix problems with new one

commit db7698aa
Merge: bb36af6d c04932d9
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 30 19:03:50 2018 +0100

    Merge remote-tracking branch 'origin/BlueDMA_Updates' into pe-local-memories

commit bb36af6d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 30 18:54:30 2018 +0100

    Updated PyNQ benchmark on 2017.4

commit c04932d9
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 18:29:29 2018 +0100

    Fixes MSIx address map

commit f75533a1
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 17:51:47 2018 +0100

    Fixes PCIe clock location constraint

commit 6416ab50
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 17:49:21 2018 +0100

    Fixes DualDMA constraint application

commit 153716a3
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 16:50:25 2018 +0100

    Fixes errors introduced by new connection scheme and new BlueDMA

commit 1466aa9c
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 16:39:44 2018 +0100

    Updates BlueDMA and MSIx Interrupt Controller to newest versions

commit 8040311c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 30 12:55:37 2018 +0100

    Zynq: Fix zero master PE compositions

commit b426ec6c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 19:39:45 2018 +0100

    Fix for zero masters on PEs

commit dcc6c418
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 17:04:51 2018 +0100

    Squashed commit of the following:

    commit 802a3eea
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:58:22 2018 +0100

        CI: Reactivate everything, with new compose-features stage

    commit d0fb3e37
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:55:43 2018 +0100

        F'in yml

    commit 6c8e648d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:53:22 2018 +0100

        YML debugging

    commit 155ed589
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:51:22 2018 +0100

        YML debugging

    commit 4a6408b6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:49:36 2018 +0100

        YML debugging

    commit 1b09ffb8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:47:22 2018 +0100

        Distinguish compose with and without features in jobs

    commit ec2af8ed
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:43:24 2018 +0100

        Reactivate compose jobs

    commit 09d289a8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:41:17 2018 +0100

        Deactivate all jobs but compose without features

    commit 40c7cba6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 11:34:15 2018 +0100

        Fix potential hanging LogTrackingFileWatcher in EvaluateIP

    commit f31d740c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 11:19:20 2018 +0100

        Temporarily increase logging of file watcher (again)

    commit f12a9074
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 10:45:05 2018 +0100

        Fix truncated log output in verbose mode

        * when an activity exits quickly with an error, verbose mode would often
          omit the most important last few lines of the log
        * reason: flushing the data to disk takes longer than for the Tapasco
          threads to die, thus LogTrackingFileWatcher exits before lines appear
        * workaround: when both waitingFor and files are empty, MultiFileWatcher
          now waits one more iteration before exiting, which seems to suffice

    commit f9148c81
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 10:22:09 2018 +0100

        Squashed commit of the following:

        commit d3245516
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Jan 25 10:19:19 2018 +0100

            Closes #149 - Zedboard Synthesis fails for 2017.3 and 2017.4

            * improved sys clock detection by checking available interfaces via
              get_board_part_interfaces, instead of trying sys_diff_clock first
            * also removed second warning when get_bd_pins returns nothing
            * removed old, unused platform code

        commit 9a0fb9b0
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Jan 25 10:18:03 2018 +0100

            Use Arty-Z7-20 board file from Digilent for PyNQ

            * contains the manually set top.xdc directives
            * identical to Pynq, except for peripheral components

        commit f6a25afc
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Jan 25 10:16:28 2018 +0100

            Update board definition for zedboard

            * Digilent has newer def of ZedBoard, using that automatically now
            * imported via MYVIVADO / XILINX_PATH env vars

        commit a29aa6cc
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Jan 25 10:14:39 2018 +0100

            Fix minor bug in PS7 instantiation routine

        commit c782eadc
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Jan 25 10:13:58 2018 +0100

            Remove 2016.4 specific code from design.master.tcl.template

    commit f873c47b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 08:23:54 2018 +0100

        Closes #137 for HLS

    commit 88259aa0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 17:01:44 2018 +0100

        Activate pipelines on branch gitlab-ci

    commit d09278de
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 16:58:38 2018 +0100

        Deactivate sbt-prepare on all except master and 20xx.x branches

    commit 9df2a6a6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 16:54:40 2018 +0100

        Another fix regarding precision_counter

    commit 30f9ac5b
    Merge: c0ed8ed6 fc930ec8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 16:53:33 2018 +0100

        Merge branch 'pe-local-memories' of git:tapasco/tapasco into gitlab-ci

    commit c0ed8ed6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 16:52:05 2018 +0100

        Remove precision_counter from composition

        * caches are not always available, so precision_counter is not
          available, causing runs to fail
        * annoying, removed precision_counter for now

    commit 35b46901
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 15:56:50 2018 +0100

        Restrict CI pipelines to master and 20xx.x branches

    commit 0a0dc675
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 15:45:13 2018 +0100

        Activate verbose output in CI HLS jobs

    commit 240ad939
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 15:33:48 2018 +0100

        Test of generated yml

    commit 4f684b2a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 15:33:32 2018 +0100

        Remove support for Vivado 2016.4

    commit be0a4b94
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 14:54:25 2018 +0100

        Pull tapasco-status 1.21

        * Chisel-generated Verilog is flattened into single module to avoid
          Verilog name conflicts

    commit d668d82b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 14:52:30 2018 +0100

        Fix bug in address map construction

        * internal master-slave connections do not appear in get_address_map
        * so their segments were not mapped, resulting in errors, e.g., for DMA
        * fix: when address map does not contain interfaces, it will try to
          deduce range and offset from properties of the segment instead of
          failing

    commit 86b53707
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 13:45:58 2018 +0100

        Squashed commit of the following:

        commit 39e7a1cb
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Wed Jan 24 13:44:20 2018 +0100

            Bugfix in ZC706 fancontrol plugin

        commit 6a06399b
        Author: Lukas Sommer <lukas.sommer.mail@gmail.com>
        Date:   Wed Jan 24 12:39:49 2018 +0100

            Moved filter condition for active-high resets to correct command;

        commit cba13f81
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Wed Jan 24 11:28:40 2018 +0100

            Arch: Fix bug in PE reset connections

    commit c830c899
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 09:00:20 2018 +0100

        Improve locking behavior of MultiFileWatcher

    commit 58542825
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 08:22:55 2018 +0100

        Reactivate verbose mode in compose

    commit b97700d3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 06:31:23 2018 +0100

        Remove --maxTasks from HLS and Import

    commit 25c503b6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 06:25:15 2018 +0100

        Deactivate resource logging, increase tasks for HLS and import

    commit ac61a13d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 06:19:29 2018 +0100

        Remove tapasco-status building from sbt-prepare job

    commit 4c6f2657
    Merge: 3691ea58 d1f36ab4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 06:15:50 2018 +0100

        Merge branch 'pe-local-memories' of esagitlab:tapasco/tapasco into gitlab-ci

    commit 3691ea58
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Jan 22 14:33:00 2018 +0100

        Change .gitlab-ci.yml to use new maxTasks param

    commit ea7c3934
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Jan 22 14:30:06 2018 +0100

        Closes #147 - Implement maxTasks option

        * now supports --maxTasks command line / JSON option to limit the number
          of parallel tasks executed by TaPaSCo

    commit f8d090ae
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Jan 21 15:32:51 2018 +0100

        Temporarily increase logging to debug OOM problems

    commit 3cb861b2
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Sun Jan 21 12:46:13 2018 +0100

        Limit threads to 1 to remove oom errors

    commit c02630a5
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 18:36:37 2018 +0100

        Adds artifact passing between hls and compose

    commit e2c63695
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 18:02:27 2018 +0100

        Changes for shared caches

    commit 82d85c69
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 17:11:36 2018 +0100

        Try to cache as much as possible

    commit 36be0ac0
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 17:04:08 2018 +0100

        Removes /cache

    commit 6a046f78
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 17:03:27 2018 +0100

        Adds cache_global

    commit fce5833e
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 17:00:42 2018 +0100

        Adds /opt/cad ls for debugging

    commit 0bb7f526
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 16:52:50 2018 +0100

        Adds cache test

    commit 5e410f65
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 16:24:17 2018 +0100

        Removes -v so tapasco finishes

    commit 532b1ba1
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 16:10:45 2018 +0100

        Reverts changes to default image

    commit 25d70ece
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 16:09:42 2018 +0100

        Replaces _JAVA_OPTIONS with SBT_OPTS

            - _JAVA_OPTIONS seems to annoy Vivado HLS and results in random
            crashes

    commit b1bbfe5f
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 14:48:33 2018 +0100

        Compile only one platform for hls

    commit 90adf995
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 14:27:31 2018 +0100

        He said I should add an s

    commit 16664088
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 14:26:19 2018 +0100

        Adds artifact for hls builds

    commit 53f0ae16
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 13:18:53 2018 +0100

        Mkaes hls verbose for debugging

    commit 2becdf3c
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 13:03:15 2018 +0100

        Removes space (and time)

    commit 3a444c26
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 12:03:51 2018 +0100

        Adds check for cache success

    commit cd75f301
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 12:01:16 2018 +0100

        Checks if vivado is included properly

    commit 425b8e98
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 11:48:36 2018 +0100

        Changes sbt-prepare cache policy to push

    commit c2f3b5ac
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 11:47:09 2018 +0100

        Replaces artifacts with cache

            - For now only sbt-prepare is shared for further jobs
            - There should be further sharing between Import and Compose

    commit b2b2d9b6
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 10:52:51 2018 +0100

        Revert "Fixes #145 - Building status core fails"

        This reverts commit 32047b00.
        The error this commit fixes was already fixed in a new Dockerfile
        version.

    commit 32047b00
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 19 10:40:58 2018 +0100

        Fixes #145 - Building status core fails

    commit 55718f4f
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 17:42:33 2018 +0100

        Removes import as dependency for compose

    commit 89b6f957
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 17:23:25 2018 +0100

        Reduces artifact size by compressing them

    commit 17a28552
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 16:06:44 2018 +0100

        Source Vivado

            For whatever reason .bashrc is not evaluated...

    commit 2cd05d74
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 15:49:46 2018 +0100

        Revert back to targetted artifacts because of size constraints

    commit fb4284aa
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 15:36:41 2018 +0100

        Get all untracked files for prepare stage

    commit 2f87a5f7
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 15:25:29 2018 +0100

        Bin is needed as artifact as well

    commit 29b4cd38
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 15:07:22 2018 +0100

        Limit artifacts to .ivy2 and .sbt

    commit 5524d39a
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 14:55:06 2018 +0100

        Adapts import-template to new format

    commit c53313a0
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 14:52:57 2018 +0100

        Used tapasco image and artifact sbt

    commit 7fd62db1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:58:10 2018 +0100

        Implement import task as pipeline stage

    commit 6e9c33a9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:51:34 2018 +0100

        Improve logging in Zynq platform Tcl

    commit e1758dbb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:51:02 2018 +0100

        Improve logging in platform common Tcl

    commit 090f4481
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:50:32 2018 +0100

        Improve logging in tapasco::ip

    commit a6e9559d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:49:58 2018 +0100

        Activate PE-local memory capability by default

    commit e3682565
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:49:40 2018 +0100

        Bugfix in Arch address map for unconnected masters

    commit b8b5dd0a
    Merge: dd6ac83b 8d677bb7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 07:59:19 2018 +0100

        Pull tapasco-status

        Merge commit '8d677bb7' into gitlab-ci

    commit 8d677bb7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 07:58:18 2018 +0100

        Squashed 'common/ip/tapasco_status/' changes from e209f949..3fd53e7

        3fd53e7 Pull chisel-axi
        41e37e7 Squashed 'axi/' changes from b8f4c554..01fad68
        88624e0 Pull chisel-packaging
        872f551 Squashed 'packaging/' changes from 134b2f62..c22243b
        f94b6de3 Remove caching of ivy repo from pipeline
        43c331dc Pull chisel-axiutils
        5937e2aa Implement cap0 bitfield
        26d61dd6 Bugfix in pipeline
        1030ffe5 Cache ivy2 repo in pipeline builds
        14876b2e Implement support for capability field in Status Core
        2a3e6856 Fix removed '<<=' sbt operator
        bccc8a73 Run sbt test in GitLab pipeline
        17e1a3a7 Fix bug concerning empty slots
        5a089419 Ignore compiled python scripts in .gitignore
        0f0a2d84 Update packaging to GitHub-version of Chisel3
        a162cfae Update miscutils to GitHub-version of Chisel3
        f0265156 Remove ununsed Scalactic dep
        d146b992 Rename RegisterFile saxi port to s_axi

        git-subtree-dir: common/ip/tapasco_status
        git-subtree-split: 3fd53e7038ab7e1ff485eee94c3516f72b9604ea

    commit dd6ac83b
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 21:31:34 2018 +0100

        Adds verbose flag for compose debugging

    commit d5e9bc89
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 21:06:26 2018 +0100

        Fixes job naming in yaml

    commit 9b9304ee
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 21:04:59 2018 +0100

        Use artifacts to avoid reevaluation

    commit fd6843ad
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 20:45:10 2018 +0100

        Removes verbose flag to avoid lock ups

    commit 23f78ad7
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 20:12:12 2018 +0100

        Fixes gitlab-ci with Centos7

    commit 4c73c789
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 19:03:03 2018 +0100

        Change image type to centos

    commit 0b823caa
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 18:22:30 2018 +0100

        Implement stages and HLS

    commit 8e810c8c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 16:33:51 2018 +0100

        Fix

    commit e34de5b8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 16:32:18 2018 +0100

        Fix

    commit 0dbd2a57
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 16:23:07 2018 +0100

        Fix

    commit 408774c9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 16:19:22 2018 +0100

        Fix setup script

    commit 38820724
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 16:16:08 2018 +0100

        Implement automated regression tests

commit d3245516
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:19:19 2018 +0100

    Closes #149 - Zedboard Synthesis fails for 2017.3 and 2017.4

    * improved sys clock detection by checking available interfaces via
      get_board_part_interfaces, instead of trying sys_diff_clock first
    * also removed second warning when get_bd_pins returns nothing
    * removed old, unused platform code

commit 9a0fb9b0
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:18:03 2018 +0100

    Use Arty-Z7-20 board file from Digilent for PyNQ

    * contains the manually set top.xdc directives
    * identical to Pynq, except for peripheral components

commit f6a25afc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:16:28 2018 +0100

    Update board definition for zedboard

    * Digilent has newer def of ZedBoard, using that automatically now
    * imported via MYVIVADO / XILINX_PATH env vars

commit a29aa6cc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:14:39 2018 +0100

    Fix minor bug in PS7 instantiation routine

commit c782eadc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:13:58 2018 +0100

    Remove 2016.4 specific code from design.master.tcl.template

commit fc930ec8
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 24 16:45:59 2018 +0100

    Fix bug in BlueDMA plugin

    * plugin could not change VLNV for dual_dma due to new location of
      stdcomps

commit 39e7a1cb
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 24 13:44:20 2018 +0100

    Bugfix in ZC706 fancontrol plugin

commit 6a06399b
Author: Lukas Sommer <lukas.sommer.mail@gmail.com>
Date:   Wed Jan 24 12:39:49 2018 +0100

    Moved filter condition for active-high resets to correct command;

commit cba13f81
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 24 11:28:40 2018 +0100

    Arch: Fix bug in PE reset connections

commit d1f36ab4
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 23 06:09:44 2018 +0100

    Closes #148 - Replace tapasco-status subtree by .jar

commit ee793881
Merge: bbae0376 82ce7119
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon Jan 22 18:58:46 2018 +0100

    Pull tapasco-status

    Merge commit '82ce7119' into pe-local-memories

commit 82ce7119
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon Jan 22 18:58:17 2018 +0100

    Squashed 'common/ip/tapasco_status/' changes from e209f949..5b218b0

    5b218b0 Pull chisel-axi
    7cecbce Squashed 'axi/' changes from 01fad68..ec8f7a2
    e56e93c Pull chisel-packaging
    0e3cc98 Squashed 'packaging/' changes from c22243b..e6a5a78
    4e421af Add assembly fatjar packaging, increase version to 1.0
    41e37e7 Squashed 'axi/' changes from b8f4c554..01fad68
    3fd53e7 Pull chisel-axi
    872f551 Squashed 'packaging/' changes from 134b2f62..c22243b
    88624e0 Pull chisel-packaging
    f94b6de3 Remove caching of ivy repo from pipeline
    43c331dc Pull chisel-axiutils
    5937e2aa Implement cap0 bitfield
    26d61dd6 Bugfix in pipeline
    1030ffe5 Cache ivy2 repo in pipeline builds
    14876b2e Implement support for capability field in Status Core
    2a3e6856 Fix removed '<<=' sbt operator
    bccc8a73 Run sbt test in GitLab pipeline
    17e1a3a7 Fix bug concerning empty slots
    5a089419 Ignore compiled python scripts in .gitignore
    0f0a2d84 Update packaging to GitHub-version of Chisel3
    a162cfae Update miscutils to GitHub-version of Chisel3
    f0265156 Remove ununsed Scalactic dep
    d146b992 Rename RegisterFile saxi port to s_axi

    git-subtree-dir: common/ip/tapasco_status
    git-subtree-split: 5b218b00f8f27f40c6cda836ddde5462f4296d33

commit bbae0376
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 19 18:52:52 2018 +0100

    Implement reading of status core regs for memories

commit 052a692a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 18 13:51:34 2018 +0100

    Improve logging in Zynq platform Tcl

commit 2d997d02
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 18 13:51:02 2018 +0100

    Improve logging in platform common Tcl

commit 0a48d743
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 18 13:50:32 2018 +0100

    Improve logging in tapasco::ip

commit 5c397f7d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 18 13:49:58 2018 +0100

    Activate PE-local memory capability by default

commit 44d4f975
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 18 13:49:40 2018 +0100

    Bugfix in Arch address map for unconnected masters

commit 6ea82dc4
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 16 15:16:27 2018 +0100

    Closes #137 - TaPaSCo is stuck after all jobs finished in verbose mode

commit 961d9bc6
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 12 16:38:09 2018 +0100

    Vivado/HLS: delete logfile before watching

commit b4311e00
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 12 16:37:19 2018 +0100

    Add temporary support for 2017.3/4

commit beb71c3d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 12 16:34:58 2018 +0100

    Rebuild all Platforms using new skeleton

    * rebuilt PyNQ, zedboard and ZC706 without features
    * expanded subsystem package: standard and custom subsystems can be
      fetched (as bd cells) and their names queried (incl. custom)
    * Zynqs adapt the memory system to bypass
    * need to run more tests, but looks good
    * timing problems in VC709, need to investigate

commit 6cb43d23
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 12 10:04:23 2018 +0100

    Improve libmpfr seeking

commit 8a660e3d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 11 16:30:57 2018 +0100

    Fix dual_dma constraints

commit 7ffe7520
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 11 15:34:51 2018 +0100

    Move all IP block related code into new namespace ip

    * tapasco::ip contains methods to instantiate common IP
    * common/ip.tcl automatically generates methods based on the stdcomps
      directory: every name has its own instantiation method called
      create_<name>, which takes only a name as an argument
    * specialized constructors go into common_ip.tcl and can override the
      auto-generated ones
    * removed all createXY procs in common.tcl and fixed all dependent
      scripts accordingly
    * removed ill-fated "clocks_and_resets" bundle - sad, but didn't work
      correctly in Vivado

commit 8d6b2d59
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 11 11:20:24 2018 +0100

    VC709: finish Platform refactoring

    * VC709 designs should build again
    * generalized address mapping, same method should be applicable to other
      Platforms like Zynq, too
    * still WIP, need to move a few bits between implementations

commit c4d81df5
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 10 17:38:57 2018 +0100

    WIP: started to work on generic address mapping

commit 2fba2589
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 10 12:55:15 2018 +0100

    VC709: Fix clock and reset wiring

commit 31e7a81c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 10 10:01:38 2018 +0100

    Fix bug in setup.sh: locate may not be available

commit d675e2be
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 9 18:38:38 2018 +0100

    setup.sh: use locate instead of find

commit 944b8844
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 9 18:38:21 2018 +0100

    WIP: Continue work on new interfaces

commit b33fa803
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 9 18:30:14 2018 +0100

    Fix chiselSetup.sh, build.sbt

commit bd890015
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon Jan 8 16:51:08 2018 +0100

    WIP: remove Bundle interfaces, does not work :-(

    * will need to use individual pins
    * started to move subsystem code to subsystem.tcl

commit 3cdff64a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 20:14:10 2018 +0100

    WIP: reimagine basic Platform construction

    * need to simplify Platform scripts, move more code into a common base
    * will generalize and unify the basic structure of the project
    * does not work yet, but looks promising

commit d04440b0
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 20:12:37 2018 +0100

    Fix bug for Vivado HLS

    * Vivado HLS does not have a -notrace parameter for source command

commit d4c91637
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 20:12:10 2018 +0100

    Implement tapasco::get_vlnv method to get VLNVs

commit 0c33be87
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 20:10:35 2018 +0100

    Add common_ip.tcl as base catalog

    * common_ip.tcl will contain all basic ip VLNVs
    * only differences are recorded in the _20xx.tcl scripts

commit 8a43f455
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 19:56:17 2018 +0100

    Fix problems with clocks and resets bridges

    * found a way to express in IP-XACT that the interfaces are only bridged
      directly; there seems to be no way of doing this via Vivado, but since
      Xilinx is using it themselves (e.g., System Cache) I hope it'll work
    * also remove interconnect_reset port, since they do not exist on the
      reset generators

commit 84c35860
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 10:19:42 2018 +0100

    Implement a bus abstraction for TaPaSCo clocks and resets

    * new interface:
      esa.cs.tu-darmstadt.de:tapasco:tapasco_clocks_resets:1.0
    * bundles host, design and mem clocks and all reset kinds for easier
      connection of the subsystems
    * each subsystem should instantiate a ClocksResetsSlaveBridge to access
      the ports
    * the clocks and resets subsystem uses a ClocksResetsMasterBridge to
      propagate the clocks and resets
    * both IPs are zero-logic direct wire thruputs; only used to allow
      bundling at interface leve

commit 15f96d39
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 16:08:35 2018 +0100

    Implement automatic build process for new Status Core

    * there is a subproject that is included as a subtree in
      common/ip/tapasco_status
    * subproject is standalone and can be run from Tcl
    * changed process in common.tcl: createTapascoStatus now generates a
      JSON configuration file and runs sbt in the subproject
    * each Composition gets its unique status core
    * status cores are cached in tapasco-status-cache in the main dir:
      when building the same composition a number of times, status cores can
      be reused; is removed automatically in sbt clean
    * required more API extensions: platform::get_address_map must be
      implemented by the Platform to communicate the address mapping to the
      status core creation
    * also added formal interface to capabilities in common.tcl:
      tapasco::add_capability_flag, tapasco::get_capability_flags and
      tapasco::set_capability_flags can be used by plugins to activate
      capability bits
    * whole process should be transparent to the user, everything is
      supposed to work as before
    * one exception: get_address_map is not yet implemented on VC709

commit decea9b9
Merge: d5704092 f94b6de3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:53:24 2018 +0100

    Pull tapasco-status-chisel

    Merge commit 'f94b6de3' into pe-local-memories

commit d5704092
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:52:36 2018 +0100

    Ignore tapasco-status-cache temp dir

commit f94b6de3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:46:52 2018 +0100

    Remove caching of ivy repo from pipeline

    * following an internal discussion, we'd rather be sure to build
      everything from scratch in the runner, or version hell ensues

commit 43c331dc
Merge: 5937e2aa 5a089419
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:39:09 2018 +0100

    Pull chisel-axiutils

    Merge commit '5a089419'

commit 5937e2aa
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:38:31 2018 +0100

    Implement cap0 bitfield

commit 26d61dd6
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:37:35 2018 +0100

    Bugfix in pipeline

commit 1030ffe5
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:34:11 2018 +0100

    Cache ivy2 repo in pipeline builds

commit 14876b2e
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:33:13 2018 +0100

    Implement support for capability field in Status Core

commit 2a3e6856
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 10:59:11 2018 +0100

    Fix removed '<<=' sbt operator

commit bccc8a73
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 10:41:06 2018 +0100

    Run sbt test in GitLab pipeline

commit 17e1a3a7
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 10:29:56 2018 +0100

    Fix bug concerning empty slots

    * empty slots did not exist at all, resulting in reads/writes causing
      bus errors, crash
    * new Slot type Empty represents an empty slot
    * slots in status configuration are filled with empty slots to fix the
      problem
    * should not increase the size significantly; all empty slots are
      represented by the same ConstantRegister

commit 5a089419
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jan 4 10:02:42 2018 +0100

    Ignore compiled python scripts in .gitignore

commit 0f0a2d84
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jan 4 10:02:00 2018 +0100

    Update packaging to GitHub-version of Chisel3

commit a162cfae
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jan 4 10:01:32 2018 +0100

    Update miscutils to GitHub-version of Chisel3

commit f0265156
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jan 4 10:00:45 2018 +0100

    Remove ununsed Scalactic dep

commit d146b992
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jan 4 10:00:13 2018 +0100

    Rename RegisterFile saxi port to s_axi

commit a68c751e
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 15:40:04 2018 +0100

    Automatically use libmpfr.so workaround on Ubuntu

commit 56210a05
Merge: 225cfa31 e209f949
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:43:05 2018 +0100

    Add 'common/ip/tapasco_status/' from commit 'e209f949'

    git-subtree-dir: common/ip/tapasco_status
    git-subtree-mainline: 225cfa31
    git-subtree-split: e209f949

commit 225cfa31
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:42:28 2018 +0100

    Change Tapasco Status Core VLNV to new Chisel version

commit 944327d2
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:42:06 2018 +0100

    Remove Verilog implementation of Tapasco Status Core

commit e209f949
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:37:19 2018 +0100

    Ignore test and chisel3 directories at top level

commit 18559a40
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:35:21 2018 +0100

    Fix minor bug in chiselSetup.sh

commit 6194279d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:35:07 2018 +0100

    Remove chisel3 libs on sbt clean

commit dad7a067
Merge: b98b7616 a9f329c5
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:21:32 2018 +0100

    Pull chisel-axi updates

    Merge commit 'a9f329c5'

commit b98b7616
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:21:09 2018 +0100

    Automatically build Chisel3 dev libs

commit a9f329c5
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jan 3 09:19:49 2018 +0100

    Bugfix for latest Chisel3

    * zero-width io ports must be assigned, or compilation will fail
    * fixed RegisterFileSpec accordingly
    * updated to Scala 2.11.12

commit 7adf7220
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 08:33:48 2018 +0100

    Ignore compiled python scripts

commit da655ea7
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 08:31:37 2018 +0100

    Implement spec tests for RTL behavior

    * re-used generic test from RegisterFile
    * status configuration is generated by spec gens

commit 5533df8a
Merge: 91193a3a 8d79675d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 08:19:26 2018 +0100

    Pull chisel-axi

    Merge commit '8d79675d'

commit 8d79675d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jan 3 08:16:17 2018 +0100

    Move generic test to companion for reusability

commit ce2bad61
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jan 3 08:10:04 2018 +0100

    Update play-json dependency

commit 91193a3a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 19:50:03 2018 +0100

    Move to latest development versions of Chisel3

commit 3cf2bdac
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 19:49:47 2018 +0100

    Move to latest development versions of Chisel3

commit d928c364
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 19:49:22 2018 +0100

    Move to latest development versions of Chisel3

commit af6fc853
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 19:47:30 2018 +0100

    Implement Builder to generate IP core from JSON

    * Builder class main uses first argument as path to JSON config file
    * IP Core is generated under ip/ hierarchy: each configuration hash is
      unique and can be used to cache products
    * sbt clean removes this cache
    * example.json contains an example configuration

commit 10730b41
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 18:31:38 2018 +0100

    Structure JSON SerDes code

commit cc738039
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 18:17:11 2018 +0100

    Implement spec testing for Json SerDes

    * JsonSpec checks that roundtrips to and from Json preserve all data
    * generators package contains ScalaCheck generators

commit 6f821d5f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 18:13:07 2018 +0100

    Finish draft for TaPaSCo status core configurations

    * Status contains complete configuration, including kernel ids, memory
      slots and some basic sanity checking
    * json package contains JSON SerDes functionality

commit 0ddba2f3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 12:32:45 2018 +0100

    Start to draft the IP core

    * started with external format (JSON)
    * noticed a problem: without Verilog module parameters Features cannot
      easily add capabilities etc.
    * postponing the project until later

commit 0ec5077d
Merge: 1846cfbe 134b2f62
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 10:24:25 2018 +0100

    Add 'packaging/' from commit '134b2f62'

    git-subtree-dir: packaging
    git-subtree-mainline: 1846cfbe
    git-subtree-split: 134b2f62

commit 1846cfbe
Merge: bea8ec99 b8f4c554
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 10:20:23 2018 +0100

    Add 'axi/' from commit 'b8f4c554'

    git-subtree-dir: axi
    git-subtree-mainline: bea8ec99
    git-subtree-split: b8f4c554

commit bea8ec99
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 10:20:02 2018 +0100

    README.md

commit cdc16d33
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Dec 29 19:32:20 2017 +0100

    Zynq: Fix address map

    * PE-local memory segments should be inserted after ctrls
    * needs fixing in VC709, too

commit 7936dadd
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Dec 29 18:54:40 2017 +0100

    Add registers to TaPaSCo status core for local mems

    * register after kernel id is reserved for memory size
    * 0xFFFFFFFF indicates no local memory available at the slot
    * smaller values are 0xFFFFFFFF - size
    * added capability flag in core, defaults to on from 2018.1

commit dcda2256
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Dec 29 15:52:33 2017 +0100

    Implement basic flags and errors for PE-local memories

commit b8f4c554
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Dec 29 14:17:08 2017 +0100

    Fix bug in Register implementation

    * width would not be propagated correctly
    * fixed, also changed standard write test to increase by 1 from offset,
      making accidental correctness less likely

commit 886e04b9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Dec 29 11:28:43 2017 +0100

    Change address base type to Long

    * addresses can be larger than 32bit, thus need to use Long
    * in fact, having the upper-most bit 1 already gave problems
    * fixed and updated all dependents

commit 70928314
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Dec 29 10:36:59 2017 +0100

    Add restart input to ProgrammableMaster

    * while high, won't execute any actions, but reset its step counter

commit 0b91c23a
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Dec 29 10:36:45 2017 +0100

    Move ProgrammableMaster to main

commit cd96aee5
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 28 11:25:28 2017 +0100

    Make ProgrammableMaster startable

    * if constructor argument is given, will start sequence only while
      io.start is high
    * default is false for startable

commit ed7185ff
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Dec 27 17:23:54 2017 +0100

    Add default implementations for VirtualRegister

    * read returns None by default
    * write returns the write value by default, does nothing

commit 17e328ed
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Dec 27 17:21:54 2017 +0100

    RegisterFile: Move behavior into method

    * behavior cannot be generated statically, because VirtualRegisters
      would then be unable to access values and regs of the module
    * behavior is now generated by RegisterFile.behavior and
      RegisterFile.resetBehavior instead
    * fixed definition of generic registerfile (no custom IO, regs, etc.)

commit 05b3795f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Dec 27 11:01:35 2017 +0100

    Remove accidental swap files

commit 930e85ba
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Dec 20 18:28:12 2017 +0100

    Fix build.sbt

commit c8eea4e8
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Dec 20 18:27:40 2017 +0100

    Implement short-hand for named bits

commit 134b2f62
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:30:09 2017 +0100

    Fix bugs in package.py regarding modules with interfaces

    * missing top-level import fixed
    * VLNVs for bus interfaces fixed
    * package.tcl is now written to disk, contains the script (for
      debugging)

commit 4a038ecf
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:30:09 2017 +0100

    Fix bugs in package.py regarding modules with interfaces

    * missing top-level import fixed
    * VLNVs for bus interfaces fixed
    * package.tcl is now written to disk, contains the script (for
      debugging)

commit 896634de
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:29:43 2017 +0100

    ModuleBuilder: add explicit top-level-module name

commit a5c36c57
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:29:43 2017 +0100

    ModuleBuilder: add explicit top-level-module name

commit 41fa107a
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:29:16 2017 +0100

    Bugfix in CoreDefinition: Interfaces were not passed correctly

commit b93801d4
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:29:16 2017 +0100

    Bugfix in CoreDefinition: Interfaces were not passed correctly

commit 5b56956d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:26:44 2017 +0100

    Fix LargeRegisterFile example module

    * needs own class to change TLM name in Verilog
    * added AXI interface definition

commit 793c88df
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 20:11:41 2017 +0100

    Fix bug concerning too narrow address widths in RegisterFile

    * arbitrary configs would sometimes mandate less bits for the address
      than required by the register map
    * could be fixed in the register map generator, but I opted to fix it by
      permanently widening the address to 32 bits (sufficient for all cases)

commit 4286de8c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:58:07 2017 +0100

    Implement 256 register file r/w for testing purposes

    * manually tested with Xilinx AXI Verification IP, looks fine

commit 04dddcf9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:57:43 2017 +0100

    Fix renamed addrGranularity -> addressWordBits

commit 0039dd2f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:56:12 2017 +0100

    Fix BitRange overlap logic in RegisterFile and provide better errors

commit 325673de
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:52:23 2017 +0100

    Fix reset behavior in RegisterFile

    * AXI mandates that all ready signals be low during reset
    * unfortunately, not only is this not the case in Queues, but they
      actively start working while reset is high (insane)
    * fixed by manually pulling the signals low on reset
    * tested with Xilinx AXI Verification IP, all's well

commit 5db38ae2
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:49:37 2017 +0100

    Fix uninitialized wires in FifoAxiAdapter

commit f93ae122
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:48:52 2017 +0100

    Simplify overlap logic in BitRange

commit 57c18b2b
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:46:01 2017 +0100

    Fix uninitialized wires in Mux

commit 9d650848
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:45:31 2017 +0100

    Fix uninitialized wires in AxiFifoAdapter

commit 99699663
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:44:56 2017 +0100

    Implement wire defaults for AXI4 interfaces

commit f26ba638
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Dec 12 18:11:07 2017 +0100

    Finish streamlined implementation of RegisterFile

    * entirely based on Queues now, fixed firing logic
    * still with workaround for problem in Queue with optional fields
    * simplified ProgrammableMaster
    * changed Registers write method to return Response instead of Boolean
    * switched completely to Spec testing: register files are generated
      ad-hoc, corresponding master program and testing steps are
      automatically generated

commit effaef3e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Dec 12 17:10:53 2017 +0100

    Bugfix registerMapGen: always uses same instances

    * register map contained always the same instances for each kind
    * core problem: the new ... generators are implicitly converted to const
    * fixed by adding random Gen element to both generators

commit f175bf4e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Dec 11 17:55:29 2017 +0100

    Move to dev versions of Chisel3 and iotesters

commit 3b80a251
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Dec 11 17:55:06 2017 +0100

    Fix problems in ProgrammableMaster regarding uninits

commit c7de8149
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Dec 11 17:53:35 2017 +0100

    RegisterFile: rewrite with Queues

    * replaced FSM approach with Queues; each channel has its own Queue, and
      all is handled using the handshakes
    * simple, because 1-cycle reads and writes can be guaranteed

commit c74b8a56
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Dec 11 17:53:01 2017 +0100

    Implement wire defaults for Axi4Lite sub-bundles

commit ee598c83
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Dec 11 17:52:25 2017 +0100

    Add AnyVals from Scalactic

commit a24a7684
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Dec 10 01:59:40 2017 +0100

    Fixed naming issues in packages

    * new scheme: chisel.axi is the main package
    * chisel.axi.Axi4 contains the full axi defs
    * chisel.axi.Axi4Lite contains the lite defs
    * chisel.axi.axi4 contains full Axi4 impls
    * chisel.axi.axi4lite contains lite impls
    * same applies for the generators, matching structure

commit bb347461
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Dec 10 01:44:32 2017 +0100

    WIP: Implement generic spec testing for RegisterFile

    * moved DataWidth from top axi to Axi4/Axi4Lite objects
    * cleaned generators, adopted new naming structure
    * implemented generators for arbitrary register files
    * master actions improved, simpler constructors
    * master actions can be automatically generated from register file
    * need to clean up the namespaces etc. - gotten really messy

commit 318d789b
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Dec 8 16:21:25 2017 +0100

    Fix test problems in RegisterFileSpec

    * fixed some issues in ProgrammableMaster regarding wrong types of the
      response channels (was using old approach, direct UInt)
    * fixed some issues in the register file spec, regarding peek/poke of
      non-IO fields, tests are functional

commit 1de898c4
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 7 14:02:01 2017 +0100

    Fix compilation issues in ProgrammableMaster

commit 72ee604c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 7 14:01:10 2017 +0100

    Fix generators import in axi4lite.generators

commit af185bae
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 7 14:00:04 2017 +0100

    Aggregate projects to make clean apply to all

commit 6394501a
Merge: e8e1cf67 1fee5bb1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Dec 2 07:48:50 2017 +0100

    Merge chisel-miscutils

    Merge commit 'e9ddda06381e35f203a5692dcd6395852424cb38'

commit e8e1cf67
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Oct 11 12:36:46 2017 +0200

    Implement generators for ScalaCheck for AXI configurations

commit 7fa3b107
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Oct 11 12:34:38 2017 +0200

    RegisterFile: remove reset logic

commit ceb82b5c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Oct 11 12:33:22 2017 +0200

    SlidingWindow: Remove reset logic

commit e3a6000c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Oct 11 12:32:53 2017 +0200

    Mux: remove reset logic

commit d8e4d2c7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Oct 11 12:31:18 2017 +0200

    Add read and write to Axi masters / addresses

commit 6f84679d
Merge: b351de03 c734b464
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 22 13:34:11 2017 +0200

    Merge chisel-miscutils

    Merge commit '48f930ee8d5d702ff5b29577c8dc13aef4b5363d'

commit c734b464
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 22 13:34:11 2017 +0200

    Squashed 'miscutils/' changes from 5041968..e9ddda0

    e9ddda0 Remove direct references of reset

    git-subtree-dir: miscutils
    git-subtree-split: e9ddda06381e35f203a5692dcd6395852424cb38

commit 1fee5bb1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 22 13:30:32 2017 +0200

    Remove direct references of reset

commit b351de03
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 31 08:50:18 2017 +0200

    !WIP! Refactor all components

commit 4ee69876
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 31 08:46:37 2017 +0200

    Add test/ to cleanFiles

commit 11694b7d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 11:05:16 2017 +0200

    Squashed 'miscutils/' changes from fa152fd..5041968

    5041968 SlowQueue: remove direct reset references
    bc2de4a Minimize SignalGenerator
    91f6202 Minimize DecoupledDataSource
    435a442 Minimize DataWidthConverter logic

    git-subtree-dir: miscutils
    git-subtree-split: 5041968ba66ec8c5329d7da6594b3f031437730d

commit 6064ffaf
Merge: f581c158 11694b7d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 11:05:16 2017 +0200

    Merge chisel-miscutils

    Merge commit '17ce5f15e119b08bf38d87c1276f001b9ff0d11d'

commit f581c158
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 11:02:24 2017 +0200

    Write FifoAxiAdapter specification

    *  basic tests implemented
    *  peekAt/pokeAt do not work; took a lot of time to figure out
    *  need to implement a workaround using a serial interface
    *  introduces its own problems, *sigh*

commit 2685786a
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 10:53:20 2017 +0200

    SlowQueue: remove direct reset references

commit 57bf9a77
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 10:52:16 2017 +0200

    Minimize SignalGenerator

    *  direct reference of reset is discouraged
    *  replaced explicit reset code with RegInits

commit 7395f54f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 10:39:41 2017 +0200

    Minimize DecoupledDataSource

    *  direct references of reset are discouraged
    *  replaced all direct refs with RegInits, where appropriate
    *  fixed overwrite bug in test outputs, each test writes in separate dir

commit 8e94f119
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 10:21:12 2017 +0200

    Minimize DataWidthConverter logic

    * direct reference of reset is discouraged
    * replaced all direct references with RegInits or removed reset
    * fixed overwrites of test runs (now each in separate dir)
    * added test directory to cleanFiles, will be removed on sbt clean

commit dc850c61
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Aug 29 14:21:25 2017 +0200

    Squashed 'miscutils/' changes from 5bda007..fa152fd

    fa152fd Cosmetic changes: Move IO defs to companion objects
    37a4949 Minor fix in valid signal

    git-subtree-dir: miscutils
    git-subtree-split: fa152fd8210a13bfb8024ae569b440ac247ccb73

commit df0710b6
Merge: 357a3810 dc850c61
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Aug 29 14:21:25 2017 +0200

    Merged chisel-miscutils

    Merge commit 'c60f21734856c5828fd574bffe7c6e31acf1c942'

commit d1530d38
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Aug 29 14:18:56 2017 +0200

    Cosmetic changes: Move IO defs to companion objects

commit cf989d9c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Aug 29 14:00:55 2017 +0200

    Minor fix in valid signal

commit 357a3810
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Aug 28 18:43:05 2017 +0200

    More refactoring, started work on FifoAxiAdapterSpec

commit 441095fb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Aug 28 18:12:34 2017 +0200

    Refactoring, clean-up

    *  split into subpackages axi4 and axi4lite
    *  moved each module into its subpackage
    *  shortened names by removing Axi-prefixes wherever possible
    *  moved Configs and IOs into corresponding companion object
    *  replaced some printlns/printfs with Logging facilities

commit ce2a5d30
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 26 16:55:54 2017 +0200

    Squashed 'miscutils/' changes from c428dca..5bda007

    5bda007 DecoupledDataSource: repeat and non-pow2 sizes
    f6b927d Implement logging for Modules

    git-subtree-dir: miscutils
    git-subtree-split: 5bda007e1425eb09deb475dbe2e19849415f7a69

commit 82e7d31a
Merge: 03be2246 ce2a5d30
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 26 16:55:54 2017 +0200

    Merged chisel-miscutils

    Merge commit 'fe9856d869b808e52fc1a27225f684c78b392230'

commit 77b40f09
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 26 16:52:51 2017 +0200

    DecoupledDataSource: repeat and non-pow2 sizes

    * repeat now also works with size which are not a power of 2
    * more complex Mux logic is only generated in case size is not a power
      of 2, otherwise identical as before
    * cleaned up a little and used new logging facilities to implement
      fine-grained info at each consumption

commit 0e19c7ff
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 26 16:50:20 2017 +0200

    Implement logging for Modules

    * implemented both hardware (runtime) logging and constructor logging
      (compile time)
    * mix-in trait Logging provides methods info, warn and error (and cinfo,
      cwarn, cerror resp. for constructor logging)
    * logging level is controlled by implicit Logging.Level, determined at
      each call, allows for selective logging

commit 03be2246
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 18:40:33 2017 +0200

    !WIP! still working on fixing Axi

commit 20323ee9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:44:18 2017 +0200

    Squashed 'miscutils/' changes from 6b570c6..c428dca

    c428dca Decreased number of tests for DataWidthConverter
    3f395f6 Bugfix concerning log2Ceil(1) == 0
    0092287 Replace unit tests for DataWidthConverter with property spec
    9ffa2fe Finish data width converter correctness spec
    435ee4b Work on generator for valid data width conversions
    f91ed9f Start implementation of data width conversion spec
    1d57540 Improve debug output of DecoupledDataSource
    4a4a7d2 Replace DecoupledDataSource testing with prop check
    9da9dc5 Finish replacement of SignalGenerator tests
    aeee2cd Started with property-based testing
    20c08e2 Fix bug in DecoupledDataSource, remove crossVersions

    git-subtree-dir: miscutils
    git-subtree-split: c428dca006d0aa62d25c83ffdffad8baf229bcfb

commit 8f2faf2e
Merge: 511f7779 20323ee9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:44:18 2017 +0200

    Merge of chisel-miscutils

    Merge commit '61fdb4b48f81caf5ae3e68aead564fb34a2c4371'

commit f127f8f0
Merge: 46bd95d9 5a3d0f79
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:43:06 2017 +0200

    Merge of chisel-packaging

    Merge commit '2f16edbf19e62a15e4770e960b05be552770e6d5'

commit 511f7779
Merge: 2cd5e201 a8d00c84
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:43:06 2017 +0200

    Merge of chisel-packaging

    Merge commit '2f16edbf19e62a15e4770e960b05be552770e6d5'

commit a8d00c84
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:43:06 2017 +0200

    Squashed 'packaging/' changes from 7854cfd1..5a3d0f79

    5a3d0f79 Postfix issue, feature warnings activated
    fc967e4c Update to Scala 2.11.11
    ad1c4c32 Support for manual AXI-mapping, postBuildOps fix
    fa4bfbeb Fix README.md markdown syntax

    git-subtree-dir: packaging
    git-subtree-split: 5a3d0f79

commit 2cd5e201
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:40:47 2017 +0200

    Start port to Chisel3

commit 85e229eb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:36:55 2017 +0200

    Decreased number of tests for DataWidthConverter

commit 5702af68
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:33:56 2017 +0200

    Bugfix concerning log2Ceil(1) == 0

commit a09d132d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 11:39:36 2017 +0200

    Replace unit tests for DataWidthConverter with property spec

    * replaced unit test with much more generic property specs
    * also refactored test classes into module-subpackages

commit 52b5a373
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 08:12:56 2017 +0200

    Finish data width converter correctness spec

commit 8d7db075
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 07:28:55 2017 +0200

    Work on generator for valid data width conversions

commit 43beb5b4
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 07:26:34 2017 +0200

    Start implementation of data width conversion spec

commit d428bf8c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 15:55:09 2017 +0200

    Improve debug output of DecoupledDataSource

commit 44b5908e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 15:52:24 2017 +0200

    Replace DecoupledDataSource testing with prop check

    * defined generic property for DecoupledDataSource:
    * testing correctness (correct order + value of data), handshakes (wait
      while consumer is not ready) and repeat behavior
    * running random tests over arbitrary bitwidth, size and repeat flags

commit b3857489
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 15:18:02 2017 +0200

    Finish replacement of SignalGenerator tests

    * finished implementation of property based testing with random
      generators, much more thorough than the previous tests
    * implemented both regular clock input and generated random clock input

commit 187a74fb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 13:38:00 2017 +0200

    Started with property-based testing

commit 63498417
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 08:10:54 2017 +0200

    Fix bug in DecoupledDataSource, remove crossVersions

commit 5a3d0f79
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 08:01:40 2017 +0200

    Postfix issue, feature warnings activated

commit fc967e4c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 23 17:20:09 2017 +0200

    Update to Scala 2.11.11

commit 8d7821f5
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 23 13:31:55 2017 +0200

    Port to Chisel 3

commit ad1c4c32
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Aug 22 18:36:06 2017 +0200

    Support for manual AXI-mapping, postBuildOps fix

    * postBuildActions can no longer use the Module instance directly, since
      Chisel3 prohibits its instantiation outside of a Driver
    * added a configuration object of type Any instead, which will be passed
      to the postBuildActions - we do not actually need the Module instance,
      only the configuration options passed to it
    * Chisel3 no longer supports renaming of top-level ports (setName has
      vanished); auto-inference of the AXI-interfaces is not possible
      without renaming
    * fixed by adding interface definitions to CoreDefinition:
    * each module may declare "known" interfaces; in this case the IP-XACT
      Tcl will match to the generated port names manually

commit fa4bfbeb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 18 16:50:58 2017 +0200

    Fix README.md markdown syntax

commit 8a742587
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:42:23 2017 +0200

    Squashed 'miscutils/' changes from 6d4e97b..6b570c6

    6b570c6 Fix bug in DecoupledDataSourceSuite
    dee2777 Update README.md
    ad4e6f3 README.md edited online with Bitbucket
    3528414 Update to Chisel 3.0 (SNAPSHOT)

    git-subtree-dir: miscutils
    git-subtree-split: 6b570c6a26a7707719404beace67a289289c90ed

commit 48cb64c9
Merge: 641d8456 8a742587
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:42:23 2017 +0200

    Merge commit '537797a1709f872129c78d22b07ad42ab469c1cf'

    Pulled chisel-miscutils.

commit 46bd95d9
Merge: a4d7be88 7854cfd1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:41:25 2017 +0200

    Merge commit '69c3892a214fd740dd605d864fdd88f70a4c7dfd'

    Pulled chisel-miscutils.

commit c5f977bc
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:41:25 2017 +0200

    Squashed 'packaging/' changes from 99804e52..7854cfd1

    7854cfd1 Update README.md - fix dead link
    b992dd73 README.md edited online with Bitbucket
    f15683a7 Update README.md
    fdfd1420 Update README.md
    2190c490 Write README.md
    4531adea Update to Chisel 3.0 (SNAPSHOT)

    git-subtree-dir: packaging
    git-subtree-split: 7854cfd1

commit 641d8456
Merge: 356808da c5f977bc
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:41:25 2017 +0200

    Merge commit '69c3892a214fd740dd605d864fdd88f70a4c7dfd'

    Pulled chisel-miscutils.

commit 356808da
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:41:00 2017 +0200

    Update to chisel3

commit 9749d045
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jul 13 18:53:30 2017 +0200

    Fix bug in DecoupledDataSourceSuite

    * chisel3 is a little finicky with peek/poke: it seems only stuff in the
      io bundle of modules is really safe
    * needed to replace peeking in the internal mems, since that seems
      to crash the LoFirrtlEvaluator
    * all tests functional again

commit 04f0a4d7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 16:11:28 2017 +0200

    Update README.md

commit cc23217a
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 14:05:47 2017 +0000

    README.md edited online with Bitbucket

commit 7854cfd1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 15:29:01 2017 +0200

    Update README.md - fix dead link

commit b992dd73
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 13:25:06 2017 +0000

    README.md edited online with Bitbucket

commit f15683a7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 12:58:01 2017 +0000

    Update README.md

commit fdfd1420
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 12:45:55 2017 +0000

    Update README.md

commit 2190c490
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 12:25:13 2017 +0000

    Write README.md

commit 9f3c5835
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 07:01:04 2017 +0200

    Update to Chisel 3.0 (SNAPSHOT)

commit 4531adea
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 7 17:22:29 2017 +0200

    Update to Chisel 3.0 (SNAPSHOT)

commit b8d8f0e1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:44:09 2016 +0200

    Define proper subprojects in build.sbt

    * miscutils, packaging are subprojects which are depended upon
    * configured correspondingly in build.sbt, removed symlinks in src
    * defined metadata for build artifact (incl. version)
    * updated .gitignore to ignore temp files in subprojects

commit f9b1ffdb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:39:16 2016 +0200

    Squashed 'miscutils/' changes from 0fec184f..6d4e97b

    6d4e97b Add build.sbt to define artifact

    git-subtree-dir: miscutils
    git-subtree-split: 6d4e97bfae9ff6dcb1f106ca6dd94bf086d40c77

commit 24c23140
Merge: e39c6df7 f9b1ffdb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:39:16 2016 +0200

    Merge commit '671c7e7c48474bfe51815e56fbabb0f68151c617'

commit a4d7be88
Merge: eac01b7a 99804e52
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:38:44 2016 +0200

    Merge commit '972b1fb317c33c96523a9b48775f470c9d0faf03'

commit 9db79f78
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:38:44 2016 +0200

    Squashed 'packaging/' changes from d2df30ff..99804e52

    99804e52 Add build.sbt to define artifact
    401df026 Add support for post-build actions

    git-subtree-dir: packaging
    git-subtree-split: 99804e52

commit e39c6df7
Merge: 3d7635a0 9db79f78
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:38:44 2016 +0200

    Merge commit '972b1fb317c33c96523a9b48775f470c9d0faf03'

commit 1ebdde01
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:28:15 2016 +0200

    Add build.sbt to define artifact

commit 99804e52
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Sat Oct 1 09:26:23 2016 +0200

    Add build.sbt to define artifact

commit 3d7635a0
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 30 19:33:00 2016 +0200

    Axi4LiteRegisterFile: Implement config register file

    * AXI4Lite interface
    * flexible ControlRegister class hierarchy: constants, single values,
      virtual registers (callbacks)
    * implemented unit test cases
    * had to implement Axi4LiteProgrammableMaster for batch testing

commit eac01b7a
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 30 19:31:47 2016 +0200

    Add support for post-build actions

commit 401df026
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Sep 30 19:31:47 2016 +0200

    Add support for post-build actions

commit bf5ca040
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 30 19:31:47 2016 +0200

    Add support for post-build actions

commit 2ae7b74d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Sep 28 17:09:07 2016 +0200

    AxiSlidingWindow: reverse order in window

commit 992c37c2
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Sep 18 13:26:54 2016 +0200

    Implement generic, round-robin Axi Mux

    * muxes N AXI-MM masters to one AXI-MM slave
    * read and write channels are mux'ed independently
    * no interruptions during bursts, next schedule on LAST
    * address valid is used to signal transfer requests
    * may cost up to N-1 cycles latency

commit 410607d7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Sep 14 20:26:01 2016 +0200

    AXIMasterIF: renameSignals with prefix and suffix

    * renameSignals on AXI bundle should support prefix and suffix in order
      to accomodate multiple instance of the interface in one module

commit 962277e9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Sep 14 10:19:13 2016 +0200

    Implement AxiSlidingWindow module

    * configurable sliding window module with AXI DMA backend
    * uses AxiFifoAdapter internally to retrieve data from AXI slave
    * shifts with Decoupled interface
    * generic module for arbitrary bitwidths / data types

commit 9ea813c5
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Sep 14 10:17:24 2016 +0200

    AxiSlaveModel: Add companion object

    * has method to fill AxiSlaveModel with structured data for testing

commit 1e69313e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Sep 12 10:39:31 2016 +0200

    AxiFifoAdapter: Clean-up configuration

    * moved config params into sealed case class
    * unified constructors to use new config object
    * added companion object for convenience constructors (backward
      compatible)
    * changed constructor calls in unit tests accordingly

commit a5b8e23c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 2 15:51:36 2016 +0200

    FifoAxiAdapter: implement size parameter

    * size parameter indicates automatic address wrapping
    * no need for resets in between (not always feasible)
    * wraps on overflow to current value of `base` input

commit d011dbf5
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 2 15:49:52 2016 +0200

    Add memory access functions for AXI slave model

    * new methods allow getter access via address or index
    * set method supports writing at address

commit 928b15f9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 2 15:48:51 2016 +0200

    Implement memory dumping for AXI slave models

commit e23188d9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 27 12:21:33 2016 +0200

    Squashed 'miscutils/' content from commit 0fec184f

    git-subtree-dir: miscutils
    git-subtree-split: 0fec184f

commit 52108c3e
Merge: b3c0eff4 e23188d9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 27 12:21:33 2016 +0200

    Merge commit '9a26aa5c3479f3bc887be835aa73a078d7584fac' as 'miscutils'

commit 524cfa5f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 27 12:21:09 2016 +0200

    Squashed 'packaging/' content from commit d2df30ff

    git-subtree-dir: packaging
    git-subtree-split: d2df30ff

commit b3c0eff4
Merge: 1561873f 524cfa5f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 27 12:21:09 2016 +0200

    Merge commit 'e67e9eea647ec97b2dc3f10d9490d5029d7ef5c2' as 'packaging'

commit 1561873f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 27 12:20:54 2016 +0200

    Remove submodules

commit 6b48aac2
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 6 08:26:29 2016 +0200

    Update miscutils

commit 0fec184f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 6 08:10:08 2016 +0200

    Clean up, add info to DecoupledDataSource

commit 294d20c2
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 5 11:17:25 2016 +0200

    Update miscutils

commit 79d6920e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 5 11:13:27 2016 +0200

    DataWidthConverter: Fix full throughput

    * new full speed test suite failed: output may not block
    * fixed by adding new special case
    * achieves full speed & correctness now

commit df4586fa
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 5 11:12:03 2016 +0200

    DataWidthConverter: Extend tests

    * separated correctness from speed tests for DWC
    * correctness tests with slow queue in between and varying delays
    * full speed suite tests full throughput of data stream (may not block)
    * current implementation fails the latter

commit 65c93606
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 5 08:22:56 2016 +0200

    Update miscutils

commit a621d2be
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 4 20:56:29 2016 +0200

    Bugfix in DataWidthConverter

    * DWC only worked correctly at full speed
    * delays caused lost nibbles, fixed now
    * added secondary test harness to test against a slow receiver

commit 8199d1c0
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 4 07:48:28 2016 +0200

    Reduce default delays for AxiSlaveModel

commit 18cf7be1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 4 07:46:43 2016 +0200

    Adapters: fix address valid logic

    * addresses should only be handshaked when data is actually avaiable /
      needed; previous logic would provide addresses as fast as possible
    * this fixes problems with handshaken addresses at other modules when
      adapter is being reset

commit fde9d942
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Aug 1 08:37:40 2016 +0200

    AxiFifoAdapter: Bugfix AXI interface

    * opposed to FifoAxiAdapter, addresses may only be supplied via the
      interface if data will be read (slave will supply data)
    * this bug led to erroneous read bursts, overflowing the buffer
    * fixed some minor condition issues

commit 1383a12d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Jul 31 09:46:42 2016 +0200

    FifoAxiAdapter: fix transaction logic

    * addressess in transactions should be supplied as fast as possible
    * waiting for the transaction to finish is not necessary and harms
      performance
    * not sure if this implementation is ok; there could be a large gap
      between address handshake and data - if this blocks the slave it
      must be fixed (further tests required)

commit bea25fbf
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Jul 31 09:45:01 2016 +0200

    AxiFifoAdapterSuite: replace asserts with expects

    * asserts cause unit test to fail w/o VCD dump

commit e70fb06c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Jul 31 09:42:41 2016 +0200

    Simplify AxiFifoAdapter

    * replaced tick-tock-buffers with single FIFO
    * burst size now independent of buffer size
    * bursts start immediately when FIFO has space for one burst
    * operation similar to FifoAxiAdapter
    * unit tests work unchanged

commit dbf972b7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 27 10:27:29 2016 +0200

    Implement configurable read and write delays

    * considering the significant delays for real-world rw access
      to memory, AxiSlaveModel should have optional delays to sim
      that behavior
    * extracted config to AxiSlaveModelConfiguration class
    * adapted existing unit test suites
    * bugfix in Axi2AxiSuite: afa now waits for writes to finish

commit c7b36058
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 26 08:15:56 2016 +0200

    AxiFifoAdapter: Improve switching speed

    * condition for switching of FIFOs led to 1-cycle delay
    * now switching when either other FIFO empty, or dequeing
      in progress and exactly one element
    * conditions are the same in both states

commit 7ce43604
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 22 12:19:59 2016 +0200

    Add Tcl scripts for Vivado projects with AXI BFMs

    * two scripts to generate block designs that will use AxiFifoAdapter
      and FifoAxiAdapter with the Cadence AXI BFMs
    * server also as cross-verification of Chisel AXI slave model
    * checks are not automated, results must be verified manually
    * AxiFifoAdapter uses Zynq BFM to preload DDR memory
    * added testbench and memory preload data for AxiFifoAdapter project
    * also added source code of preload file generator

commit 5f640c4e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 22 12:15:41 2016 +0200

    FifoAxiAdapter: rewrite to use ASAP bursts

    * now has single FIFO of configurable size
    * burst size is configurable separately
    * burst is started as soon as burstSize is exceeded in buffer
    * decided against even more aggressive mode of starting immediately,
      since that would likely be detrimental to system performance
    * adapted and verified all unit tests

commit 3447f7f1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jul 21 10:34:13 2016 +0200

    FifoAxiAdapter: Fix WSTRB field

    * WSTRB now correctly adapts to dataWidth (all bytes enabled)

commit 4f3e1b66
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 20 09:46:20 2016 +0200

    Implement full-round trip validating test

    * new test suite: uses both FifoAxiAdapter and AxiFifoAdapter to
      validate a full roundtrip on a AxiSlaveModel
    * most comprehensive test

commit 6d6556b1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 20 09:42:32 2016 +0200

    AxiSlaveModel: Support write bursts

    * also rewrote size-related code: addrWidth and size are now
      optional parameters, but one must be specified (other is calced)
    * fixed some issues with the write address masking (addresses are
      always byte-boundary)
    * modified tests accordingly
    * removed asserts from tests, using proper expect calls instead
      (test now finish with errors, instead of aborting pre-VCD dump)

commit 8e521465
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 20 09:39:40 2016 +0200

    FifoAxiAdapter: Bugfix size parameter

    * did not work correctly for different dataWidths
    * also size parameter in burst address was not set correctly:
      need to specify full-width bursts

commit 6f9d34f8
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 20 09:38:42 2016 +0200

    FifoAxiAdapter: Remove read channel

commit fe9d7b90
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 20 09:34:41 2016 +0200

    AxiFifoAdapter: improve performance

    * now stays in fetch mode and just flips buffers, if current FIFO
      is empty
    * empty checks more aggressive: now checks if FIFO will be empty
      in the next cycle to mask the state transition

commit 97bbef13
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 19 13:50:34 2016 +0200

    Update miscutils, move tests to chisel.axiutils

commit 14b8a115
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 19 11:17:27 2016 +0200

    DecoupledDataSource: unassert valid during reset

    * minor bug: valid would be asserted during reset, fixed

commit 3f3fef24
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 19 11:14:10 2016 +0200

    DataWidthConverter: Fix bugs in implementation

    * previous implementation was not capable of handling a continuous
      stream of data (continuity must be preserved to avoid congestion)
    * new implementation fixes this and several other minor issues
    * better unit test: now using inverted pairs of DWCs
    * makes testing code much simpler and data/waves easier to check
    * added additional tests to specify the required timing behavior
      (i.e., preserving continuous data streams)

commit d2df30ff
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 16 10:22:59 2016 +0200

    Use args to ModuleBuilder to filter builds

    * args can contain names of modules, only those are built
    * names are case-insensitive
    * no args builds all modules
    * added uniqueness check for module names

commit 47415f44
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 16 10:15:17 2016 +0200

    CoreDefinition: another bugfix

commit 723c66e4
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 16 10:01:49 2016 +0200

    Bugfix in new CoreDefinition constructor

commit 67b84bed
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 16 09:58:41 2016 +0200

    Implemented base module builder

    * ModuleBuilder generalizes the building of modules:
      user needs only supply list of CoreDefinitions to build
    * provides main() to run automatically
    * CoreDefinition: additional constructor to automatically
      supply root dir in ip/<name> subdir

commit f0013921
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 16 09:28:47 2016 +0200

    Add signal generator from separate package

    * separate package for SignalGenerator can be removed
    * unit test included

commit 4869b09f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 15 11:33:18 2016 +0200

    Add links to packaging and miscutils submodules

commit 896bddf6
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 15 11:32:15 2016 +0200

    Move everything to package chisel.axiutils

commit a95601dd
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 15 11:21:54 2016 +0200

    Move to package chisel.packaging

commit 5adfb62d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 15 11:19:04 2016 +0200

    Move all to package chisel.miscutils

commit 18a5d95e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jul 14 18:01:59 2016 +0200

    AxiFifoAdapter: bugfix in burst length

commit 74d116c0
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jul 14 17:07:58 2016 +0200

    Add example AxiFifoAdapter IP-XACT core for BFM tests

commit fa52f452
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jul 14 17:06:59 2016 +0200

    AxiSlaveModel: fix off-by-1-bug in burst length

    * AR_LEN can be used directly for countdown var

commit c479cc97
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 13 10:42:22 2016 +0200

    Bugfix: Chisel tests cannot run in parallel

commit 9684a9c2
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 13 10:39:33 2016 +0200

    AxiFifoAdapter: implement AXI mem to FIFO adapter

    * tick-tock buffer approach: one buffer is filled via AXI4 read
      bursts, the other is made available for dequeuing
    * can provide continuous data at full speed, given that the bursts
      finish fast enough
    * also added some unit tests for fixed blocks of memory
    * missing: support for wrap-around (currently via reset)

commit 90c05e9b
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 13 10:38:45 2016 +0200

    AxiSlaveModel: Support for read bursts

commit e6c0e03b
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 12 10:03:55 2016 +0200

    Fix bug of failing tests when running 'sbt test'

    * caused by parallel execution of suites (apparently Chisel does
      not like that)
    * fixed by deactivating parallel and forked executions

commit 28b71a00
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 12 10:03:25 2016 +0200

    Move individual test outputs to own subdir

    * each suite now has a subdir
    * each test has subdir within suite dir

commit 6fc06386
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Jul 11 19:46:28 2016 +0200

    DataWidthConverter: support upsizing

    * upsizing mode (inWidth < outWidth) implemented
    * added unit test support for upsizing

commit fae43067
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Jul 11 09:44:18 2016 +0200

    Implement DataWidthConverter and unit tests

    * basic Decoupled-based data width converter
    * currently only downsizing implemented with endianess selector
    * works, but performance is lackluster yet
    * unit tests cover several interesting combinations in both endianesses

commit 26f72705
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Jul 10 14:45:40 2016 +0200

    AxiSlaveModel: implement mem size parameter

    * memory size can now be controlled independently from addrWidth
      to allow large address spaces

commit 4443aa0c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Jul 10 09:51:58 2016 +0200

    First draft of FifoAxiAdapter

    * adapter to write data from Decoupled-Fifo as AXI4 master
    * base address supplied as input
    * all widths configurable
    * FifoAxiAdapterTest1 uses DecoupledDataSource to test with
      constant data set
    * can also be used to verify against AXI BFMs

commit 4a10a2e7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 9 09:22:45 2016 +0200

    Add CoreDefinition scala class

    * Scala model for core definitions
    * support for reading and writing Json format

commit 5a1f9945
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 8 15:33:36 2016 +0200

    DecoupledDataSource module

    * testing utility: provides fixed data via Decoupled
    * configurable with/without wrap-around
    * unit tests

commit c58f5a12
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 1 07:00:52 2016 +0200

    Bugfix

commit 90e7cca7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 1 06:38:27 2016 +0200

    Initial version of packaging script

    * based on Python, Vivado IP Integrator
    * produces component.xml with correct reset polarity

17f0d672

03 Apr, 2018 1 commit
- Use global lib dir directly under top-level · 0615ad96
  Jens Korinth authored Apr 03, 2018
```
* libplatform and libtapasco can be built in the same location now
```
  0615ad96
15 Nov, 2017 1 commit
- Extend .gitignore to generated scripts in bin/ · c14f5e70
  Jens Korinth authored Nov 15, 2017
  
  c14f5e70
14 Jul, 2017 1 commit

Squashed commit of the following: · a831b501

Jens Korinth authored Jul 14, 2017

commit c824a896
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 14 19:55:44 2017 +0200

    Update examples

    * added project to contain all subprojects
    * updated all examples to latest version and cleaned dirs
    * all examples are building again, not sure if they work

commit 4e2f91de
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 14 18:35:23 2017 +0200

    Update README.md

    * need to rewrite the GETTINGSTARTED documents, removed them for now
    * also deleted 'release.sh' leftover

commit e51b951c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 14 18:20:02 2017 +0200

    Bump version to 2017.1

commit 111d1485
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 14 18:19:47 2017 +0200

    Fix bug in usage output

commit 7d96d783
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 14 18:04:28 2017 +0200

    Closes #112 - itapasco does not start

commit 2237d2c0
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 14 17:55:19 2017 +0200

    Reset to normal logging

commit 44a6271c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 14 17:51:51 2017 +0200

    Fix most whitespace errors

commit 1914aec8
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 14 17:40:36 2017 +0200

    Fix broken main man page and update

    * man tapasco page is broken, was too optimistic that man would be able
      to parse the ASCII format directly (works on Darwin)
    * replaced hard-coded strings with mini-markup language
    * Formatters can produce any kind of representation
    * same code is used to produce CLI output and man pages
    * will simplify the updates in the future

commit 3959bfb3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 14 10:44:49 2017 +0200

    Closes #111 - Add CLI log tracking switch

    * new switch is -v/--verbose with optional MODE as quoted string

commit ab773490
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jul 13 17:52:48 2017 +0200

    Squashed commit of the following:

    commit e1683d56027c71d4fbf2ba2543a528da1b44285d
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Thu Jul 13 17:36:59 2017 +0200

        Replace old Feature implementation

        * old implementation was "fat", i.e., each Feature had to have its own
          class on the Scala side of things
        * knowledge about validity is on Tcl side; led to double effort to check
          for invalid values, which went out-of-sync
        * removed fat layer, replaced by thin, generic implementation:
          Features have a name and a map of properties, mapping strings to
          strings; all properties are passed exactly as-is to Tcl
        * special case: added "Enabled" -> "true" in all cases, reasoning: if
          somebody goes to all the trouble of defining a Feature, it should
          usually be enabled
        * can be overridden explicitly (for whatever reason)

    commit b559df40a0ad697e4d1b60f8c4ee927cae44c4ec
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Thu Jul 13 16:45:15 2017 +0200

        Fix bug in path parser, fix test cases

    commit 0ee9f090705d1ffd4b36d5c26b9a1978c57fab6a
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Thu Jul 13 15:58:54 2017 +0200

        Fix bug in HLS gens

        * 'all' must be used _instead_ of kernel list, not within

    commit 7b67ee180af8f53276b58c9697b8f798469b2afc
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Thu Jul 13 15:51:39 2017 +0200

        Update usage info and man pages

        * man page is generated by Usage; not as nicely formatted, but readable
        * simplifies maintenance by keeping information in one place only

    commit 7cffc777da2db55f74e23eb1546f597a881de9df
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Thu Jul 13 12:11:50 2017 +0200

        Implement missing --logFile option

        * added to property checks as well

    commit bfa6d8fc173c4edd58c78c12f749ebfc2947ee4e
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Thu Jul 13 12:01:08 2017 +0200

        Increase the number of worker threads to 500

    commit 884d3f5ffd5d3fd0890f07650cabc4a482ad4f1b
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Thu Jul 13 11:59:30 2017 +0200

        Improve error messages from parser

        * mostly fine-tuning to make sure the lastParser value gives the user
          the right idea about the mistake
        * see also the script parserTest.sh in Seafile/TAPASCO to generate a lot
          of error messages automatically

    commit 28215f874dab107810344584b98267809eb4dc4d
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Wed Jul 12 19:27:53 2017 +0200

        Dump example jobs, if none are specified

        * Configuration dumping should automatically use JobExamples to generate
          a list with on instance of each job
        * useful for users to get a starting point for their configs
        * updated README.md accordingly

    commit 72969fcbcb6ff5583c368969fa6d59cc5d290756
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Wed Jul 12 19:22:01 2017 +0200

        Finish work on new parser and property tests

        * all parsers implemented, spec'ed and debugged
        * wrote a lot of property tests, caught some bugs I'd never have found
          otherwise, very nice
        * changed a few bits and pieces, need to rewrite man and usage

    commit 786596a793a8d0510465438e77a5067f5d1bd67b
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Tue Jul 11 18:49:36 2017 +0200

        Bugfix exceptions in MemInfo when /proc/meminfo is unavailable

        * not portable, sometimes /proc/meminfo may not exist (e.g., Darwin)
        * will warn once, then deactivate all resource checks on mem

    commit e029dc27619de33477e3a3c156a91e18bb1f7eb7
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Tue Jul 11 18:49:08 2017 +0200

        Bugfix for setup.sh on Darwin

    commit b53bbbc225eaf0b1c31bac2e20299e07b9e00fcf
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Tue Jul 11 18:47:42 2017 +0200

        Continue work on new parser

        * split classes into more sub objects
        * each subobject needs its own test suite with at least one test for
          each parser defined therein
        * got better with scalacheck, tests are stronger

    commit 6b3b2504d31e1f673f4336901bec18203e3f2b3d
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Sun Jul 9 18:34:01 2017 +0200

        Added unit tests and cleaned up a little

    commit 8b12879df3ed59803a66ee7a97d006bb20982056
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Sun Jul 9 18:33:00 2017 +0200

        Add missing --parallel in man page

    commit 10d8b3a02bb8b02fc4ac287aa9e6fa6d4dece51e
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Sat Jul 8 23:34:22 2017 +0200

        Implement new parser with better error handling

        * error messages of the current command line argument parsrer are
          abysmal, extremely confusing to users
        * since scala parser combinators do not feature cuts, it is very
          difficult to provide better error messages
        * started re-implementation of parser using 'fastparse'
        * works extremely well so far

commit d47c6666
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jul 12 19:40:12 2017 +0200

    Closes #110 - Implement support for PEs with .xci IPs

commit a90dcd37
Merge: b0724575 1221cbdc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jul 12 17:35:47 2017 +0000

    Merge branch 'BlueDMAPerformanceCounters' into '2017.1'

    Adds performance counters to BlueDMA

    See merge request !6

commit b0724575
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jul 12 18:00:40 2017 +0200

    Closes #99 - Allow selective Core building in itapasco

    * as requested, HLS runs will only be initiated for Platforms and
      Architectures selected in the corresponding tabs

commit 1221cbdc
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Mon Jul 10 18:47:34 2017 +0200

    Adds ID signals back in to avoid Vivado errors

commit 2dd2b14f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon Jul 10 17:09:37 2017 +0200

    Add trace output of Vivado and Vivado HLS

    * external Vivado/Vivado HLS processes only log to files
    * for debugging it would be helpful to have the stdout and stderr of the
      processes log directly in the console
    * added ProcessLogger for the outputs; trace level, should only be
      activated selectively

commit e495ff21
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Fri Jul 7 16:34:03 2017 +0200

    Adds performance counters to BlueDMA

        - Closes #89
        - Adopts DebugScreen accordingly
        - Implements all registers requested in #89 expect for
          * Host read delay
          * FPGA read delay

commit 9b59398d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 7 15:40:06 2017 +0200

    Fix bug in VC709 driver reloading

commit ed7906b9
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 7 15:27:14 2017 +0200

    Fix typo in bit_reload.sh

commit b8a2c3c2
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 7 15:26:01 2017 +0200

    Bugfix address map in VC709

commit d6d9b5f3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 7 15:19:13 2017 +0200

    Add missing constraints file for MSI-X controller

commit fd1b8d2f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 7 14:21:48 2017 +0200

    Bugfix path name for compositions with Cache

commit 278fae90
Merge: 5029ff2f 0608e988
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jul 7 12:15:46 2017 +0000

    Merge branch 'BlueIPUpdates' into '2017.1'

    Update BlueDMA and MSIxIntrCtrl to the newest versions

    See merge request !5

commit 0608e988
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Fri Jul 7 10:40:10 2017 +0200

    Adds newest BlueDMA version

        - PCIE Burst Length 64
        - FPGA Burst Length 256
        - Alignment 32 Bytes
        - Fixes SUPPORTS_NARROW_BURST parameters
        - Adds NUM_READ_OUTSTANDING and NUM_WRITE_OUTSTANDING to help
        interconnects decide on the DMA features

commit 2785e65e
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Fri Jul 7 10:38:07 2017 +0200

    Eases timing in the wait for completion path

commit 5029ff2f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jul 6 18:18:30 2017 +0200

    Remove resource check for memory

    * memory usage estimates are based on numbers reported by the
      Lichtenberg cluster, but are too conservative for normal users
    * removed check for memory entirely

commit ed0497b2
Merge: c54b8cf7 4cd951cb
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jul 6 16:13:17 2017 +0000

    Merge branch 'assembly' into '2017.1'

    Adds 'sbt assembly' as necessary step to exeute tapasco.

    See merge request !4

commit c54b8cf7
Merge: 0c436917 9922406b
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jul 6 16:12:35 2017 +0000

    Merge branch 'ngc_evaluation' into '2017.1'

    Allow evaluation of kernels using primitives provides as .ngc-files;

    See merge request !3

commit 0c436917
Merge: a543f07d bfcfeb64
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jul 6 15:56:51 2017 +0000

    Merge branch 'ATSBackports' into '2017.1'

    Ports changes of the ATS Branch of TPC to Tapasco

    See merge request !1

commit 4cd951cb
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 16:58:10 2017 +0200

    Adds 'sbt assembly' as necessary step.

commit bfcfeb64
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 16:50:50 2017 +0200

    Removes last remnant of the past

commit 9922406b
Author: Lukas Sommer <sommer@esa.tu-darmstadt.de>
Date:   Thu Jul 6 16:45:00 2017 +0200

    Allow evaluation of kernels using primitives provides as .ngc-files;

commit 12b1048b
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jul 6 14:20:07 2017 +0000

    Update setup.sh

commit 658d5eb6
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 14:18:50 2017 +0200

    Simplifies timing for BlueDMA

commit 125f4b44
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 14:17:57 2017 +0200

    Fixes interrupt false_path

commit 37de28fa
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 11:50:04 2017 +0200

    Adds ZSH to dir-free setup.sh

commit 71b50778
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 11:28:50 2017 +0200

    Fixes addressing of the interrupt handler

commit 32bde4df
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 11:21:08 2017 +0200

    Fixes memcheck example

commit a6a8b210
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 11:18:24 2017 +0200

    Adds stable MSIXIntrCtrl

commit 63d53405
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 11:17:09 2017 +0200

    Adds stable BlueDMA

commit c6c0046d
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 11:09:18 2017 +0200

    Adds tie-offs to unused interrupts

commit 3d1045af
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 11:05:28 2017 +0200

    Fixes error handling in fflink driver

commit a76bff21
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Jul 6 11:03:25 2017 +0200

    Backports driver improvements

commit a543f07d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 29 17:00:20 2017 +0200

    Add more log output for plugins

    * more detailed logs for each event, easier for debugging
    * also provides a rough idea of current progress during bughunt

commit 7fdc699d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 29 16:57:23 2017 +0200

    Bugfix Zynq address map generation

    * another bug appeared, fixed
    * cleaned code, added more verbose output to log

commit d6adc315
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 29 13:14:30 2017 +0200

    Bugfix for newer Vivado versions in Zynq platform

    * address map code did not work correctly, fixed

commit 3c810860
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 29 13:12:12 2017 +0200

    Bugfix: Remove netlist replacement for cores

    * netlist-only IP cores lead to problems with the clock constraints
      regarding the bus interfaces: Vivado could no longer infer the clock
      for each AXI interface automatically, leading to broken cores
    * removed netlist creation; deactivation of OOC builds in 2016.4+ fixes
      the core problem of synthesizing the same core dozens of times

commit 99e50066
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 29 13:00:29 2017 +0200

    Add flatten option to unzip

    * ZipUtils now has flatten option for unzip (set by default)
    * if not set, will recreate directory structure in target dir

commit edf10ce3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 29 12:56:37 2017 +0200

    Improve timing closure

    * evaluation was too pessimistic for many cores, leading to designs
      significantly slower than possible
    * fixed by using more aggressive synthesis options
    * more aggressive pnr options had no measurable effect on WNS
    * using new options in both evaluation and compose

commit 41a66104
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 9 16:41:45 2017 +0200

    Closes #91 - Alternatives are not built prior to DSE

    * alternatives are now checked and built, in case the alternatives
      dimension is activated in DSE

commit dd2daa49
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 9 16:12:25 2017 +0200

    axi4mm patch: use one master per refarg

commit bc9d2096
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 9 16:01:00 2017 +0200

    Deactivate debug logging

commit ed3c435f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 9 15:57:43 2017 +0200

    Add IP for BlueDMA

commit 55e97aec
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 9 15:57:03 2017 +0200

    Stop cleaning after erroneous runs

commit 7e36ed16
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 9 15:47:37 2017 +0200

    Update MSI-X interrupt controller

commit 6474f392
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 9 15:43:11 2017 +0200

    Bugfix bash detection

commit 7b094701
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 9 14:26:18 2017 +0200

    Bugfix in tapasco-build-libs (missing LKM)

commit 877e715c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 9 13:28:35 2017 +0200

    Bugfix in output file name of tapasco_benchmark

commit 3190c491
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 8 10:26:36 2017 +0200

    Add ATS/PRI controller in address map on Zynq

commit 78dc930d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 8 10:13:47 2017 +0200

    tapasco-benchmark: Update JobThroughput

    * reduced required instances to one
    * minimal number of threads tested is now twice the number of physical
      processors (accounts for hyper-threading)

commit fad012d4
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Wed Jun 7 10:26:08 2017 +0200

    Closes #90 - Implement INTC-less MSI-X architecture

    * removed all interrupt controllers for VC709
    * replaced by 132 MSI-X interrupts (128 PE, 4 other)
    * replaced driver code

commit f31e734b
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jun 7 09:23:58 2017 +0200

    Increase memory requirements for ComposeTask

commit 7e0a9532
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jun 7 09:22:00 2017 +0200

    Bugfix in Import, fixed wrong names of zips

commit fead6df4
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jun 7 09:21:15 2017 +0200

    SLURM: add comment to jobs containing the composition

commit cd1ac9ed
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jun 7 09:18:27 2017 +0200

    SLURM: retry failed enqueues

    * slurm executables are highly unreliable, both sbatch and squeue often
      fail with socket errors and similar
    * need a retry mechanism for sbatch, too
    * will retry a number of times now, with 10secs in between, before failing

commit 755114a3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jun 7 09:16:11 2017 +0200

    Only write bitstream in case of timing closure

commit 41e5c933
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jun 6 14:21:01 2017 +0200

    Clean compositions on success by default

commit a7e51d68
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jun 6 14:15:28 2017 +0200

    Do not change into TAPASCO_HOME to run

    * since we are by now using the jar to execute, there is no more need to
      change the current directory in the tapasco/itapasco scripts

commit 15b9811a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jun 6 14:12:27 2017 +0200

    Produce pre-synthesized netlists in EvaluateIP

    * synthesis can be accelerated by dumping an EDIF netlist during IP
      evaluation and only using the netlist in the IP-XACT core
    * no need to re-synthesize IP, especially useful in case of many
      instances
    * replaced old links to original zip files by new zip that contains only
      the component.xml and the netlist

commit 325315a8
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jun 6 13:55:21 2017 +0200

    Activate synth retiming, deactivate OOC by default

    * retiming is not activated by default, but helps with timing closure
    * OOC is the new default for all IP cores in the top-level; since we are
      only running a single time we cannot benefit from the feature

commit f5a1123a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jun 6 13:52:05 2017 +0200

    Bugfix ResourceMonitor canStart with SLURM

    * SLURM should ignore resource constraints
    * tasks now start correctly in SLURM mode

commit 22cbefbd
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jun 6 13:51:45 2017 +0200

    Implement zip creation method in utils

commit 14c8db46
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jun 6 13:51:14 2017 +0200

    Fix whitespace

commit fb0730d9
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jun 6 13:48:46 2017 +0200

    Implement global 'maxThreads' parameter

    * better control to restrict parallelism (~ memory consumption)
    * global parameter --maxThreads [NUM] controls general.maxThreads in Vivado
    * applies to both synthesis and implementation
    * removed superfluous implicit in Composer

commit a8f64503
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jun 6 13:42:49 2017 +0200

    Bugfix clean() in VivadoComposer

    * stopped working due to rename of Vivado project

commit d2f237c5
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jun 6 13:37:59 2017 +0200

    Allow sourcing of setup.sh from other directories

    * only works for Bash shell; warning for others

commit c0611535
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Sun Jun 4 09:15:31 2017 +0200

    Change default for mem frequency to design frequency

commit 67e822c6
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Sun Jun 4 09:10:41 2017 +0200

    Implement --parallel switch

    * Jobs are executed sequentially by default, but there are cases in
      which it is useful to execute them in parallel instead (especially in
      combination with SLURM)
    * implemented global --parallel switch to activate this mode
    * added to all representations (parser, Json, prettyPrint)

commit 25ef5cf5
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 2 18:48:31 2017 +0200

    Correct memory resource requirements for PyNQ/ZedBoard

    * just had a number of runs killed, because their memory usage exceeded
      8 GiB (Xilinx claims 6 GiB, but apparently for PnR only)
    * moved to generous 10 GiB

commit 962b0dd7
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 2 18:47:28 2017 +0200

    Closes #92 - Do not run HLS in DSE for existing cores

    * fixed; existence of cores is now checked as in Compose

commit 96dc8327
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 2 10:22:32 2017 +0200

    Update rot13 kernel

commit b89ccf99
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 2 10:21:37 2017 +0200

    Cleanup kernels: remove unused/broken code

commit e8e1b0e9
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 2 09:33:17 2017 +0200

    Improve MSI-X interrupt controller for many channels (JAH)

commit 063c48e6
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 2 09:32:05 2017 +0200

    Remove BAR offset for BlueDMA

commit 49396f7d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 2 09:31:18 2017 +0200

    Fix bugs in VC709 plugins (arg passing)

commit d0aabfa4
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 2 09:30:25 2017 +0200

    Fix bugs in ZC706 plugins (arg passing)

commit 0763e216
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 2 09:29:26 2017 +0200

    Pin heartbeat and init of OLED ctrl to LEDs (zedboard)

commit 12683104
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 2 09:28:24 2017 +0200

    Add missing plugin events in master template

commit 6b037ef5
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jun 2 09:28:01 2017 +0200

    Fix bug in VLNVs for Vivado 2016.2

commit f4678826
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 1 17:35:24 2017 +0200

    Closes #82 - VC709: MSI-X controller

    * MSI-X controller by jah with 8 channels replaces MSIs
    * works on newer Linux kernels

commit 615f6dd2
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 1 16:59:21 2017 +0200

    Backport bugfixes and improvements from ATS branch

    * backport improved vc709.tcl
    * support for MSI-X interrupts
    * support for BlueDMA replacement for dual_dma
    * Platform API: raw read/writes
    * setup.sh automatically builds .jar
    * Compose: dumps Configuration in output directory
    * Compose: adds activated Features to last dir level
    * new Feature ATS+PRI w/Tcl support
    * new Feature BlueDMA w/Tcl support
    * some bugfixes regarding Features

commit 8a5068c7
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 1 13:13:23 2017 +0200

    Backport new VC709 driver to Tapasco

commit 4f9d515b
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 1 10:54:30 2017 +0200

    Fix VC709 Platform

    * fixed bug in bit_reload.sh
    * fixed compile bug in newer kernel versions
    * IRQs do not work! need to port MSI-X controller

commit 66e29471
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 1 10:53:13 2017 +0200

    Update .gitignore

commit 29b5c977
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 1 10:52:47 2017 +0200

    Forgot to checkin new Status core

commit 1d9ddfb8
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 1 10:49:49 2017 +0200

    Zynq: Use new default clocks to generate subsystem

    * create_subsystem_clocks_and_resets automatically gets freqs
    * using now in Zynq, removed manual mem freq computation
    * fixed bug in default argument

commit 9d883d00
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jun 1 10:39:04 2017 +0200

    tapasco-debug: Add status core infos to bottom line

    * added information to kernel map screen
    * now showing: #intcs, vivado version, tapasco version, timestamp
    * also showing: host, mem and design clocks, caps bitfield
    * changed layout a little bit, fixed width of 80 chars

commit 74d948f8
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed May 31 15:45:41 2017 +0200

    Closes #53, #68, #80 - Capabilities and Status Core

    * backported device capability interface
    * extended status core with new registers:
      + Vivado version
      + Tapasco version
      + Timestamp (UNIX)
      + Clocks (host, mem, design)
    * added new common methods to query the frequencies and globals to set
    * used as default by create_subsystem_clocks_and_resets
    * extended Platform to contain optional frequencies
    * implemented unit tests for each new property
    * if set, they are written to Tcl in VivadoComposer

commit d9ea378f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed May 31 14:29:38 2017 +0200

    Fix bug concerning illegal name of thread pool

    * 'Architecture' is illegal, renamed to 'uArch'
    * fixed in Platforms

commit 7fdee069
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed May 31 09:35:41 2017 +0200

    Update benchmark data for Zynq platforms

commit 1bdde6b2
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 18:07:07 2017 +0200

    tapasco-build-libs: Fix bug when LINUX_HOME is not set

    * also increased "cleanliness" in clean by removing lib dirs

commit a74c7bb7
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 17:18:25 2017 +0200

    Fix Platform API header bug in tapasco-benchmark

commit b7e974f7
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 17:17:46 2017 +0200

    Fix header bug in tapasco-benchmark

commit a300ef27
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 17:16:19 2017 +0200

    Add option switch for measurements in tapasco_benchmark

    * options are: a(ll), m(emory transfers), i(nterrupts), j(obs)
    * default is all

commit 77c28d57
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 17:14:26 2017 +0200

    Fix output bug in tapasco-benchmark

    * forgot to output final values, resulting in erroneous readouts
    * switched back to high_resolution_clock, since wrong values were
      unrelated to the steadiness of the clock

commit 53d35035
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 16:16:22 2017 +0200

    Benchmarks: Add new job throughput measure

    * added Json serdes
    * fixed unit test cases

commit 9ff38dee
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 15:31:01 2017 +0200

    Closes #75 - Rename or remove [tapasco::get_generate_mode]

    * removed; not required anymore
    * standard name for Vivado project is now microarch

commit 03d74ebf
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 15:21:00 2017 +0200

    Closes #71 - Rename baseline to axi4mm

    * baseline sounds suboptimal and does not give any idea towards the kind
      of Architecture
    * since it is based on AXI4 memory mapped interfaces it is renamed to
      axi4mm
    * fixed all occurrences of baseline

commit 766370fb
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 14:58:14 2017 +0200

    Closes #78 - Rename tapasco_api.h/hpp to tapasco.h/hpp

    * suffix `_api` is unusual, removed
    * fixed all include occurrences

commit 4087088e
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 14:30:54 2017 +0200

    Closes #79 - Rename platform_api.h to platform.h

    * suffix `_api` is unusual, removed
    * fixed all includes

commit 2a8a3af7
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 13:38:03 2017 +0200

    benchmark: remove throws in TransferSpeed

commit 6446089f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 11:40:10 2017 +0200

    benchmark: Remove legacy output

commit 7a751bf9
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 11:06:55 2017 +0200

    Fix ctrl+c handling in tapasco_benchmark

    * unfortunately, ncurses needs to trap signals, so the last version did
      not work correctly
    * now using raw mode to check for ctrl+c directly
    * also moved ncurses initialization into main, instead of the
      measurement classes

commit 562a94ca
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 10:16:08 2017 +0200

    benchmark: reduce InterruptLatency load

commit e2bced6b
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 10:13:20 2017 +0200

    benchmark: Trap SIGINT and exit cleanly in case of exceptions

commit f274fe25
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 30 10:12:48 2017 +0200

    Improve TransferSpeed loop, reduce load

commit 8d6d9989
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 29 14:52:09 2017 +0200

    Improve convergence speed of CumulativeAverage

    * tiny bug: initial value was considered a valid measurement
    * led to slow convergence, if actual measurements are large
    * also fixed a bug concerning the minimal/maximal elements

commit bc797e4f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 29 14:50:16 2017 +0200

    Implement job throughput measurement in benchmark

    * measures how many jobs with minimal runtime (1cc) can be scheduled per
      second, using a fixed number of threads
    * benchmark will record at least 1-8 threads, more while performance
      increases
    * also improved convergence and reduced update speed for the other
      measurements

commit 55ad20bf
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 26 18:57:02 2017 +0200

    Fix examples to work with current APIs

    * done: arrayinit, arraysum, basic_test, warraw
    * others still missing
    * need to unify the tests, basic_test is a good start
    * should rename warraw to arrayupdate and remove warraw refs

commit 2ee7b740
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 26 18:55:43 2017 +0200

    generate_boot_image: Fix pynq devicetree

commit 20e33f67
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 26 16:52:29 2017 +0200

    Zynq: clean bit_reload.sh output

commit 939702ba
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 26 16:50:19 2017 +0200

    tapasco-build-libs: clean arch/tests

commit fcd5e3a6
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 26 16:43:37 2017 +0200

    tapasco-build-libs: build tapasco-debug and tapasco-benchmark

commit 13748a1a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 26 16:42:52 2017 +0200

    Improve readability of Platform description table

commit ba7f1b4a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 26 16:41:55 2017 +0200

    Bugfix Benchmark: Cycle counts and chunk size must be Long

commit f3f4df2a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 26 16:39:10 2017 +0200

    tapasco_benchmark: Fix bug in Platform guess

    * now using host name as platform, if unknown

commit 63d0282e
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 26 16:35:30 2017 +0200

    Require sudo password only once at start

    * generate_boot_image.sh requires root rights at many different points
    * in it possible that the sudo timeout hits in between, leading to
      aborted execution if the user fails to re-enter the password
    * fixed that, asking once, re-using the password
    * also fixed and improved several other things:
    * fixed zedboard and zc706 devicetrees (needed patching to activate IRQs)
    * same with PyNQ, but different approach: have fixed devicetree in pynq
    * fixed U-Boot output log redirection

commit d28e1a32
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 26 14:22:24 2017 +0200

    Bugfix in basic scripts for PyNQ

commit ea050b7d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed May 24 19:04:18 2017 +0200

    Include linux-xlnx in SD card images

    * additional size parameter allows to control size of output image
    * if size is larger than 4GiB, the full linux-xlnx build tree will be
      added to the rootfs at /linux-xlnx (1.1GiB)
    * modified rc.local script changes owner recursively to 'xilinx'
    * fixed some more bugs

commit 69f18a39
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed May 24 15:09:10 2017 +0200

    Prepare disk image in generate_boot_image.sh

    * instead of directly formatting and partitioning an SDcard,
      generate_boot_image now prepares a disk image file
    * setup via losetup, formatted and mounted via kpartx
    * much faster than previous method, including faster writing to SD
    * major stylistic improvements, clearer style
    * fixed bug in parallel executions

commit 0dbcdbbb
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 23 19:29:56 2017 +0200

    Update README.md in boot

commit 1871ad51
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 23 19:22:38 2017 +0200

    Implement SD card generator for PyNQ, ZC706

    * extended the zedboard version
    * fixed devicetrees, now working out-of-the-box
    * automated extraction of root FS
    * patching root FS for network stuff, removing Jupyter, but keeping the
      autoresizing, which is pretty neat
    * PyNQ is non-trivial to rebuild; decided to extract directly from the
      image
    * PyNQ image is downloaded from public URL at Digilent (minimal
      footprint in git)
    * not enough space to put linux-xlnx on board; maybe increase image
      size? or provide script to automate the process

commit 3053b5f9
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 19 19:01:49 2017 +0200

    Implement basic script to produce boot images

    * it is an incredibly annoying process I'd really like to automate
    * first draft seems to work ok, but there is a problem with the devicetrees
    * need to continue work next week

commit d764cc24
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 19 18:42:03 2017 +0200

    Compose: Rebuild only missing kernels

    * Compose started an HLS task for every PE in a Composition
    * problem, if Core does not have a Kernel (imported IP-XACT)
    * wanted to fix that in any case, but until now it was just a
      convenience/efficiency thing, now it was a bug

commit 3773b845
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 19 18:41:00 2017 +0200

    Zynq: new IRQ offset is 61 - 16 = 45

    * apparently the interrupt is now shared (SPI) in recent kernels

commit 8400a7d9
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 19 18:40:21 2017 +0200

    tapasco-debug: leave ncurses before exiting

commit 0dff8108
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 19 18:38:44 2017 +0200

    tapasco_benchmark: Extend latency data

    * latency data now contains min, max and average
    * new Json format implemented in scala
    * fixed several minor issues in case of errors

commit 35f0b38e
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 19 18:34:24 2017 +0200

    Fix function reservation bug in libtapasco

commit 55c48b53
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 19 18:33:35 2017 +0200

    Fix initialization bug in libtapasco

commit c0dca204
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed May 17 21:42:44 2017 +0200

    Zynq: Fix relative path problem in load bitstream

commit 74fee3f4
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed May 17 21:41:03 2017 +0200

    Closes #73 - PyNQ: Fix base clock

    * added type clk to the bd pin and a frequency of 125 MHz
    * added some debug output
    * fixed PS parameters (from PyNQ example design)

commit d32c94ff
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed May 17 16:12:08 2017 +0200

    Closes #72 - Rename .bit file

    * changed to better name reflecting composition, target and freq

commit f149a3d0
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 16 17:26:55 2017 +0200

    Improve arch documentation

    * updated Doxygen configs
    * added two READMEs for the test builds

commit 39e4890d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 16 17:26:03 2017 +0200

    Add object files and DSE results to .gitignore

commit 5c494830
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 16 17:25:10 2017 +0200

    Closes #69 - Composer.Result should contain UtilizationReport

    * fixed occurrences, renamed the member

commit a87b16be
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 16 17:21:33 2017 +0200

    Closes #6

    * fixes support for 2016.4 and 2017.1
    * improved modularity by implementing shared platform::generate
    * checking results of runs in Vivado, adding list of logs to check in
      case of error
    * cleanup

commit ee529830
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 16 09:37:28 2017 +0200

    Bugfix broken Run.compare

commit 0260f867
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 17:58:20 2017 +0200

    Closes #61 - DSE: False positives for double enqueues of ConcreteRuns

    * compare support was completely broken, a wonder that the code ever
      seemed to work at all
    * comparison of the actual Composition was missing; comparing
      Compositions is a bit tricky due to many isomorphisms in the
      definition
    * opted to compare area utilization instead: Unlikely that two different
      compositions in the same DSE run will ever have _exactly_ the same
      number of LUTs, FFS, etc.
    * should work now, comparison order: area, h-value, frequency

commit 7ab0344b
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 17:47:40 2017 +0200

    Implement re-usable job examples to generate Json

commit 9e99bc51
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 17:46:07 2017 +0200

    Closes #10 - Examples for Json syntax of Jobs

    * new object JobExamples contains examples and dump code
    * can be used to re-generate directly from the defs
    * also added a README.md to mark optional/mandatory params

commit c1de1ee9
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 16:53:38 2017 +0200

    Bugfix RE for synth logs

    * previous RE did include many other runme.logs, fixed

commit 94383778
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 16:40:03 2017 +0200

    Closes #60 - iTaPaSCo: Add log chasing patterns for Vivado

    * added only synth_1/runme.log, impl_1/runme.log
    * tracking all runme.logs just scrambled the output and generated a lot
      of CPU load
    * need better way to distinguish the sources; colors?

commit c8a58f11
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 15:46:05 2017 +0200

    Closes #12 - Rename Descriptions to extension ".json"

commit 328f9c33
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 15:22:02 2017 +0200

    Remove outdated documentation in doc subdir

commit d0169b2d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 15:06:17 2017 +0200

    Closes #52 - Import: Check re-run condition for task

    * missing report now correctly triggers re-evaluation of the core
    * moved core.description file into 'ipcore' subdirectory
    * fixed problem with relative paths for import file

commit ddd478c7
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 13:57:26 2017 +0200

    Closes #62 - DSE: Synthesis report is empty, but utilization.txt exists

    * was in fact not implemented; fixed

commit 0bd0702f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 13:44:22 2017 +0200

    Closes #63 - ComposerLog: PlacerError not recognized

    * added new message to regex
    * will subsume all placer errors of the form 'ERROR: [Place...'

commit 638b8f6c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 13:32:13 2017 +0200

    Closes #65 - Composition directory structure: Target first?

    * changed order to: Arch/Platform/Kernels/Counts/Freq
    * makes a lot of sense, easier to find bitstreams for a given target

commit 1a762feb
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 13:18:43 2017 +0200

    Add additional hierarchy levels in composition dir

    * new pattern example: `counter__arrayinit/012_042/090.0/baseline/pynq`
    * adds useful groupings: compositions with the same kernels, same
      instance counts, same frequencies
    * nesting is extremely deep, but still worked in test

commit 64d9aa89
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon May 15 12:33:54 2017 +0200

    Closes #16 - Rename Composition Directories

    * changed dir pattern, example: arraysum__12___counter__1--90.0
    * much better readability, also works for names ending in a number
    * may be too long; but tests were so far successful

commit 40ec9b94
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Sun May 14 15:37:08 2017 +0200

    Closes #57 - Slurm DSE: squeue causes RuntimeException

    * isRunning is now returning true instead of false on error
    * fixed the problem, may incur up to 15secs of additional wait time

commit 080ffa67
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Sun May 14 10:24:02 2017 +0200

    Closes #58 - Platform: Remove slotCount

    * not removed, but made optional w/default 128
    * may be yet useful in certain cases

commit 94e60bf1
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Sun May 14 09:21:23 2017 +0200

    Ignore json11 files for tapasco_benchmark

commit eed6d5f6
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Sun May 14 09:20:45 2017 +0200

    Upgrade to latest version of scalatest, scalacheck

commit 1ce272eb
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Sun May 14 09:18:49 2017 +0200

    PyNQ: Fix DDR parameters, PS parameters

    * since PyNQ does not have a board definition file, DDR and general PS
      parameters (e.g., APU freq) have to be set manually
    * overridden createZynqPS in pynq.tcl takes care of that and also
      replaces the missing board automation for DDR, FIXED_IO

commit 5bfe0e82
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Sat May 13 23:55:41 2017 +0200

    Closes #55 - Platform: Make board part optional

    * making it optional was trivial, but support in PyNQ was not
    * noticed that the board part of the ZedBoard and the support files for
    the ZedBoard were used, this does not work (completely different board)
    * had to pull the master XDC to find the clock pin and fix that
    * Platforms can implement platform::create_clock_port to generate their
    own clock ports
    * plugin is used to generated the constraints "post-synth"
    * Zedboard and PyNQ bitstreams build, but cannot be tested

commit e38d3aef
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Sat May 13 15:27:18 2017 +0200

    Implement ScalaCheck properties for Benchmark interpolators

    * testing correct behavior of interpolators for simple cases (2/3
      value interpolation)
    * added some inline doc for Benchmark

commit 40e9463a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 12 19:08:14 2017 +0200

    Platform: Add latency function

    * extended tapasco_benchmark to record latencies for runtimes between
      2^0 and 2^31 clock cycles
    * extended benchmark Json to record new data
    * wrote linear interpolation base class to interpolate between
      measurements for both transfer speed and latencies
    * fixed unit test, supplied Arbitrary for the InterruptLatency class
    * updated and pretty-printed the Json example

commit de5ccefa
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 12 15:57:21 2017 +0200

    Closes #54 - Tapasco return code is wrong

    * would return 0 when Configuration was parsed successfully
    * now returning folded result of tasks

commit 60d8e621
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 12 15:24:17 2017 +0200

    Closes #26 - Check Vivado Compatibility

    * tested HLS and bitstream composition for 2016.2 - 2017.1

commit e5f2ad89
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 12 15:05:21 2017 +0200

    Closes #56 - Vivado HLS 2016.4+ crashes during HLS

    * error messages were the problem: Tcl's exec interprets any output on
      stderr as an error condition by default (not only the actual retcode)
    * this insane behavior can be fixed by using -ignorestderr parameter

commit 310d1be1
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 12 14:59:25 2017 +0200

    Closes #5 - VC709: Support multiple FPGAs in JTAG chain

    * scanning all targets and devices, programming the first VX690T
    * improved the bit_reload.sh scripts:
       - normal option parsing
       - enabled verbose output w/o driver reload
       - disabled 'default' bitstream (I mean, WTF?)
    * moved bit_reload in VC709 into standard location in module

commit 5cec7aba
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 12 10:56:17 2017 +0200

    Closes #2 - Fix number of threads in Compose

    * replaced maxThread var in trait Composer by implicit argument to
      compose method, facilitates easy pass-through
    * in Tcl, tapasco_jobs global and the Vivado maxThreads setting are only
      written if maxThreads is not None (default value)
    * dse.Run sets the implicit to 1

commit ce53b756
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 12 10:13:39 2017 +0200

    Remove TAPASCO_FREQ environment variable

    * no longer used; tpc_freq must be set in scripts

commit 7bb05b40
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri May 12 09:57:47 2017 +0200

    Closes #50 - Timing Report: Reports false max delay path

    * TimingReport would report _first_ max delay path; but there can be
      many, they are ordered by clock in the report
    * added RepSeqMatcher to extend SequenceMatcher for Seq[T]
    * sorted paths by slack and picked the ones with minimal slack (max
      delay path) and maximal slack (min delay path)
    * also fixes minDelayPath, which is pretty useless, however

commit a1dc2f2e
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu May 11 18:54:34 2017 +0200

    Closes #51 - Parse component.xml to exclude Verilog includes

    * LS patched this on TPC, forward ported it to TaPaSCo:
    * OOC must extract Verilog includes, but must not add them via add_files
    * hard to determine what an 'include' is, but IP-XACT component.xml
      contains this information -> parsed to an exclusion set
    * confirmed to work with example from LS and standard "counter"

commit ec9f64e1
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu May 11 17:34:51 2017 +0200

    Closes #21 - OOC: Do not delete files on error

    * EvaluateIP would delete files from .zip regardless of result, leaving
      the directory in non-reproducible state, fixed
    * also fixed: in case of success, the base directory would not be
      deleted due to wrong order of `deleteOnExit`s

commit 87f0de99
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu May 11 17:10:55 2017 +0200

    Add Terminology man page

commit a02ac9e1
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu May 11 15:40:40 2017 +0200

    Closes #46 - Man pages

    * wrote man pages for all executable in bin/
    * also wrote man pages for the basic API headers and libraries

commit 701420ae
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed May 10 18:10:20 2017 +0200

    Implement PyNQ platform support

commit 17ec1ec1
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed May 10 12:13:46 2017 +0200

    Increase Vivado requirement to 2016.2+

commit 6c41bb6f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 9 19:44:30 2017 +0200

    Rebranding ThreadPoolComposer -> TaPaSCo

commit 7be62ffb
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue May 9 16:35:10 2017 +0200

    Squashed commit of the following:

    commit 3f9c305c39b7efe74fefe3cbe2e39e36247925dd
    Merge: 13be23c fa08f25
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue May 9 09:40:42 2017 +0200

        Merge branch 'master' of gitlab:jk/threadpoolcomposer into dev

    commit 13be23c2007cc97d8b9b07b1b96aa0f7a653ec37
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon May 8 18:31:14 2017 +0200

        Split view.dse into dse.config and dse.graph

        * too many classes with different purpose in one package are confusing
        * moved classes related to ConfigPanel into 'config' subpackage
        * moved classes related to DSE graph into 'graph' subpackage
        * moved SliderPanel into 'itpc.common'

    commit 894678fd2730f9a6b5004992c2c521b0fafe8770
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon May 8 18:12:49 2017 +0200

        Move selection.dse to view.dse

        * DSE views are not Selection/Detail style, needed to move

    commit b016011532b4071c1de28728cd68f4ea2c2b8eff
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon May 8 16:15:59 2017 +0200

        Improve inline documentation

        * added implicits to documentation
        * fixed scaladoc warnings / link errors (as far as possible)
        * minor refactorings w/o functional changes

    commit 2ea522006a1bb5291139ea9e9620f1a1f3ec81aa
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri May 5 14:05:13 2017 +0200

        Add itpc package description

    commit 7964227ecf8dd799932a8298bf92613ac3e2eac5
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri May 5 13:39:08 2017 +0200

        Reify LogViewer and ReportViewer

        * added commands tpc-logviewer and tpc-reportviewer which can be used to
          start the two classes directly (w/o sbt run)
        * added corresponding sbt commands
        * refactored SimpleSwingApplications into 'executables' package

    commit 573627f4334ceb2ebb01b536dca63e14b857ce5d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 22:17:02 2017 +0200

        Improve scaladoc in package activity

    commit fd208eb6499814086c6b824afa316996c5b90c22
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 22:16:24 2017 +0200

        Remove unused import

    commit 831ecefa412d84125f2a9884983aa8c38aa03d7a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 21:25:39 2017 +0200

        Bugfix HLS buttons

        * HLS buttons stopped working, broken during refactoring
        * re-implemented the basic logic, works now
        * building for all Targets at the moment, not just selected one

    commit 0f013c4ebd598eab11ea70143145117a79732194
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 18:04:51 2017 +0200

        Fix scalastyle warnings

    commit 9e5a43c80525ce0cf78638a261a6edbad8aabfb8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 17:32:27 2017 +0200

        Remove "Dump debug states" item

    commit 19ab8421c365c333fff4eaab15f4f224a61f259a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 14:43:47 2017 +0200

        Remove debugMode flag in iTPC

        * for testing purposes, the default job would automatically set
          debugMode to random
        * resetting to None, if required, can be supplied via command line

    commit 0540785d4c463c9f0e1412f992c206cc4bae5d44
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 14:41:29 2017 +0200

        Fix missing repaints in main graph while DSE runs

    commit 9073f526586d91f739a737d7cd51ae839307598b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 14:41:06 2017 +0200

        Log message when DesignSpaceGraph is cleared

    commit 8d620970183cf199f83c4ccda8a06571292b01c1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 14:39:43 2017 +0200

        Bugfix: Do not reset DesignSpaceGraph on task completion

        * reason: new UI button lets user decide when to switch back to
          configuration, until then data needs to be retained

    commit 3c3d6bdb38fcd7e0def0dbdf6246d837a9b7fe3f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 14:38:57 2017 +0200

        Bugfix in ColorGradientMap regarding invalid doubles

    commit a1d10ac0fdba0c749ba30487a02130bbb5c83d22
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 14:36:38 2017 +0200

        Fix DSE page in main app

        * re-implemented DSE page using multiple ViewControllers
        * ExplorationConfigController controls the ExplorationConfigPanel
        * ExplorationGraphController controls the ExplorationGraphPanel
        * ExplorationController switches between the two
        * switch to EGP happens when exploration task starts
        * switch back to ECP happens when user clicks button in EGP after DSE
          finished
        * previous functionality completely restored

    commit 5a1fc594e441cab26949a30cda8d54d2b9643b66
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 13:41:37 2017 +0200

        Implement primitive log viewing tool to browse logs

        * Swing appplication, first parameter should be logfile
        * reads DSE logs (Json) and rebuilds the DesignSpaceGraph
        * UI is only the graph portion of the DSE

    commit d41c0d42659c18f02c55cbeb871b67f673442056
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 13:40:14 2017 +0200

        Selecting events in table should focus elements

        * broken during refactoring, used to work
        * re-implemented, works

    commit 63c2e90954fa9d0f2f5f96358144719249929744
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 13:18:34 2017 +0200

        Implement graph chasing keyboard shortcuts

        * move forward/backward in batch
        * move along generated / pruned edges
        * add focusing of selected elements

    commit ac1d8e3a5e160cc313e0cee5cf745a6f4421b505
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 13:15:55 2017 +0200

        Demote item event logging in Graph to trace

    commit 355ca7c09bf5bddcac123572ea07186f43f486e1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 10:58:46 2017 +0200

        Fix scalastyle warnings

    commit 96e6fd5aa42f617995aefffd2fe4dfa3f52ec7e1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 10:58:15 2017 +0200

        Fix bug in MainViewerHighlight

    commit e0cb378fcba2c314d4093437cf1e5c537c79a8cf
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 10:56:16 2017 +0200

        Implement detail panel for design space elements

        * first detail panel should show details for the run/element
        * added to ExplorationGraphPanel at top left
        * implemented setter logic for picking
        * no unset implemented, once picked, data will remain

    commit 2e5b9b726fe2a1f5c63e4268a139719275741587
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 4 10:55:31 2017 +0200

        Implement tables for ReportPanel

        * now supports all currently implemented Report types
        * simple Table in a ScrollPane

    commit 75cbb00fae9489994e767f1d0a4997eb43f15d68
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed May 3 15:36:11 2017 +0200

        Reimplement picking support, add report views

        * Graph now listens to ItemSelection in picked state to generate events
          for picked elements
        * implemented basic ReportPanel, which can display arbitrary reports
        * replaced placeholder in graph view with new ReportPanels
        * added logic to retrieve Composer.Result and populate ReportPanels, but
          data display itself is not yet implemented

    commit 39d577e06c0def3739a3cca4dcf9901bd391c95a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed May 3 15:33:29 2017 +0200

        Add mainClass in MANIFEST for jar

    commit dbd73683330ff0b4324ec6112b8788d9bc766ad8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed May 3 15:33:08 2017 +0200

        Add vim temporary files to .gitignore

    commit 64671e2d5774cec25bb1c0d32595c30d31c4cd2c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 21:42:00 2017 +0200

        Reactivate assertions in build.sbt

    commit dd8a82410fb94914689f334d1531dd46a563cb2b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 21:38:32 2017 +0200

        Add requirement and trace output to AreaUtilization

        * apparently AreaUtilization would sometimes be called with empty
          compositions
        * added a requirement to catch those cases; also added trace and debug
          output to simplify debugging

    commit 6f9478f2ece0ac6b679514554d3fb6f3a2227d17
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 21:35:22 2017 +0200

        Fix broken Target when loading DSE logs

        * when loading a DSE log, the default platform (in this case VC709)
          would be selected instead of the one used to generate the log
        * this lead to different heuristic values and area estimations, since
          they are not taken as is from the file, but recomputed on demand
        * fixed by appending the full Configuration to the logfile format
        * nice side-effect: full DesignSpaceExplorationJob can be restored
        * simplified the Json SerDes

    commit 8b756add85931d97cc52bf3f95a9f24aa1f6dba3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 09:59:41 2017 +0200

        Add direct access to exploration log table events

        * when replaying via Publisher/Listener the original timestamps get lost
        * implemented direct access to log events via setLogEvents (no get)

    commit 23b57bc16b1eb84476cde77e77347481486c5317
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 09:43:27 2017 +0200

        Make panel in ExplorationGraphController public

        * added strongly typed property for the ExplorationGraphPanel

    commit c75b57fbf825ef8edf4a377ff2f0d17a618735b0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 09:41:15 2017 +0200

        Fix layout issues in ExplorationGraphPanel

        * report panels now always resize to 20% each
        * main split is 75% graph, 25% bottom
        * satellite graph is also 20%

    commit ea1a2a2017a8017a4a9ec80573e7d187d1a21b2e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 09:39:24 2017 +0200

        Fix auto-centering and -scaling in Graph panels

        * problem was listening to the outer component's resize events instead
          of the VisualizationViewer's: events would happen _before_ the VV is
          initialized and its matrices would be 0, thus the errors
        * fixed by listening on the inner component on switch

    commit b34bbeec6b1f5e0bdf67e301fae2e4097ed7a7ca
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 09:35:37 2017 +0200

        Make ExplorationLogTableModel compatible w/replay

        * replay null's Task and Exploration instances in events
        * explicitly wrapping in Option and generating different formats in
          case of null
        * added TODOs to check if it would be better to change Events

    commit 70c10a41fd9fdccb186a8c7e940d577a98ff9f2f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 09:35:04 2017 +0200

        Remove redundant try..catch from Centering

    commit 5208f0cb3e4ac2fe3cd2d3e4c8d206c6546ea90a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 09:34:19 2017 +0200

        Fix DesignSpaceExplorationTask

    commit 062f24694579c8db02f0c760e4ea51f72413d834
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 09:32:55 2017 +0200

        Make iTPC globals private to prevent use outside

    commit a5ddfa79deddd6a4f2a28e673c3557c387131161
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 09:31:34 2017 +0200

        Change Exploration base path to Path

    commit 7fa7e426eac7e23e4e07593dd624a352540eb002
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 06:58:30 2017 +0200

        Implement replay feature to load Json DSE logs

        * ExplorationLog can already be read from file
        * added load method to DesignSpaceGraph to accept a filename and replay
          the DSE events into the graph via Publisher/Listener interface

    commit 7e708ab54c5bef0a68e0492cffb6a3b0ae997575
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 30 06:54:24 2017 +0200

        Bugfix RunGenerated Json SerDes

    commit c20756260c7529d647f712c5b0e4beed882919e9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 26 20:21:38 2017 +0200

        Reboot DSE panel

        * work in progress: implementing new report panels and re-implementing
          the central panel
        * ExplorationConfigPanel it the configuration portion only,
          ExplorationConfigController its corresponding ViewController
        * ExplorationGraphPanel is the graph portion only,
          ExplorationGraphController its corresponding ViewController
        * both will be reunited in a very simple ViewController that will switch
          between them
        * introduced new Graph global to track state of JUNG graph for exploration
        * auto-tracks Task starts and get the exploration currently running
        * tons of changes all over the place

    commit db5d40f569366cbfcc14f099d15490dfa7bd09bd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 26 20:18:20 2017 +0200

        Add Target convenience getters to DesignSpaceExplorationJob

    commit 5b9f6ba4403661810c9e6526ab4fe1a48077372c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 26 20:17:40 2017 +0200

        Bugfix dividerLocations in TripleSplitPanel

    commit d86a37b240287225dd452ec245d164336d4eeca8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 26 20:16:17 2017 +0200

        Move core DesignSpace routines to companion object

    commit 265f97bf8140b9a91353c1c5c70e1beb52a0635f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 26 20:15:37 2017 +0200

        Implement modification methods on Composition

    commit 7a544af76425ba859c20ca4e3403beefffbcbfca
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 21 18:29:47 2017 +0200

        Fix model

        * iTPC's internal `Model` class is bloated, obsolete and duplicates code
        * replaced it with a cleaner construction approach:
          `View` instances (alias for `scala.swing.Component`) are managed by
          `ViewController` instances, which control the entire wiring of their
          view (and subviews)
        * App constructs ViewControllers, which construct their views and can be
          nested, make views accessible
        * Views only communicate via Events, to which their Controllers subscribe
        * added `globals` package which contains singletons for iTPCs global,
          shared state: Configuration, AppState, Job and TaskScheduler
        * approach only for iTPC, in general global state is disfavorable
        * Controllers manipulate either internal or global models
        * EntityManager: add method to compute all Targets
        * Composition: add methods to modify compositions

    commit 3e88b817a1b83ecf0711d1f80f5337c4a9e86c6c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 21 17:58:15 2017 +0200

        Bugfix missing update to base path for Compositions

        * base path for Compositions was not set when loading a Configuration

    commit 4cff179286a7af301f42c1550b0fe4d6aec93c7a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 20 16:48:23 2017 +0200

        Loosen coupling between App, AppMenu, Tasks

        * test balloon: Removed tight coupling via Model, replaced with
          Publisher/Listener model instead, Controller takes over the "wiring"
          of the components
        * seems like a cleaner approach, but unclear how to scale

    commit 2a4938cf4c4621601f0743152f0b94696b26add9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 20 16:35:01 2017 +0200

        Remove public listeners array from Publisher

        * interface was not well designed, e.g., add method cannot easily be
          overridden in Publishers
        * removed listeners object and replaced it by generic collection methods
          (+=, -=, foreach, map)
        * where this collides with methods in the super class, a publisher
          object should be created instead (see e.g., AppMenu)
        * much cleaner approach and thread-safety

    commit 71c94b5def29652983eba4ec3012b059912005e6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 20 14:43:59 2017 +0200

        Add value property to SliderPanel

    commit b04a046dc6be1e4df6b32be56c30cf6f78ca2cf3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 19 22:11:44 2017 +0200

        Remove border from pruned nodes

        * also made fill color half transparent again (was lost with new
          implementation of HeatMap)

    commit 9ee8c6bfeecaa54ae08de0975e7b5329818f29bd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 19 22:10:02 2017 +0200

        Fix bug in DividerSync

        * DividerSync updates too early with zero sizes, causing Exceptions
        * fixed by checking input values before setting
        * also moved setting to EDT thread

    commit 2a78cee31b429a0048cc9dbecb0e65dc102c57bc
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 19 21:29:39 2017 +0200

        Fix and improve heatmap color scheme

        * HeatMap implementation was discontinous
        * added generic linear gradient map implementation `ColorGradientMap`
        * implemented better looking, continous heatmap based on it

    commit 2a656a187c3b3ced3c488a4c836f2154e6caa176
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 19 14:13:40 2017 +0200

        Fix some scaladoc problems

    commit fdb3f74192f31789f28b602ff0e32a712b200332
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 19 13:27:07 2017 +0200

        Silence DSE parameter number scalastyle warnings

        * added TODO to revisit this problem at a later time
        * maybe some grouping of the DSE parameters could fix this properly?

    commit 181b34dca0a455dc9adfe282b989c9972844c4c0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 19 13:22:41 2017 +0200

        Refactor DirectoryWatcher to fix scalastyle warnings

    commit 2ca93fd1259ed5c03b3dcca93a1111994cba4a1e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 19 13:12:31 2017 +0200

        Refactor ComposeTask to fix scalastyle warnings

    commit b652b41c6cd04afcbfb1bbc81d6e0fbb4533940e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 19 13:08:51 2017 +0200

        Refactoring to fix scalastyle warnings

    commit c5787beebf41d23638272a40d226b1ece38711ea
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 19 13:07:59 2017 +0200

        Refactor DSE config panel to fix scalastyle warnings

    commit 1928a4ba89d29b9e9da89987d4dbd7c1f90416ce
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 19 13:07:15 2017 +0200

        Silence scalastyle warnings of cyclomatic complexity

    commit 1c97cc4d6e65611ba4a0d308927826744100e8f7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 18:53:34 2017 +0200

        Refactor EvaluateIP activity to fix scalastyle warnings

    commit 2af864cfa2a09dc9942e96501d23bf47157fda02
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 17:46:33 2017 +0200

        Refactor VivadoComposer to fix scalastyle warnings

    commit be5a9a139f02c908b17182884f494923daf97f86
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 14:28:49 2017 +0200

        Refactor Import activity to fix scalastyle warnings

    commit 6135d87e369e0956c17b2cd99abe41037f207173
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 13:57:06 2017 +0200

        Merge legacy package 'dse' with new code

        * itpc.dse package contained replacement code for DSE
        * now merged all code in 'dse' package

    commit 07a9a54ab336e77c25aab07c1365690f374f866a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 13:41:47 2017 +0200

        Implement UI to exit DSE after finish

        * after DSE finished, there should be a UI element to exit the DSE mode
          and start the next exploration
        * added a button that will be activated
        * needed to add stopExploration method to DesignSpaceExplorerModel

    commit c29bd09dbe85d52ded505f611c4c5c840603f493
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 12:55:59 2017 +0200

        Remove batch size warning when SLURM is enabled

    commit 1e938aac9fee5621a61c14e97cb04943685b54c4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 12:53:19 2017 +0200

        Fixed size nodes are not ideal

        * DSE main graph shows nodes in fixed size, even at high zoom levels
        * produces a lot of overlaps e.g. [arrayinit x 1]
        * added upper bound for scaling factor to allow zooming in and
          discerning individual runs
        * useful for tracing edges, too
        * changed colors a little bit, still ugly

    commit 7140f1a3cb06b89f284bc11b15d6a0c4b6996934
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 12:16:48 2017 +0200

        Increase main loop delay to wait for Frame close

    commit 7a63b85243466da9c73ac15fe9b97bb2fbdd00b0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 12:16:24 2017 +0200

        Move DSE result dialog to EDT

    commit 136c749fd1c004805bba443d1c9e2baf75ed5e2f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 11:42:39 2017 +0200

        Bugfix DSE with successes in multiple batches

        * logic to return successful element was broken for the case when there
          was a success, but a TimingFailure generated a better feedback element
        * if the batch containing the feedback element failed, the DSE would
          return no element, instead of the success from the previous batch
        * should be fixed, but is untested

    commit 76dc5320f51a8582c24aaf7ef45308ee5ce29faf
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 11:26:43 2017 +0200

        Add result to RunFinished

    commit 31baa18eadd839de2c9e022b65b11724ddfdff3a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 11:05:23 2017 +0200

        Show UI dialog with DSE result on finish

    commit 14acbd31a9dff19af914c9b3dbe04daf70f6b3e7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 18 10:11:21 2017 +0200

        Add final result to ExplorationStarted/Finished

        * started event already contains more detailed info, but finished does
          not even state the result in Json and Log formats
        * fixed that, also added focus on winning element for ExplorationLog

    commit c4d9c695c86c98e68fc48cdb9725bdfe83cdf882
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 11 18:26:48 2017 +0200

        Move Entity-related classes to filemgmt package

    commit d5ce6b3ead649cdb26d838fac5df5c58b5b38858
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 11 18:08:40 2017 +0200

        Fix magic number warnings

    commit a08358d06f3033bfa454a212076a89e267d27c37
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 11 17:57:15 2017 +0200

        Clean unused imports, dead code

        * added compiler warnings for unused import
        * fixed approx. a million instances of the warning throughout the code
        * left as warning for future builds

    commit 933d71dae471290fb8c4db694aa09664055bbd63
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 11 16:07:48 2017 +0200

        Move Publisher, Listener to util package

    commit 6bfce9bebeef3f6d2525406267fab6fbba6d8577
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 11 15:15:49 2017 +0200

        Move file management classes to new package

        * new package 'filemgmt' contains BasePath, BasePathManager, ..
        * fixed references accordingly

    commit 19a6c83af29465aee437d4cd6d79e69f0904f617
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 11 14:32:01 2017 +0200

        Fix problem with DSE logfile names

        * when no logfile parameter is set, DSE task would create a "None"
          logfile (empty), otherwise there would be a directory "Some("
          instead of the actual logfile
        * fixed both cases with proper Option handling in task

    commit 5305035f16c7897a058098229add5d69b97b1174
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 9 09:17:47 2017 +0200

        Simplify VLNV extraction in VivadoComposer

        * unnecessary conversions from and to String/Path

    commit 156583f381ffae752e795b921297f94d05ebdd1c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 9 09:15:53 2017 +0200

        Bugfix computation of resources for multiple consumers

        * fixed subtle bug in the code
        * added logging, trace logs for each check

    commit c54af322013414b93685654f5d838c5f405c2dd1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 9 09:13:06 2017 +0200

        Remove resource requirements in debugMode

        * ComposeTask should not require actual resources for demos

    commit e69cc75f82197bfe7962967297c213067ad1d976
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Apr 8 07:18:31 2017 +0200

        Prepare for Demo

        * increased main window size (again)
        * start with deactivated DSE (no dims)
        * move status panel text to the left (Mac OS resize icon hides text)
        * remove "add" debug button from Tasks pane
        * fix HLS builds: use job instead of HLS task to import cores

    commit ebd33fdf814296b27025d10ff7c98965d8b7ba09
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 7 13:41:42 2017 +0200

        Add benchmark host data to DescriptionPropertyTable

    commit 5ffcf6341d532850ede9a0120986c26ca53b1ec7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 7 13:10:46 2017 +0200

        Bugfix: only check for SLURM jobs on exit if enabled

    commit 78ae03e836689483d4eda04fedcf5058248a5d2f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 7 11:43:26 2017 +0200

        EntityManager: Issue warning on failed builds

        * builds of file-based entities fail silently, difficult to debug
        * added builder methods for the entities, which adds logging for fails
        * fail warnings should appear at most once (memoization)

    commit c050df0ac9fb6e390e6404db450899b55793b61d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 7 11:41:53 2017 +0200

        Add bitstream to Composer.Result, improve logging

        * Compose and DSE should output at least one message with a summary of
          the final result
        * added bitstream location to Composer.Result
        * logging improved

    commit 824dda3636c640010ff770267e800bd20625eca7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 7 11:39:53 2017 +0200

        Add simple toString for DSE Dimensions

    commit 82bc806ee5cb38230e13ad6cf2b59041ad385ddc
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 7 11:38:11 2017 +0200

        Fix usage for DSE: missing frequency

    commit 500495ce22e065bbfaddae83e11646ad3571e14d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 6 18:58:49 2017 +0200

        Fix scalastyle warnings

    commit 97acf5775718bd2798547e1d5fca57dfeded7960
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 6 18:57:11 2017 +0200

        Add flag for BasePath if dirs should be created

        * some tests generated thousands of directories since the change that
          directories are created on set
        * added a new flag which is true by default, but can be deactivated for
          the tests
        * also added default values for the defined dirs of BasePathManager:
          only compositionDir and coreDir will be created on set now

    commit b7ab7145f81e78ae5e542febf5467c4316130fa1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 6 18:55:25 2017 +0200

        Ignore scalastyle warnings for Implicits

    commit e74ceb2a589bb137214abbf0a919233a6cdc5211
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 6 18:55:09 2017 +0200

        Modularize the command line parser

    commit a0fdb65de6f67dd6b1ff10bd103957a859a9fd55
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 6 17:24:03 2017 +0200

        Squashed feature branch for Jobs replacing Command

        Squashed commit of the following:

        commit cdc932ba7d2790c1caa3d47b9f76b07c2ed74e4c
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Apr 6 08:50:36 2017 +0200

            Slow down DSE demo mode

            * increased random delays in debugMode r

        commit 0c12d6bbcdbecd3d94f31d4d7745747726dc9d2d
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Apr 6 08:50:09 2017 +0200

            Bugfix ComposeTask: Frequency is now Double everywhere

        commit dbf1db6bf513605bb480ddd31da604506c659ebb
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Apr 6 08:48:35 2017 +0200

            Bufix UtilizationReport: BRAM is given in Doubles

            * Xilinx should know that there is no such thing as 0.5 BRAM, but they
              are reporting it anyway
            * fixed parsing accordingly

        commit 71242070a0643c615601ebdf2949f61f040c4f40
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Apr 6 08:47:40 2017 +0200

            iTPC: set DSE into demo mode for presentation

            * no GUI elements yet for debug modes, so needed to hardcode
            * real mode worked on endor

        commit 1690d0206d50a7c8b61ed7e0459e822eb56c4345
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Apr 6 08:46:12 2017 +0200

            DirectoryWatcher: Demote watch errors to debug

            * happens frequently when Vivado deletes folders before iTPC can start
              to watch them
            * pollutes the log, so demoted log message

        commit 01e7bd74a0a2c6e6f752585efa5eec8f64f39ba4
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Apr 6 08:45:39 2017 +0200

            Remove test logging output

        commit 61b858ed7a96c333be4e7d08e12514a168b9b063
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Tue Apr 4 18:23:38 2017 +0200

            Re-implement SLURM support

            * all console jobs and executors now support slurm
            * there is a new global config parameter "slurm" and corresponding
              entries in the Json and CommandLineParser defs
            * fixed a bug concerning Json parsing: verifying is called later than a
              .map on an element; this lead to unexpected Exceptions when TPC tried
              to parse an HLS implementation as an Composer implementation (bad
              gotcha, need to remember this problem)
            * cleaned up DSE output, Runs are now numbered sequentially using an
              AtomicInteger in Exploration
            * fixed result parser for SLURM DSE (would not pick up results)
            * improved log output in several places
            * Slurm itself is still global state, left for later fix
            * composer/HLS implementation is not properly passed down in DSE,
              defaults to Vivado - won't fix for this version

        commit 1ac53293ccfaba43c19f0da60e5f8ba073a3ba36
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Tue Apr 4 09:53:04 2017 +0200

            Reduce task package log level to debug

        commit 36864aa0dba9353054316654eb8f237db1f90b1b
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Tue Apr 4 09:48:57 2017 +0200

            Implement DSE job executor

            * rewrote parameters to DesignSpaceExplorationTask, removed Model
            * implemented executor
            * removed singleton stuff, instead DSE task cannot be launched if a DSE
              task is already running (ResourceMonitor)
            * required new canStart method in ResourceConsumer and a delay in Tasks
              to avoid parallel starts
            * fixed divergence issue in Writes[Job]
            * added usage info for DSE job, added command line parser grammar

        commit 26fdb2b68cd91b6d1225b72bf8b49a88708f0bc9
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Tue Apr 4 09:44:33 2017 +0200

            Add default values for DesignSpace.Dimensions

        commit afd14593bd731ee90d960036fc4eea8552a4cdf4
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Tue Apr 4 09:44:01 2017 +0200

            Fix Json Writes divergence problem

        commit 2e077d591f9821ded1240048aad326f5ddb8606f
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Tue Apr 4 09:43:32 2017 +0200

            Remove check for arguments at start

        commit 136c6bbe5fbe12d65ee9d54ef5f21a9e6f5f6b75
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Mon Apr 3 18:09:05 2017 +0200

            ComposeTask: implement debugModes

            * optional debugMode string is now interpreted:
              s generates only successes
              p generates only placer errors
              t generates only timing failures
              r generates random results after random delay
              everything else generates other error
            * useful for debugging

        commit 949a076b4c0c91f74871c7e9fcf7070df25197a5
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Fri Mar 31 09:42:36 2017 +0200

            Fix missing FileAssetManager init in itpc

        commit aeadd4b92aea8ca35f9e003371e3ced6b84c488f
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Fri Mar 31 09:38:49 2017 +0200

            Implement debug mode for Compose

            * added parameter debugMode in all representations of ComposeJob, which
              can be an arbitrary string
            * if the string is non-empty, the ComposeTask will return a random
              result value after a random delay
            * primary use is debugging of the DSE

        commit bcfe833e448357a3c6fe47881708a64b02419012
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Fri Mar 31 09:36:40 2017 +0200

            Make BasePath create directories, if necessary

        commit 7c4e5de6e7bc41860a6105d74343dd7690202b70
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Fri Mar 31 09:36:10 2017 +0200

            Improve error messages when Cores are missing

        commit e9bca3de6e358af9e1ccc47905ed3d8c45d83828
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Fri Mar 31 07:37:03 2017 +0200

            Fix bug in itpc command

        commit 5515524f95893f8055288875a7449d0358051c80
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Mar 30 17:36:38 2017 +0200

            Implement batch mode execution for all Jobs except DSE

            * fixed automatic HLS for Compose jobs, kernels are automatically
              synthesized and imported
            * skipping existing cores for synthesis, if zip exists
            * skipping existing cores for import, if core.description exists
            * improved ComposeTask arguments
            * added ComposeJob "Implementation" property to select Composer
              implementation + supporting code (Json SerDes, CommandLineParser)
            * test runs were successful, yay!

        commit 64203140f495a8afb88adcc13b0527d4b0ab3e41
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Mar 30 13:36:27 2017 +0200

            Fix missing prefix bug in CoreStatistics

        commit b079f55cdcd86aaf4dd8f05e099b26a9f8022bae
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Mar 30 13:34:55 2017 +0200

            Implement usage help for TPC command

        commit 3cb1cea9554e53d6c02bde488a15ea921a1893e6
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Wed Mar 29 21:25:46 2017 +0200

            Refactor Commands to Executors

            * use Executor type class to implement execute method with varying
              implementation on Job itself
            * implementation of execute is defined by implicit Executor
            * previous instances of Command were replaced by Executors
            * moved Executors to package jobs/executors

        commit 54e2291f27a8a1fbec2c64239c9bc7008936b811
        Merge: ada14f9 9971926
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Wed Mar 29 14:46:03 2017 +0200

            Merge branch 'itpc2' into itpc2-jobs

            Conflicts:
            	src/main/scala/threadpoolcomposer/Common.scala
            	src/main/scala/threadpoolcomposer/ThreadPoolComposer.scala
            	src/main/scala/threadpoolcomposer/activity/CoreStatistics.scala
            	src/main/scala/threadpoolcomposer/activity/Import.scala
            	src/main/scala/threadpoolcomposer/activity/composers/VivadoComposer.scala
            	src/main/scala/threadpoolcomposer/base/Configuration.scala
            	src/main/scala/threadpoolcomposer/base/ConfigurationImpl.scala
            	src/main/scala/threadpoolcomposer/base/json/package.scala
            	src/main/scala/threadpoolcomposer/commands/Compose.scala
            	src/main/scala/threadpoolcomposer/commands/HighLevelSynthesis.scala
            	src/main/scala/threadpoolcomposer/dse/Alternatives.scala
            	src/main/scala/threadpoolcomposer/dse/DesignSpace.scala
            	src/main/scala/threadpoolcomposer/dse/Heuristics.scala
            	src/main/scala/threadpoolcomposer/itpc/common/EntityManager.scala
            	src/main/scala/threadpoolcomposer/itpc/model/UserConfigurationModel.scala
            	src/main/scala/threadpoolcomposer/reports/SynthesisReport.scala
            	src/main/scala/threadpoolcomposer/util/AreaUtilization.scala
            	src/main/scala/threadpoolcomposer/util/FrequencyLimit.scala

        commit ada14f9aebee9cd889a30431d1d5278b10316f86
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Tue Mar 28 13:35:36 2017 +0200

            Fix unit test for Configuration

        commit c6caf4254831ef5e978c3aadab05aac1d1f7f1f5
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Tue Mar 28 13:22:35 2017 +0200

            Move CommandLineParser to top-level package parser

        commit d0c0a436d94d08a8dcb3a915f6d9f11fb951055b
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Tue Mar 28 13:17:47 2017 +0200

            Improve Json SerDes

            * added implicits to enable appending and prepending values to Tuples in
              a type-safe manner
            * this made most extended unapply methods (wrABC) obsolete, since values
              can be easily added to the deserialization tuple
            * used in both jobs and base packages

        commit 3f05cc3c011f1094a2aec5047d3f9885af41b25b
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Mon Mar 27 17:40:58 2017 +0200

            Fix unit tests for Core

            * Core now requires build target
            * adapted example files accordingly

        commit 5fa64d1b37cd7676207e9976ca29b80a8c87937f
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Mon Mar 27 17:28:24 2017 +0200

            Implement new parser for command line args

            * simple key-value-pair parsing is no longer adequate for the complex
              objects generated from the command line arguments
            * this has been true before, but became very obvious with the new Job
              objects, which could not be properly parsed with the old format
            * implemented a full-blown parser with a convenient syntax
            * restores the command-line arguments (almost) to full control
            * some simplifications had to be made regarding relative paths; if I
              ever find the time I will fix the remaining issues, until then some
              definitions cannot be externalized (e.g., Compositions)
            * rewrote unit tests to reflect new syntax and objects

        commit 244bacca592e66905943e2b5ad90a681b4350305
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Fri Mar 10 18:57:42 2017 +0100

            Add missing Jobs defs + Json SerDes

        commit 31a48d2ab111a5856cffa90adb25b13587b72401
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Fri Mar 10 18:49:23 2017 +0100

            Implement 'jobs' structs for each activity of TPC

            * Configuration object is a problem; it contains many parameters
              specific to a single activity and is a sort of catch-all
            * it becomes increasingly unwieldy to maintain and should be refactored
            * implemented a 'jobs' array instead, which contains structs with
              specific parameters for each activity, e.g., HLS, Compose, DSE.
            * each Job is Json serializable
            * idea is sound, but made it necessary to already commit to the switch
              to the EntityManager, which I'm not so sure about
            * need to think more about the problem before committing this to itpc2

    commit fa08f25ac5321d8cd282923f334077e560a27024
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Apr 3 15:47:00 2017 +0200

        VC709: Bugfix large allocator size limitation

        * large allocator was limited to 256MB/per allocation
        * increased to 2GB
        * increased tpc_benchmark tests up to 2GB

    commit f3f563b513e63c3532fe938806bc7c9c4548bc82
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 22 13:34:20 2017 +0100

        HLS: Fix problem regarding kernel names

        * when top function name name and kernel name differ, co-simulation with
          Vivado HLS can fail due to inconsistent renaming
        * fixed by not renaming at all

    commit 7dbbc96ff22b566dc811de1549cbcdc1af49f127
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 21 16:59:18 2017 +0100

        tpc-debug: Implement 'peek' command

        * now supporting three key commands: peek, poke, poke_and_wait
        * peek is 'r', poke is 'p', poke_and_wait is 'w'
        * also added hints for the keys at the bottom

    commit 99719269f185bd7a2c0265532205bdaf5192c936
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 17 18:22:37 2017 +0100

        DirectoryWatcher: reduce logging

        * directories can disappear quickly, reduced corresponding messages to
          DEBUG level

    commit 1a8aed96a9eefde4bc5548bb4c6ecd251468842b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 17 18:22:17 2017 +0100

        Fixed minor problems

    commit d11f09ed078d023f476ca3e2b4acd2711c1c3768
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 17 17:35:28 2017 +0100

        Replace legacy file management with FileAssetManager

        * removed all legacy description finding/parsing code
        * replace all call sites with references to FileAssetManager
        * fixed broken directory configuration for initial Configuration (now
          correctly set in FileAssetManager)
        * added `target` field to Core for easier searching
        * added explicit kernel,target -> core mapping method in EntityManager
        * added method to find Target for Report file
        * fixed minor FIXMEs that were in affected code

    commit 6281295abed3607562d919d7f88eeeb8554c81da
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 17 12:15:41 2017 +0100

        Use FileAssetManager in ConfigurationImpl

        * removed legacy code for finding entities

    commit bd3f8fdc90cc63a392c3550db26d69ff17fcddbb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 16 16:59:51 2017 +0100

        Isolate Entity management

        * entity caching/management should be handled similarly to Reports
        * renamed EntityManager to FileAssetManager
        * FileAssetManager consists only of few components: DirectoryWatcher,
          BasePathManager, ReportManager and (new) EntityManager
        * moved code from EntityManager into new class EntityManager
        * renamed unit tests for ReportManager
        * implemented very simple unit test for the FileAssetManager

    commit 4c8204da11344c99ede1f28a1fc82beae84c2b05
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 15 16:02:04 2017 +0100

        Rename ReportCache to ReportManager

    commit ac66feab7aa79834db65f5aa57672f6d5e16e7ea
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 15 15:57:00 2017 +0100

        Replace report management in EntityManger with ReportCache

        * removed all code related to reports and replaced it with a single
          ReportCache instance `reports`
        * adapted call sites accordingly

    commit 6d71328218e167b3fd1c01f36a5b53832bacc1e7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 15 15:55:14 2017 +0100

        Forward EntityCache events from ReportCache

        * also add reset and clear methods to reset underlying EntityCaches
        * implemented dump() method for debugging

    commit db4504cfb2f35810a7efa96217c7873b98a8277b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 15 15:54:35 2017 +0100

        Re-include Compositions in Entities list

    commit 9d448da9f0e664a05d82fa75338d5d291f1ab43d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 15 15:53:38 2017 +0100

        BasePath.toString should return underlying Path.toString

    commit 8ed5bbf68fef89c55003058ee21adb283800b5a0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 15 14:55:47 2017 +0100

        Implement ReportCache for all report kinds

        * supports power, timing, area and synthesis reports
        * maintains EntityCache instance for each kind
        * covered by unit test spec

    commit 2a4ec2421ade3d7424ad113e9d439c7389615fc4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 14 18:16:06 2017 +0100

        Bugfixes in DirectoryWatcher

        * full path was not computed correctly, only containing directory would
          be returned as path in events
        * fixed that by resolving full event details
        * fixed timing issues when nested paths are created quickly by
          implementing a new directory walking method: compares all entries
          against a timestamp and generates events if their last mod times or
          creation times are after that timestamp
        * new method catches fast file creations, which used to fail, but is
          still not perfect; best as it gets with 'WatchService'
        * caught these bugs with new unit test, once again proving that one
          should always write them first, or at least after first prototype

    commit 152334adb1b32bb581215307121b53948d7caad1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 14 18:14:54 2017 +0100

        Make DefaultEntityCache object private in itpc

    commit c350fd16ed7f410c88d467fa01605832170dc5e9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 14 18:04:24 2017 +0100

        Implement unit test suite for EntityCache

    commit c2f2bcc26cca27ba3f4924b884893de1e340c79e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 14 18:04:02 2017 +0100

        Implement unit test suite for DirectoryWatcher

    commit b8177e6fc5985b5d96ee4ad36064cac7f78caeeb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 13 10:22:20 2017 +0100

        Implement unit test for BasePathManager

    commit 8b4f44f1ba66dda95d723667d1961442d10028c4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Mar 12 10:29:28 2017 +0100

        Implement unit test for BasePath

    commit 620a7ed1e4972d1e1489bf542d5f277ba422f3cd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Mar 11 19:51:45 2017 +0100

        Isolate base path management in EntityManager

        * moved to separate BasePath class, which publishes events
        * grouping all base paths in BasePathManager, which facades as a
          Map[Entity, Path]
        * facilitates removal of most code in EntityManager regarding paths

    commit 85bf2efd3b4ac554fbb3c7c80458c99fe9ede232
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Mar 11 07:40:59 2017 +0100

        Add 'slurm' parameter to Configuration

    commit 254549ecc1b6eef4b17f44b251e9c86496f1b9d4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Mar 11 07:24:57 2017 +0100

        Add 'designFrequency' parameter to Configuration

        * need to replace legacy parameter passing via TPC_FREQ
        * replaced all instances in Scala code

    commit 0cfb2f1889cbb877b609e00ec250aac59cade13a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Mar 11 07:07:56 2017 +0100

        Move `hls` and `composers` to `activity`

        * HLS and Compose are the core activities, should be in the activity
          package

    commit a2d1b921e4e4f1f8beb009fd4b833a7ecec6dc70
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 8 13:19:33 2017 +0100

        Bugfix in Import: link .zip in ipcore subdir

    commit 34781bcad00662bd15abf56dea8435519093207c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 8 11:30:16 2017 +0100

        Bugfix BulkImport when csv is empty

    commit 4fe5e04b44eceb51591e64d7375649e68932927f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 7 19:35:01 2017 +0100

        Add FIXME in SynthesisReport to remove legacy code

    commit 4b736f8b5917107f2a4dcb3acc91c8e409afc9f6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 7 19:34:40 2017 +0100

        Add header to ImportTask

    commit 61e67f4a32c7cb6a6ec971c42eebba99ac343a44
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 7 19:33:07 2017 +0100

        Re-implement 'corestats' command

        * moved logic to activity.CoreStatistics
        * implemented new execution model based on Tasks scheduler
        * new CoreStatisticsTask (simple class)

    commit e3ecdf01c9c4cb46742a1366e50e82925de725a1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 7 14:37:05 2017 +0100

        Fix sporadic exception in DefaultDirectoryWatcher

        * DefaultDirectoryWatcher would occasionally throw an unexpected
          exception because the received watchkey could not be found in
          the paths map
        * simplified code to retrieve full path by using the Watchable
        * needs type cast, but previous version did require one cast, too

    commit 8f75a2abd25a1a24ab76baac9bf740f0be545dbe
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 7 14:34:26 2017 +0100

        Re-implement BulkImport from CSV

        * re-implemented bulk import as command 'bulkimport'
        * added new package 'activity' which will contain the action logic for
          such commands, to facilitate re-use
        * moved EvaluateIP into this package (not a command)
        * moved Import logic into this package (used by both BulkImport and
          Import commands)
        * re-implemented BulkImport using new Tasks interface
        * improved loggging in Tasks

    commit f90de53a9f2777dfd9decc0bd64532982175dea1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 6 11:44:52 2017 +0100

        Refactor EvaluateIP, use refactored helper classes

        * EvaluateIP is singleton object now, no need to create instances
        * apply method gets all required parameters as args

    commit 1b5977f60ee1a36ccf9f07b96b8b93d7b18cb22f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 6 11:43:59 2017 +0100

        Support ProcessIO in InterruptibleProcess

    commit 520441db241667c024bb3dd4dc76fd4f957448a3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 6 11:17:41 2017 +0100

        Remove unused code from UtilizationReport

    commit 4db52054a0aedbba57e865751b3001b9e071b79e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 6 11:17:08 2017 +0100

        Remove legacy code from PowerReport

    commit a54295fa09e26e24330651bc133d1ff77ee32d3f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 6 11:12:24 2017 +0100

        Add data path delay to TimingReport

        * extracting data path delay from timing reports
        * removed legacy code from TimingReport

    commit 0bf5257c11aede177522d9c8e442bf0d5acbb220
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 6 11:08:22 2017 +0100

        Move SequenceMatcher into separate class in util

    commit b2d484b860fb39f63a70849ef25d6f4cb50f6b4e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 6 09:38:29 2017 +0100

        Implement UtilizationReport for Vivado reports

    commit 3de7d1945f5422a7dae578e48203c7d753f0447c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 6 09:36:02 2017 +0100

        Move .zip file helpers into own class

    commit 2e799bb95bb6507694e460118ddf7f159428e68d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Mar 4 18:44:45 2017 +0100

        Fix missing directories bug in EvaluateIP

    commit 6c290fc38bb1d174e60f30f047f7db6e81ad480b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Mar 4 18:42:00 2017 +0100

        Re-implement AddCore and HLS commands

        * now based on uniform (implicit) Tasks scheduler
        * renamed AddCore to Import, matches BulkImport (from csv)
        * improved HLS result type to directly reflect the result values (no
          more Options)
        * fixed HLS task to use new Import companion
        * fixed InterruptibleProcess, now returns same value as `timeout`
          command on time out

    commit d786662c65d0a6dad2e94bc5185379e62029d2db
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Mar 4 18:31:19 2017 +0100

        Rename `Import` to `BulkImport`

    commit 44ae44917d42a30b80b4f3eb2a3be4c440180988
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 3 11:03:16 2017 +0100

        Fix hanging threads at exit

        * needed to interrupt blocking threads to exit cleanly
        * sys.exit is no longer required in normal case

    commit 357dd02556de788ba1bac836a45f6d5fc1c2c58d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 3 09:19:56 2017 +0100

        Re-implement HLS command

        * based on Tasks
        * unified HLS tool interface

    commit 3cbf1bc274d9e79628d26181ba8463b34c9e2764
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 3 06:58:58 2017 +0100

        Move `itpc.task` package to `task`

    commit 134d5fd0ffe5a6bce3168b04f397fe6151069210
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 3 04:12:58 2017 +0100

        Implement HLS in separate trait

        * similar approach to Composer
        * isolating the Vivado code in object

    commit fb1052f2d92ac69ef4f4abceff16607706a78beb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 3 02:47:07 2017 +0100

        Fix simple scalastyle warnings

    commit 0982628d034032bc38a8c783e1a4a03b4488326a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 2 20:09:04 2017 +0100

        FlexLM: suppress exception if no lmstat is found

    commit 58419e2e53d96851a8a823027359b541f32e9c59
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 2 20:07:33 2017 +0100

        Close iTPC swing application properly

        * sys.exit is not a good way to exit the application
        * fixed that by using quit instead of close on the main frame

    commit 8e4947dadf92adb9bfd48084ca390adaa9f24348
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 2 20:07:00 2017 +0100

        Move ComposerResult to Composer.Result

    commit 5631cff8a99d8ad6800c0c847db40c6cb4180f2a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 2 10:06:32 2017 +0100

        Implement unit tests for SynthesisReport

    commit f8adcc31ab53a3175a5a1cc9f55effb5892ed8ba
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 2 10:05:02 2017 +0100

        Unify SynthesisReport apply: should return Option

        * SynthesisReport would directly throw Exception, unlike the other
          reports
        * fixed that, fixed callsites appropriately, too

    commit 8c98b8ffa3a639b69ddc7c70c504e671451a5740
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 2 09:03:15 2017 +0100

        Implement unit tests suite for CoSimReport

    commit a6104f46a70adeff24ae6e75ff8fe1e7cbcec878
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 2 08:46:16 2017 +0100

        Implement PowerReport unit test suite

    commit f017722878cf2c0819d67b391187cbc040849146
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 2 08:45:56 2017 +0100

        Added invalid TimingReport test

    commit 69ced376a75c1590de2ba77b86eb51356aef4205
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 2 07:58:46 2017 +0100

        Move package 'itpc.slurm' to 'slurm'

    commit c14ba5c8a7ebfa412234c94f14f4c8f204a29cca
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 1 18:56:03 2017 +0100

        Remove legacy iTPC code

    commit f42b397a6b5880614670ff9531b11d29c63ebcf7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 1 18:53:15 2017 +0100

        Fix whitespace at end of line

    commit 250550d330f81b58797b9a45bbf7e6ad3a827045
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 1 18:40:54 2017 +0100

        Bugfix in ComposeTask

    commit 356339175f5d0828a5711087d2d8cae5385a0a54
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 1 18:40:19 2017 +0100

        Fix scalastyle warnings in reports package

    commit a47a7553cd69898d971d8c9f24baf0e08a121cf0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 1 18:24:57 2017 +0100

        Fix scalastyle warnings in util

    commit 7aaef74e1ac04e70ebed7070e279c4410c777b82
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 1 17:34:07 2017 +0100

        Refactor reports: introduce common base class

        * added base class Report with source file
        * fixed a few problems and stylistic problems

    commit c24c0ebcfa2a06cf108387c0e379270e5af00767
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 1 17:15:56 2017 +0100

        Move DesignSpace related classes into DesignSpace

        * DesignSpaceElement -> DesignSpace.Element
        * DesignSpaceDimensions -> DesignSpace.Dimensions

    commit 388cdb0edb4e42fc669f4f8e6e58b0d12c6dadfd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 1 17:15:30 2017 +0100

        Minor refactorings (fixed visibilities, final mods, ...)

    commit ca76cca6eca4e8e63479af0861804a32e5a5873a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 25 17:50:08 2017 +0100

        Remove Builders from base package

        * implemented Builds trait, which adds methods to read/write to/from
          Json trees and files directly, returning either Exceptions or
          instances
        * facilitated the elimination of tons of ugly code, e.g., all *Builders
        * all serializable entities (i.e., instances of `Description`) now have
          Json SerDes support in their companion objects (e.g., `Core.to`,
          `Core.from`, etc.)
        * stumbled across tons of other problems (more or less related) along
          the way, fixed everything in code I needed to touch anyway
        * removed all *Builder classes
        * added Json Reads/Writes/Formats for all entities in base/json
        * moved Tcl writer to base/tcl
        * removed FeatureReads, FeaturesWrites, clumsy BasePathReads/Writes
        * new Json format for features: "Feature" key identifies the actual base
          class, features are now stored in actual JsArrays
        * fixed all test cases and corresponding Json example files
        * removed deprecated and duplicated simulation arguments from Architecture
        * improved Benchmark tests: ScalaCheck universally quantified checks
        * improved Composition tests: ScalaCheck universally quantified checks

    commit cd8141e36abc91fd20f7f3955fa1c4129ac0479e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 25 17:38:59 2017 +0100

        Upgrade to Scala 2.12

        * also updated all libraries, except indirect dependencies which are old
          (e.g., guava 19 instead of 23)
        * fixed deprecation warnings
        * added new optimizer flags

    commit 0aa3a1c96630fc8ab9d25af24383914e3b62d7b1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 24 18:17:12 2017 +0100

        Refactor code base I

        * got fed up with horrible code base state, started refactoring that I
          kept pushing to later
        * moved all commands to new package 'commands'
        * renamed 'descriptions' package to 'base'
        * moved several common classes (e.g., Target) to 'base'
        * re-implemented Json support: each package has sub-package 'json'
        * 'json' sub-packages are package objects containing Reads/Writes/Formats
        * needed to touch almost every file in the code base to reflect the
          changes and import the correct classes
        * only step I, could not (yet) remove the 'Builder' classes

    commit ed1e4feb7716d88b7027843313265ac667688e5c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 24 12:59:04 2017 +0100

        SLURM: add cancel and cancelAll

        * SLURM jobs should be cancellable, implemented interface for `scancel`
        * also implemented cancelAll via `squeue -u $USER`

    commit 50cd8a1aef601a90d9a43979420e94352f3a913a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 16:15:12 2017 +0100

        ComposerLog: Add computation of ComposeResult value

        * centralized logic to scan Vivado log for errors and warnings and
          compute corresponding ComposeResult value for the Run
        * added apply method that parses string representation of ComposeResult

    commit 84f60027334842f06f2090b4d0f4778e0e9ffe84
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 16:14:31 2017 +0100

        Fix missing parameters in Writes[Configuration]

    commit 58ad9fe38010fafc28a2731b95a091c74bc6dbd9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 16:12:27 2017 +0100

        Fix problems with SLURM ComposeTask

        * fixed frequency setting (via TPC_FREQ in batch script)
        * using `logFile` parameter to generate clean log without ANSI colors
          for log tracking, SLURM redirected logs are kept just in case
        * works now in SLURM mode

    commit b57255d4c1c0c47af7d629624f497e6f0739b4d7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 16:10:56 2017 +0100

        Fix DSE directory structure

        * each Run outputs into its own directory now
        * fixes problems with conflicting file names

    commit 6b3337ce8dba44c4e2cdc3ce6630a7253332fa05
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 16:10:28 2017 +0100

        Fix bug when calling generate on a Run without result

    commit 8a49f0856947bd5cad2062f63ebd86675e1dc6c1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 16:09:48 2017 +0100

        Select exactly one Target for each ComposeTask

        * same problem as with HLS tasks, platforms and archs were not filtered

    commit 389766c13591ddcb555ee075b837676eac5b5c70
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 16:07:39 2017 +0100

        Launch each HLS task with exactly one Target

        * architectures and platforms were not filtered correctly
        * each HLS task would generate all Targets, instead of just one

    commit 6ac3be58d4cf239446049d9b5c0bc6e0f5de5342
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 16:03:46 2017 +0100

        Fix HLS task log output

        * SLURM redirects stdin/stderr, which include ANSI colors
        * difficult to read in log tracking
        * breaks log tracking mechanism (regex don't match)
        * fixed by using `logFile` parameter to generate log
        * SLURM log is only used as a fallback

    commit 672cae974dddf4811580c2bf0203f00fdfb1fd72
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 16:02:29 2017 +0100

        Fix memory requirements for ComposeTasks

        * SLURM registered more memory consumption than Xilinx estimated,
          causing it to kick jobs
        * increased memory requirements to more realistic values

    commit 99c17c849b53c6e853738031f4f3b97ca51d8382
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 15:59:52 2017 +0100

        EntityCache: fix clear()

        * clear should reset the cache, either using new paths or the original
          ones, if none are given
        * fixed, cache files list is repopulated correctly

    commit 86557c5c8f820094c775b3ebc7f5d60cc523f89f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 15:59:06 2017 +0100

        Add Fmax values in Core detail bar charts

    commit 23784568fd14ebd2581f7f3645cbb9e0b58dae49
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 15:56:58 2017 +0100

        CoreTable: Always ask for SLURM, if available on build bts

    commit afc45d417a0e352e98a1ce6574f2e0bb01001362
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 15:53:42 2017 +0100

        Remove Compositions cache from EntityManager

        * monitoring the compositions directory is not feasible, Vivado
          generates way to many files to walk efficiently
        * Composition files are not used as much any more, are not a full entity
        * removed from Entities.apply() for this same reason
        * removed the cache and monitoring of dir completely
        * only directory remains

    commit 75a7e7d3038070a28cb1ebf0346c70bbfac9fc62
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 15:47:56 2017 +0100

        Make ResourceConsumer SLURM-aware

        * `usesMoreThan` should not take CPUs and Memory into account, when
          SLURM is activated
        * local resources are irrelevant when running on cluster

    commit 7326e412905fafc02722b1adbe15294fad2b8fa2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 15:46:19 2017 +0100

        Make CoreTableModel react properly to Cleared events

        * if Caches are cleared, model must fire "structure changed"

    commit bf0a759a9592dd3e746de03a54339e0438759d36
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 15:41:16 2017 +0100

        LogTrackingPanel should stop tracking on hide

        * log tracking requires a lot of polling and should be stopped when the
          tracking panel is no longer visible
        * also fixed potential problems with the amount of trace outputs

    commit 543c2c1001090a3ff5ca6e458b7d1eb1ab50ec01
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 23 15:01:25 2017 +0100

        Deploy "fat" jar and execute directly

        * using sbt to launch TPC has the advantage of automatically building
          new changes; unfortunately, on clusters nodes tend to have a slight
          clock skew, which triggers sbt to rebuild .class files
        * changing .class files during runtime leads to NoClassDefFound
          exceptions, crashing TPC
        * instead deploying a "fat" jar with all dependencies, which is used
          in the bin/-scripts to run TPC/iTPC
        * fixed problem on HLR cluster, starts faster, too

    commit 971199a56a44d04c9cd5e834cbb0fd16c2bc1723
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 22 17:12:19 2017 +0100

        Implement SLURM support for compose and hls

        * HLS build buttons ask for SLURM mode (if available)
        * implemented super-primitive SLURM support in package `slurm`
        * new template for SLURM batch scripts
        * HLS seems to work, Compose does not work at the moment
        * removed batch size warnings, if SLURM is used
        * fixed bug in SlurmPanel, which would not register CheckBox changes

    commit b3507089cc3c4a3ccb049e533a233375325dc748
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 22 17:07:55 2017 +0100

        DesignSpaceExplorerModel: use absolute bd path

    commit b45ac9473b62f6ce3c392c0c7139aa65f124d8a3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 22 17:07:08 2017 +0100

        EntityManager: fix bug in TPC_HOME when not set

    commit d1f02a1e34996c9be4e5839d4ba575b51bb4fdb1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 22 17:06:12 2017 +0100

        Use new Logging handlers in Compose

    commit 5af0a748eec1b739cc3abd221c938ca6f09eced7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 22 17:04:55 2017 +0100

        Refactor Logging: use Exception Scala DSL

        * Scala provides an Exception DSL that covers typical cases (e.g.,
          returning Option/Either, default values)
        * added wrapper that use an implicit logger to log exceptions

    commit da99504565749e32197fb983eaad72a27de91462
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 21 13:46:58 2017 +0100

        Bugfix: Missing directories during HLS

    commit aae8c0b7c0d4beeade36a806f6f3e53d00bf1a45
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 21 11:36:40 2017 +0100

        Show warning when batch size exceeds physical processors

    commit 04b242ba3b2ca6c919a7d964e4c0dbab176a6ebf
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 21 11:34:06 2017 +0100

        SliderPanel: do not issue intermediary events during change

    commit 831a5509a1b712feec8f2da212ec77c6abc29003
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 21 11:33:16 2017 +0100

        Enable DSE at start if initial composition is valid

    commit 556a4e3a42c3731cf818bc3c7035886f80169b3a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 21 11:31:34 2017 +0100

        Set initial split in SelectionDetails to 0.5

    commit 890e8f9f6a0e16386bc75f819359fd232a7f6e1f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 21 11:31:11 2017 +0100

        Check for running tasks on exit

    commit fe3921ed5d954b08aa6f645c604ea43dc4b9d622
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 21 10:22:43 2017 +0100

        Implement global AppState model

        * models the internal state of the iTPC application
        * centralizes reactions of the UI, e.g., disabling of pages etc.
        * used in AppMenu to disable items in DSE mode

    commit 407a5c72007e3906023e0cce919a112c7e91a255
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 21 07:57:30 2017 +0100

        Improve Json SerDes code for Exploration.Event

    commit fe4d7fc53f6297f5a010d5bb9e574ca288ba4010
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Feb 19 07:14:52 2017 +0100

        Separate main menu from App

    commit 774e8a964c45ccbb68ab29ab033664b344e68f34
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 18 07:04:12 2017 +0100

        Use pretty-printed Json in Description output

    commit 19a6a36650e33ea5eac424c550a27524abbe5d23
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 17 19:22:27 2017 +0100

        Implement Json SerDes capable exploration log

        * implemented Format objects for all required types
        * reading from and writing to Json works
        * needed to add apply/unapply to AreaEstimate, ResourceEstimate
        * removed old ExplorationLogFile and replaced it with Json variant
        * works well, log is highly readable (both human and machine), but large

    commit 686a1b9ff70df0a7875510f5c84ade3a70dd5a00
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 17 13:47:47 2017 +0100

        Improve readability of Exploration log events

    commit babeecaf3bd8dff9ba61c9aab38f3b6ee67096da
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 17 11:41:56 2017 +0100

        Refactor code and work on minor UI bugs

        * refactored GraphStyle to reduce boilerplate code
        * also started to remove the DesignSpace... prefixes; is apparent from
          package name
        * changed layout of log table and main graph
        * fixed most UI issues with DSE graph:
            - column width of timestamp in ExplorationLogTable
            - width of SatelliteGraphPanel
            - fixed Centering rescale code (now works (tm)!)
            - fixed scalePoint in SatelliteGraph
            - fixed window resizing issues
        * re-added all edges in graph model; renderer selects which to render
        * added SplitPanes to DSE configuration panels
        * fixed redrawing of DSE configuration panels

    commit 6615891e2082e9f87b32996ef279e0e34786f2cd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 17 11:40:46 2017 +0100

        Prevent node locations from changing in Layout

    commit 9392df4768c50d641cea437f9d0c3bc86bb4f9c5
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 21:43:25 2017 +0100

        Use picked state in main DSE graph

        * picked vertices will show additional edges, such as GeneratedBy and
          PrunedBy
        * otherwise, edges will not be rendered at all
        * very helpful; facilitates browsing of the result, e.g., finding out
          why a Run has been pruned

    commit f0565f643124dbcfcc7fdeb56b5295e48a94dfec
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 21:42:53 2017 +0100

        Support label renderers in GraphStyles

    commit 212d1705c4e9679c9bf5f97b3d7df832171171fe
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 21:41:05 2017 +0100

        Implement a focus-on method for exploration events

        * main graph should enable to focus on set on nodes
        * focus() method does that, recenters on center of nodes
        * panel now listens to log table, focus is triggered on row select

    commit aca1b88539787f8d14a0351871c1da20951e7616
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 21:39:22 2017 +0100

        Add row selection event to ExplorationLogTable

        * added an EventSelection object, which publishes selection events
        * can be used by other classes to register interest

    commit c0e25098b535f4115ef6f9032df3596de6333d1f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 21:36:56 2017 +0100

        Change RunPruned: should contain a set

        * every prune generated a single event, should be reduced
        * instead, a RunPrune event will be generated once per cause and reason
        * much better in the log, and makes it easier to grasp the pruned sets

    commit fff2360403bcb346a38ab3369d96b4101632883b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 15:11:04 2017 +0100

        Finish refactoring of Graph appearance to Styles

        * DesignSpaceGraphMainStyle now contains all drawing related code for
          the main DS graph
        * DesignSpaceGraphSatelliteStyle contains the style for the satellite
          panel, which is smaller and simpler
        * removed all drawing and styling code from the panels
        * added Style applications instead

    commit 9917cd6960acd8f9e72718ec35dd17fdf94588ca
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 15:07:43 2017 +0100

        Make HeatMap colors half translucent

    commit 60864c3ccdfd4ffd8caeacdcbb133bd00d39e091
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 15:07:14 2017 +0100

        Track H-value range in DesignSpaceGraph

    commit 7bd381e914fa30f9767d64c439a8db5237461cbe
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 08:07:27 2017 +0100

        Refactor DSE graph panels

        * lots of shared code in both views should be extracted
        * moved code for centering and scaling into Centering trait
        * started to implement GraphStyles to configure VisualizationViewer
          appearances (i.e., Vertex styles etc)
        * implemented HiddenEdgeStyle to suppress edge rendering
        * not finished, not reintegrated yet

    commit 96c2d895743f3fc2ea7ed8de5b575cfd69dbcd9c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 08:03:49 2017 +0100

        Add keyboard mnemonics to tabs

    commit e9c387bb9e086a383c937de3d05084295320b1e2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 08:02:52 2017 +0100

        Debug: increase ComposeTask runtime, success chance

    commit 548d422288cfc294414564255c83c013afe1f67a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 08:02:17 2017 +0100

        Remove InBatch edges, only show edges of last Batch

    commit fd62beeb6ef58cf49577a0f633791303760186ba
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 15 08:01:35 2017 +0100

        Add HeatMap color scheme

    commit b12ec0242ce04bad26d5264939814be3833749d0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 14 11:39:45 2017 +0100

        Fix bug in DSE: not reporting successful elements

        * if successful element was not first in batch, it would not be reported
        * fixed that, if after pruning DS is empty it will be reported

    commit 50eaa5e8d6701fcb61d83de7d3e9cfdb6d173ad1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Feb 12 18:24:07 2017 +0100

        Work on DSE satellite view

        * does not work properly, translations/scaling of original view seem to
          upset the state of the satellite (sigh)
        * need to figure out what's wrong; also no nodes are shown

    commit 167554b8335f665171070c6cb31fecf230bce36e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Feb 12 17:26:37 2017 +0100

        Implement auto-scroll for ExplorationLog

        * Exploration log should automatically scroll down to latest event
        * replaced inefficient hack of replacing the entire table with proper
          table model (much better performance)
        * ideal date format is unclear, keeping full timestamp for now (minor
          performance impact due to format in rendering of table)

    commit 15a06c08a486cab389ea82f2d67d5efd10b1ba0a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Feb 12 16:52:17 2017 +0100

        DSE graph: center grid and scale to fit

        * was more difficult than it should have been, my brain is not working
          correctly
        * fixed the broken recentering, then fixed the scaling
        * there are still rounding errors in the scaling, but it's ok now

    commit a732b3b97fb87e7f4fe205ee58be43ab85db3a89
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Feb 12 13:23:15 2017 +0100

        Improve DSE graph: draw grid, re-organize

    commit ff77c21c3805654d4a9f169d59a2b0922ed5eae6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 11 08:52:32 2017 +0100

        Use SplitPanes to improve UI

        * using SplitPane in SelectionDetailPanel, thus applying to all tabs
        * using SplitPane in Core details to improve chart visibility
        * user can define split between properties tables and charts

    commit 344615538565537c64c9d544928e1f36ae8be65e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 11 08:34:39 2017 +0100

        Remove unused SetSelectionPanel

    commit 47380e9615294111c15a00dffa8049c9037bac9b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 11 08:26:52 2017 +0100

        Do not show "Build" buttons while HLS in flight

        * added state to CoreTableModel: can track running HLS tasks
        * shows "HLS still running" instead of build button while at least one
          HLS task for the Kernel is still running

    commit 25b2fdf87196aa537845611f67f35f8c17a2eff2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 10 19:10:37 2017 +0100

        Update CoreTableModel on changes to reports

        * can affect summaries etc.

    commit cbc7aeded5fbf006d8715ebd8be31621585cec56
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 10 19:08:08 2017 +0100

        Fix bug in EntityCache

        * EntityCache often receives MODIFIED messages with no prior CREATEs
        * such files were never added to the set, thus missing from cache
        * also added double-check to scan paths after directory was created,
          in order to find missing items in case events were lost between
          filesystem actions and watching the new directory
        * need to check if this is really necessary (don't think so)

    commit 21b66deef7e305e0f1b28495fac30068d2aaf016
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 10 19:05:34 2017 +0100

        Implement debugging tool: complete state dumps

        * added menu item to dump complete application state
        * includes internal state of caches etc.
        * will make it easier to hunt down caching bugs
        * subject to changes

    commit bb37b5a4a026b3001aaae4fe86719ddfc07aa079
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 10 17:01:22 2017 +0100

        UI updates onEDT, minor UI fixes

    commit 78a4f41c0fb0cffef17a2951d14781c34c7fb5c8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 10 16:58:02 2017 +0100

        Re-implement Platforms and Architectures tables

        * using same approach as for Cores: auto-updating Model

    commit ec2f19a154fbd6d0582a80c620dd417b3fa384dd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 10 16:55:25 2017 +0100

        Replace mkdirs by Files.createDirectories

    commit 5ee1db1f70fa659da218e9241d428dc2c6d598b9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 10 16:35:59 2017 +0100

        Fix bug in DirectoryWatcher missing create dirs

        * need to walk newly created directories and recursively add subdirs to
          avoid missing new dir creations
        * can be simulated using 'mkdir -p a/b/c/d/e' on console:
          DirectoryWatcher would pick up only a, missing the others
        * fixed that by generalizing start(): new directories are walked
        * might still result in some missing directories; crappy API crap

    commit 0da0532e3690f3044c183bd3168ea5e2fb71b7e4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 10 16:33:50 2017 +0100

        Replace uses of File.mkdirs with Files.createDirectories

        * apparently, the Watch Service has problems with mkdirs

    commit d97f9f32fc65fe0cafe2c7b057aa555fb9410974
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 10 10:48:30 2017 +0100

        Rewrite DirectoriesPanel to react on EntityManager

        * did not react on EntityManager changes until now
        * fixed that and generalized the path editor, leading to simpler code

    commit bd22b1ec31285b09175295a3203e431fa7c0d4d4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 9 19:59:37 2017 +0100

        Implement load/save support for Configurations

        * turned out to be a major pita: required support in most tabs to
          support non-UI driven updates (so far all updates to the model
          originated from the UI)
        * had to rewrite the SetSelectionPanel to properly include the state
        * had to define a 'load' method on the ConfigurationModel which raises
          events to trigger redraws, updates, etc.
        * also rewrote the entire CoreTable: new CoreTableModel updates itself
          properly and removes the need for the hack of constructing new tables
          on the fly
        * each CoreTable now has only a fixed model, which keeps itself updated
        * much better performance; also works nicely with EntityManager updates
          (e.g., on new descriptions)
        * fixed several minor bugs all over the place
        * added some inline docs

    commit 438181e539b808dd8e391acb8a5ab9009ffc6fa9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 9 19:58:59 2017 +0100

        Worked on DSE graph, reducing performance impact

    commit a4171cb0758506198bfe1fee1d1285e90af9f22a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 9 19:53:22 2017 +0100

        DSE: fake mode for ComposeTask with different results

        * ComposeTask returns randomized results, including timing failures,
          placer errors and success
        * will be helpful to debug DSE graph

    commit 6570f343d699ad3e418c4cb59c0e7c540630a4fe
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 9 19:45:23 2017 +0100

        Demote DirectoryWatcher warnings about inaccessible dirs

        * happens quite frequently and is nothing to worry about
        * new level: DEBUG

    commit 243da3779f0628ad54abd1643691344916353aea
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 9 19:43:30 2017 +0100

        Enable JSON dumping of Configuration instances

        * implemented missing JSON Writes for Composition
        * implemented JSON Writes for Configuration

    commit a5a0d44ed9f715491a2212b2f0dd97b281fc88d5
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 9 19:41:46 2017 +0100

        Implement pretty printing for Core Descriptions

    commit 4687237b59d85ca7ae8f1619ebedcbcfa6736bfe
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 9 19:41:00 2017 +0100

        Fix bug in CompositionBuilder: allow empty Compositions

    commit 0a274b7298da402e7a14f2474c89b8fd3d2bc044
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 9 19:39:43 2017 +0100

        Fix missing output in HLS tasks

        * need at least INFO level output in main package
        * reduced outputs for caches and EntityManager

    commit 16868e7901c39410f34de87a1939bcad6f2cf367
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 8 15:21:44 2017 +0100

        Order targets by name in all panels

    commit b71942cf9f919efe1397e05450fab4b824901772
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 8 15:20:03 2017 +0100

        Try to fix the drawing errors in DSE graph

        * synchronized update methods (should not have any impact, but does not
          hurt either)
        * removed layout.reset() calls; positioning of nodes seems fine now

    commit ee8fdf8aae54381238ad1f4288f92a7194410f44
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 8 15:17:18 2017 +0100

        DSE exploration: fix bug in generate

        * no feedback elements were ever added due to a bug in the generate
          method's code to check the result value
        * also, new elements were always computed first, then discarded if not a
          TimingFailure result
        * rewrote the code to fix the bug and checking for result first

    commit e6c5512122533ba9bb9e39e4d3843df1c834e643
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 8 13:58:02 2017 +0100

        Add slider for fixed frequency mode

        * until now, env var TPC_FREQ determined frequency used in DSE when
          frequency variation was disabled
        * replaced TPC_FREQ by explicit parameter and value in DSE model
        * added a slider panel which facilitates frequency selection when
          frequency variation is disabled
        * needed to change several places to use explicit value

    commit e7f6f6843cb21961c8f93953af21e155cbaf57e8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 8 08:09:20 2017 +0100

        Remove old internal composition in CoreTablePanel

    commit f45c8f6018400a4c543e799c3c840ec04f973e28
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 8 08:08:03 2017 +0100

        Fix bug in CompositionSummariesPanel on empty compositions

        * CompositionSummariesPanel did not check whether Composition is empty,
          resulting in an exception for empty.max

    commit 00f2f6e2b6708474151386bab2def102ff8c8228
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 8 08:06:58 2017 +0100

        Fix addition bug in CompositionModel

        * when setting the count for an existing kernel, replace old value
          instead of summing the values

    commit d22bf56ed1b92bb8a78e19d8c87fb8435500c3a2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 7 17:46:26 2017 +0100

        Rewrite ConfigurationModel

        * ConfigurationModel is replaced by UserConfigurationModel
        * old code was very bloated and fragile
        * new code relies EntityManager and benefits from automatic memoization
        * significant improvement in performance
        * needed to adapt most UI classes to reference new config model
        * simpler event hierarchy for changes to configuration: only raises
          two events for change in targets and change in the composition
        * added better formatting for DSE log messages
        * DSE compositionDir is relocated to its DSE... directory, keeping all
          files related to a DSE run in one place
        * fixed bug in DSE dir name: invalid characters
        * added new CompositionModel to manipulate the Composition
        * both CompositionModel and UserConfigurationModel can be implicitly
          converted to their outer kinds (Composition, Configuration), can be
          used in place of the outer kinds
        * added inline documentation all over the place (but still not complete)
        * default batch size: number of processors

    commit fa24f4de8a26b655bb74b98b4257593862209859
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 7 17:43:24 2017 +0100

        VivadoComposer: write new global tpc_jobs

        * is set to same value as maxThreads

    commit 12f7c722e398df5e20f838017540abfed747bf38
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 7 17:42:35 2017 +0100

        TPC main: add stack trace for exceptions

    commit d42f6c701ab42502fb7c678ecd6960c7ffdaad32
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 7 16:03:51 2017 +0100

        common.tcl: add override for get_number_of_processors

        * get_number_of_processors queries /proc/cpuinfo, if possible
        * for batch execution on a SLURM cluster, this must be overriden
        * introduced global variable tpc_jobs: if it is set, its value
          is used instead, otherwise /proc/cpuinfo will be queried

    commit a1ab15343c1665f42eee1c88d2051436caf1e7af
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 6 17:53:58 2017 +0100

        Fix bug in DirectoryWatcher

        * must not try to walk non-existent paths

    commit 2a9894179d7d6e17601a96c8b72c4c8d319f629f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 6 17:48:05 2017 +0100

        Move outputDir facilities to EntityManager

    commit 6bfbb6207d0a34263fe807a87f64ea37687add5b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 6 15:19:03 2017 +0100

        CorePanel: use EntityManager

        * modified CoreTablePanel and CorePanel to listen to EntityManager
          events of all kinds
        * will react on any base path change, or entity change

    commit 53f73bb6edb8bb78c5debaf11162b6f9130e493e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 6 14:56:47 2017 +0100

        ArchitecturesPanel: use EntityManager

        * ArchitecturesPanel now listens to EntityManager and live updates the
          Architectures in the selection list

    commit b413c790b664f6ac34d7555f37d97e05101644b3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 6 14:43:38 2017 +0100

        PlatformsPanel: use EntityManager

        * PlatformsPanel now listens to EntityManager and live updates the
          Platforms in the selection list

    commit f96360dd7a400ba7cf0db4e990254e4c12b5742e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 6 14:41:35 2017 +0100

        SetSelectionPanel: add custom formatting

        * data in the set can be formatted by overriding "format"
        * also fixed bug in computing best width for empty tables

    commit 1bee6b97d26f34e0feadf72ff0ec58ea0468c499
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 6 13:46:39 2017 +0100

        Replace DirectoriesSelection with EntityManager

        * EntityManager can take over the base path mgmt
        * Entity will take over the Directory enum
        * replaced all instances in several files

    commit e370542cb3240590b0a44d792be4eb1209dfcf1a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Feb 5 13:24:39 2017 +0100

        Improve ScalaDoc

        * worked mostly in itpc/common
        * some work done in itpc/task
        * some work done in itpc/model

    commit 439ce071785dc42713d4542b0e7384a853af72cd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 4 15:09:53 2017 +0100

        EntityManager: Implement events

        * EntityManager should propagate the change events from its caches to
          listeners, which need to update their own state
        * e.g., the GUI may need to update a list of Platforms
        * to this end, the EntityManager listens to EntityCache events and adds
          Entity type information to its own published events
        * Bugfix: filtering of DirectoryWatcher events was broken in EntityCache

    commit 9e1d030a8fc65e7a385cd10cd4a0bbd1603e4009
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 4 11:18:27 2017 +0100

        Add support for Core reports

        * renamed DescriptionManager to EntityManager
        * renamed DescriptionCache to EntityCache
        * added support for reports in EntityManager
        * reports can be queried individually and in bulk

    commit cfca532167bd82f32217ac10b7db076d8a86a20e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 4 08:11:16 2017 +0100

        Add TODOs for reports in DescriptionManager

    commit d607693af45cd9e1383929e0a1a9480a95c4b43b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 4 08:07:43 2017 +0100

        Implement central DescriptionManager

        * singleton to manage dynamically defined Descriptions
        * holds DescriptionCaches for each type of Description in TPC
        * manages base paths for descriptions, propagates changes to
          DescriptionCaches
        * directories are monitored automatically, providing consistent caching
          for both the definition files and their instances
        * will use this as the central place to query Descriptions: need to
          refactor existing code to use it accordingly

    commit 0f99f3651f5d2bcabb6b244ccc29f0fd4ddd469e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 4 08:06:51 2017 +0100

        Remove explicit DirectoryWatcher ref in DescriptionCache

    commit dbb74a67b9ceebbd7692850df1f2d51cb5562a95
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Feb 4 08:05:59 2017 +0100

        Change color of different log appenders to distinguish their outputs

    commit 2830f129135237315909e6a2f4f76a6dc8b569cd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 2 16:39:44 2017 +0100

        Build generic DescriptionCache with DirectoryWatcher

        * tracking the current state of the description files is still a
          nuisance, a lot of code duplication and manual invalidation
        * DirectoryWatcher can be used to improve upon this situation:
          Description directories can be monitored directly and updates to
          both the description file list and the cached descriptions can
          be updated correctly and automatically
        * DescriptionCache does exactly that: It listens to a
          DirectoryWatcher and updates a list of file matching a regular
          expression
        * apply method can be used to construct the Description from a
          Path, this build function will be memoized using Memoization
        * cached Descriptions are invalidated automatically on file
          modifications and/or deletions

    commit c0d06c3b91ef366d3ff2888ffb681dd699aa8e88
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 2 16:36:38 2017 +0100

        Implement generic directory monitor

        * DirectoryWatcher uses JDK7+ WatchService to monitor directories
        * recursively monitors all subdirectories
        * translates WatchService events into own hierarchy as Publisher
        * provides file events with full paths
        * must be started and stopped manually

    commit 06ea36d88c6c88ceca9a60e8f209efe7965ce0ab
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 22:02:15 2017 +0100

        Make DSE log panel resizable

        * split pane for graph / log
        * currently missing: cancel button

    commit ac930625002fce4a3d7bc38f5de7cecf703f86ac
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 22:00:09 2017 +0100

        Move all DSE logs into separate dir per exploration

        * using timestamped directory
        * added base path into Exploration

    commit 5a50fb9cd78d0b1d266ba88560cafc6fdc49b37a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 21:06:41 2017 +0100

        Remove old listener code from ExplorationTask

    commit 78261954015fc182a49ab1b9e4f721a2192d3164
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 21:03:38 2017 +0100

        DSE: add separate logfile containing only DSE events

        * ExplorationLogFile class writes events to file
        * DesignSpaceExplorationTask creates instances, but no proper names for
          the files yet

    commit 80bc049025702c6783fcd10c389f1b9b3d919465
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 20:37:22 2017 +0100

        Use Memoization in ConfigurationModel

        * rebuilt Memoization (badly) in ConfigurationModel
        * fixed that, using Memoization class for cleaner, better code
        * added clear() method to Memoization for resets

    commit 506b7b179ca1972ccb891b415db90b7b77703f6c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 20:21:44 2017 +0100

        Bugfix race condition in Memoization

        * forgot proper synchronization in Memoization: WeakHashMap is not safe
          to read concurrently (bummer!)
        * fixed insertion code; there was a race condition between contains
          check and get call, fixed by directly using getOrElse

    commit 41d166c1df1ee7ad4e0ff42f53b5f35d522bee6d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 19:54:13 2017 +0100

        Exploration: Provide more verbose error on duplicates

    commit 716d7e516336fb126fb993418f384c941f1c5b06
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 19:51:33 2017 +0100

        DSE graph: Fix exception when tooltips are shown

    commit 4104286ad02597e97552cf06b3df7c8bba3b3eda
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 19:49:43 2017 +0100

        Fix duplicate compositions bug in DesignSpace

        * in some cases, feasible compositions would be generated twice
        * rewrote code, much simpler and correct now

    commit 6d337ddee3207df766a888be9716a57bcb341a1a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 19:49:16 2017 +0100

        Implement proper toString for DesignSpaceElements

    commit daa15a657f9ac9816c96c6590779c152a4bc0dfd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 19:46:50 2017 +0100

        Improve performance by CoSimReport memoization

        * added memoization for the CoSimReport find method
        * works exactly like for SynthesisReports, huge performance improvement
          in itpc/dse

    commit 681a72d4ea9399f02fcf53237f3e33f99ce3a929
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 19:44:52 2017 +0100

        Bugfix CoSimReport parsing

        * Vivado 2016.3 and newer sometimes use 'x' in the co-simulation reports
          to indicate that no value can be given in certain columns, e.g.,
          average latency when only one execution was done
        * this lead to the whole report not being parsed
        * fixed that, returning 1 cycle latencies instead

    commit dd7e8c82ca5508141684379b04bccbad6e9c9865
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 19:43:16 2017 +0100

        Fix bug in SynthesisReport memoization

        * fixed synchronization

    commit 333a41559b3b56f32625d147858bcc6c1fd41c97
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 19:40:41 2017 +0100

        Improve toString performance

        * AreaEstimate and all descriptions are frequently converted to string
          representations in itpc
        * computing toString as a lazy value improves performance significantly
          with only small memory penalty

    commit 241f2a28b1df4535fd14cec843f0a1c8f4ff13a3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 12:24:17 2017 +0100

        Add support for 2016.3, fix dual DMA

    commit da1ad919240b2a6c68d207eb77d8416c3a8e15aa
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 12:19:41 2017 +0100

        Add support for 2016.4, fix Dual DMA

    commit bb9a17594d4744c306bc5ba5f036fbefbfbc13d9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 12:17:27 2017 +0100

        Remove broken kernel 'sobel'

    commit 0bb157c88818f29c65869a3096fa03dcc20170a7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 12:17:03 2017 +0100

        Remove broken kernel 'map_angle'

    commit b5a512b8243c847e35b3f1444dc7a6e196fe6866
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 12:16:34 2017 +0100

        Remove broken kernel 'inout1'

    commit a55d0fc0c94e0de826859462e18e352fc92bd908
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 12:16:03 2017 +0100

        Ignore .log files

    commit d5a1a1f981941cfa593f34d24e389a3074bb7cc1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 12:14:15 2017 +0100

        Zynq: use default synth and implementation flows

    commit e0c3e94c1f571b81f1f0aa8869e79d8fefed11fb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 12:13:38 2017 +0100

        VC709: use default synthesis flow

    commit a3da23fba85a552154062f5770700380fe20ef5f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 1 12:12:13 2017 +0100

        Fix synchronization of Configuration memoization

    commit ef0966104fe3cffd81f913e3da9b50c1edc58e51
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 31 18:40:57 2017 +0100

        Fix number of threads in ComposeTask

        * Vivado must not use multiple cores in DSE mode, uncontrollable
        * fixed number of threads to 1

    commit 1eb9deff65b9481ca7b7abb6e1a1384b8ffe9de9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 31 18:40:15 2017 +0100

        ConfigurationModel: fix overeager synchronization

    commit b8caae8cc13002c243678a7e875e718ca5c61333
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 31 17:41:32 2017 +0100

        Bugfix: log tracking panel does not work for completed tasks

        * log tracking would not work properly for already completed tasks:
          after receiving the first lines, tracking would stop and skip
          additional logs referenced in the first
        * log tracking stays on now, also for completed tasks
        * need to check performance

    commit c8a74ebc4bfe9e01c8a77de3ba572cabd73bd220
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 31 17:39:45 2017 +0100

        Fix resource requirements for HLS task

        * HLS task performs evaluation and thus needs both Synthesis and
          Implementation licences
        * possibly a device licence might also be required, unclear; in our case
          we always have the same number of licences for parts as for Vivado
          itself

    commit e6424a73f6452b1d5fa001b3856b43e0962ef9a0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 31 17:38:27 2017 +0100

        Bugfix: cores do not appear in list after HLS task

        * caused by memoization of configuration and findCore in Common
        * added resets to recompute lists once

    commit 1a0cca4ccdb525118eeb1c47d6f0857fb38d1ba2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 31 17:35:40 2017 +0100

        VivadoHighLevelSynthesis: run AddCore in same thread

    commit a7bbf83c54c63e666797c67e8fa213e2de5c67dd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 31 17:34:24 2017 +0100

        Memoization: move to util and add remove method

    commit 50f0e4c19864dffb639c8df2ad96a902b21a26ea
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 31 15:36:47 2017 +0100

        Implement resource monitoring for task scheduler

        * added new package: 'util' - moved MemInfo there
        * implemented FlexLicenceManagerStatus class to query FlexLM licences
          via lmstat; this can be used to schedule tasks according to the
          remaining licences (lmstat must be in PATH, or infinite lics assumed)
        * implemented ResourceMonitor: manages ResourceConsumers, which require
          CPUs, Memory and Licences for their task; monitor supervises the
          launching of new tasks according to the current resource situation
        * all Task implementation now have resource profile; added information
          from Xilinx regarding memory requirements for Vivado
        * Tasks now uses ResourceMonitor to schedule task execution (not fair at
          the moment, tasks with high resource requirements might starve)
        * Status panel now shows output of ResourceMonitor, too

    commit e63c1d731d3826236fe5dc6b515d0a24ac8ce07a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 27 16:37:39 2017 +0100

        Bugfix: Manual address map for Zynq

    commit 50792b1387f78fc2f6002facdfdcce46a225c675
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Sat Jan 21 08:46:10 2017 +0100

        Squashed commit of the following:

        commit 4cc7dc22af4863a784ff2db0a461c489f94e3514
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Fri Jan 20 10:03:05 2017 +0100

            Fix number of parallel threads for HLS

    commit 83a7af9722e057374c6903bfa47551ec3a9e481f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 14 22:09:09 2016 +0100

        Bugfix: add dependency to fix Nullable stub warning

    commit 1ce0beb87634a759c674d251565ccb5cf74bd592
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 14 22:06:55 2016 +0100

        Worked on JUNG graph visualization

        * much more color-coded details now, e.g., edges
        * readability is still so-so, need to improve looks
        * added ColorSchemes as distinct class (will re-use)

    commit 18d2da2d29ce043f1fcbc57303d8ac6874360eff
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 14 22:06:20 2016 +0100

        DesignSpaceExplorationTask: carefully control instantiation

    commit 0f6f9666614042d989b735c070d8e55ad8dffdfa
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 14 22:05:39 2016 +0100

        DEBUG: ComposeTask directly generates PlacerErrors

    commit 7ae0b50340e51cf2b720feda5745ca300d3ed37d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 14 22:03:10 2016 +0100

        Implement edge events in graph model

        * DesignSpaceGraph now adds edges for pruned, generated, and in batch
          events to visualize DSE progress
        * rewrote Nodes to be DesignSpaceElements (no further indirection)
        * besides fixing and edge-related bug, this makes the access to the
          vertices much easier and more direct
        * also avoids double vertices collections

    commit 4aeb935b0617325f8a509356da0101c00e92b517
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 14 22:02:17 2016 +0100

        Bugfix: Do not start exploration with two instances

    commit a0b7e05cb4055db155498ec1d330df0dc9d7addb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 14 22:01:18 2016 +0100

        Re-implement generation and pruning in Exploration

    commit 6db84be78d5e8c41ef52a116be6f2bf8aa57917f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 14 22:00:40 2016 +0100

        Make signal in Startable optional

    commit 7f286988b977d49ca9025be3fb01b6a8eca5f0fc
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 14 21:59:23 2016 +0100

        Make AreaUtilization accesses thread-safe

    commit 3e02244af1ddcda3b700e39f059fbb4d95ee70d3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 14 21:58:51 2016 +0100

        Define ordering on AreaEstimates

    commit 6f066449f036fb5b577052372bf2986d736238de
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Dec 11 14:09:34 2016 +0100

        Move design space enumeration out of constructor

    commit 359f2557913fcd4bfa8d8824c9e81b55a48c4084
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 8 19:45:20 2016 +0100

        Work on DSE panel and implementation

        * previous implementation of basic DSE algorithm was based directly on
          Futures and thus unsufficient for SLURM cluster mode
        * re-implemented a simpler version in itpc/dse:
          the Exploration object can be created via its companion and controls
          the DSE execution; it spawns Batches of Runs, each Run corresponds to
          a ComposeTask
        * feedback stage not yet re-implemented
        * much more flexible: a ComposeTask can basically run anywhere and can
          easily be re-implemented for SLURM batch mode
        * also cleaner implementation of the algorithm itself
        * Exploration publishes several events during its execution
        * added Graph panel via JUNG2 (not working yet)
        * added new layout of design panel for running DSE
        * implemented basic Memoization to speed up DS enumeration
        * tons of changes regarding DSE model

    commit f917a0dbcc02140a592a020e8508c684f961443f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 6 16:19:09 2016 +0100

        Fix missing 'core' package

        * accidentally got ignored in .gitignore file
        * re-added for implementation of the Core panel

    commit 2592292df8aa7d3aa8c9aaed8b1023c069c2c78d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 2 19:23:15 2016 +0100

        Structure itpc package into submodules

        * directory structure elevated to package structure
        * visiblities not yet fixed
        * moved multi-file pages into separate dirs: core, dse
        * requires a few more imports, but looks cleaner

    commit 237acae74cfd17cd29a001cef8cd37590c751f67
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 2 18:10:43 2016 +0100

        Implement DSE panel

        * implemented according to my draft note from 28.11.
        * had to modify DSE classes Alternatives and DesignSpace
        * problem: findCoreDesc will launch HLS, needs fixing
        * rough sketch, but so far works pretty nicely
        * only GUI mechanics, DSE task itself is not implemented yet
        * no detail panel at the bottom yet, should show progress information
          while running
        * consider switching the entire panel when running instead of
          deactivating all the subpanels

    commit 8827727dfa10a033f0bd6fe18cb409f9dba13520
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 2 18:08:28 2016 +0100

        Provide means to change borders in SelectionDetailPanel

        * each container now has a corresponding val that can be overriden to
          change the appearance of the instance

    commit d83b89fd3bbb642a108dd8b1d2dc1c05caa93e83
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 2 18:07:24 2016 +0100

        Disable column reordering in most tables

        * added NonEditable object to easily change Tables to non-editable
        * fixed column reordering in most tables

    commit fa92d7fb334cf50deb2e2253c96e71c5be20e34a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 2 09:51:55 2016 +0100

        Use command line parameters for initial configuration

    commit 4403d1c4804e41aaa198b8bab1c409fa46fc7a3d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 2 09:46:19 2016 +0100

        Fix broken 'rot13' HLS kernel

    commit 9c714f39a28b6152bebd3100f871168c6600657b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 2 09:45:15 2016 +0100

        Remove splashscreen from command line tpc

    commit a14912baf783869eb11e9eebfda53fe6dade5600
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 25 19:44:58 2016 +0100

        Add splash screen during load

    commit b8c17cea3082792813b68bdf8a405af035227f5f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 25 19:43:17 2016 +0100

        Start work on DSE panel

        * not much done yet; model representation started with some events
        * Composition and DSE panels are deactivated at start, only enabled when
          a composition is set in the config
        * started to generate the design spaces (needs more work, too slow)

    commit db8635e57312db092642de1b21c7a15dfc299b49
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 25 19:38:36 2016 +0100

        Change tab colors for Tasks and focused

    commit c4abbd752cbe03015747d776b6e258a8680ccb4f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 22 09:42:37 2016 +0100

        Rework the model

        * needed to split the MVC model, since too many different concerns
          were concentrated there
        * Model is the new top-level class, refactored most panels
        * contains an instance of the ConfigurationModel (just refactored)
        * user detail selection is split off: detail selection events are
          passive UI events and are located in Model.detail, with its own
          event publisher
        * moved directories selection into separate class with more
          detailed change events (for the specialized listeners)
        * Model.config should be split even more into user choices (which
          affect the TPC configuration) and the configuration itself
        * change in Tasks model: the global task queue is no longer a
          singleton in the companion object; instead, each Model contains
          a Tasks object in Model.tasks
        * this reduces implicit coupling and increases the reusability of
          the Tasks queue set itself

    commit e0ffe760a77ffb17a824b5b7546bce77da966f97
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 22 07:22:02 2016 +0100

        Move Task events into Events object

    commit da4ac75cefcd75ed7a83516cd874e1ecf0679110
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 18 16:33:55 2016 +0100

        Fix update problems in Cores panel

    commit 1714b48126a669aa675496f2edad10981610cbdf
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 18 16:30:59 2016 +0100

        Fix 2.11 warnings and errors

    commit 240fef0990a883657a5e1f05a29f0788bc662984
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 18 16:27:47 2016 +0100

        Upgrade to Scala 2.11.8

    commit 7ca0e1aaf3b1078bf0eb4cfb59a9548a595ff655
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 10 19:21:10 2016 +0100

        Implement IP-XACT .zip import

        * added button in cores panel (want to keep workflow left-to-right in
          tabs, decided against file menu)
        * generalized log tracking: LogFileTracker object prepares
          thread-specific file appenders, LogTrackingPanel displays and chases
          logs, LogTracking task identifies log tracking objects and gives
          access to the logfiles they'd like to track
        * changed default log level on console to INFO
        * stopped removing Vivado runs that failed with OtherError
        * had to make inner generation method AddCore.addCore public to
          implement the import task in the same thread

    commit 055e79fe524651daff0a29715fadc1d9ddd07fb6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 10 13:03:12 2016 +0100

        Support for Vivado 2016.3

        * dual_dma upgraded to 2016.3 Xilinx IP
        * fixed error in config for dual_dma (all versions), fixed display names
        * PCIe bridge is missing axi_ctl_clk, adapted platform Tcl

    commit aafb3dcf54411d3512afbd048e8b176554ee897a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 8 10:14:20 2016 +0100

        Add pie charts for area usage in composition

        * extra tab "Composition" shows pie chart with utilization data for
          Target, depicting each PE kind separately
        * bugfix: platform/arch selection did not affect overviews in "Cores"
        * moved composition overview classes to selection subdir

    commit c73de6f083794f232fa11cd8c3503bda6458f1f0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 7 18:21:40 2016 +0100

        Implemented composition overview panels

        * composition counts can only be changed _after_ all cores have been
          synthesized and the reports are available
        * when counts are > 0 utilization, max. frequency and feasibility
          are computed for each architecture and platform
        * two bugfixes in core selection, details should update correctly
        * using memoized configuration everywhere, good speedup

    commit b6d17e00698185a4ad479c0d79ef95bce9d7b78b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 7 18:17:55 2016 +0100

        ConfigurationModel: Memoization

        * implemented memoization for the immutable config object
        * unified access to immutable config via model
        * changed event kind for core selection (no param)

    commit 86df9eeb4d2285efb1c53cdc9eff9cbe4ea969f2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 7 12:11:14 2016 +0100

        Improve core selection panel

        * moved main table to separate class
        * better separation between data and view
        * added count field for composition management
        * CorePanel now contains the business logic, the table only receives
          pre-processed data

    commit 7e8394114be17d15419970610c6615f923554101
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Nov 5 15:17:05 2016 +0100

        Updated layouts, table columns sizes etc.

    commit acf19ac8ffe75ea2a37b91552c9588379b03275d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 4 19:00:55 2016 +0100

        Finish HLS tasks, fix bugs all over the place

    commit 694992e800225248545bcb5a7c2305cefed9d3ce
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 4 09:19:06 2016 +0100

        Replace ZeroLogger by SLF4J and Logback

    commit ff5c4caa59b80a8bf1d3cf2cfced7ba5e5f4e70b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 3 18:33:59 2016 +0100

        Continue work on new TPC GUI

    commit 0a65374e192f2a1c19d736f22221b6ae5c719d28
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 2 22:12:45 2016 +0100

        Build new GUI for iTPC

    commit fe8ccadd93771d9297de7b10eaace68c152d487c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Oct 29 15:10:01 2016 +0200

        Fix Vivado compatibility

        * working Vivado versions: 2015.2, 2015.3, 2015.4, 2016.2, 2016.2
        * implemented VLNVs as version specific sub-Tcls that are sourced for
          the appropriate Vivado version
        * each Vivado version has its own dual_dma IP core version (1.0-1.4)
        * bugfix in HLS script (causing error in 2016.x)
        * updated requirements in README

    commit 415767a21bfbd93eed144ed4e4f7842b9c233c0d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Aug 27 05:14:31 2016 +0000

        Update GETTINGSTARTED.md

    commit 20149f35b37efbb578336d101669cf33c0d43ec9
    Author: Andreas Koch <ahk@esa.informatik.tu-darmstadt.de>
    Date:   Fri Aug 26 22:47:00 2016 +0000

        Update GETTINGSTARTED.md

    commit 335e393101f7a8888e7d6115b251a67042d62e77
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 26 19:56:17 2016 +0000

        Update GETTINGSTARTED-zynq.md

    commit ba76f01a0f40a7838dec128af4410b29e687019f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 26 19:46:56 2016 +0000

        Update GETTINGSTARTED.md

    commit e705a350f43d1ab6e10fc41865cf891de5ad0535
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 26 19:45:29 2016 +0000

        Update README.md

    commit 7c0dd76f5c37ca3b7446a12fe596e05bb1d9a54e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 26 19:33:18 2016 +0000

        Update README.md

    commit 3040b8295851347753594fdb4ce4fd9fec36f242
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 26 21:27:28 2016 +0200

        Add draft for icon

    commit 570774d9a262cbdd53e3a110ba9b91262895deb2
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Mon Jun 13 10:33:34 2016 +0200

        VC709: Kernel Oops bugfix (DC)

         * bugfix for kernel oops (found by EVO)
         * replaces dynamic mem allocation with stack allocation

    commit 63ced96d72cd2bdb73be0a8f49bf44c3249f1d72
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 26 15:34:51 2016 +0200

        libtpc/libplatform: flush logs on SIGINT

         * logs are often incomplete when application is stuck or terminated via
           signals, since file output is not flushed
         * added signal handler for SIGINT to log abnormal termination, flush
           outputs and then exit

    commit 4f584c8eef3b879065618367ccd0b2a30d00e160
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed May 25 08:38:54 2016 +0200

        Fix bug in Vivado master template concerning sim

         * COMPILED_SIMLIB env var should not be required for TPC_MODE=bit

    commit 6700bfd7a4bb1c306ec656b03031eb4126c05696
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed May 25 08:37:38 2016 +0200

        Compose: always use at least one composer thread

         * corner case for systems with too little memory for running Vivado

    commit 085c98163d120f8aa6b950261b4d121c09041f7a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 12 14:43:24 2016 +0200

        Use fixed size thread pool in Compose

    commit 9a962669eb4698f390fb869c3fe687cb1f9c3755
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu May 12 14:42:39 2016 +0200

        Bugfix HLS simulation log dumping

    commit 669fcf3dba1b03e33e8ccb649cac67f49fcbecb4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri May 6 12:50:22 2016 +0200

        Use clang to improve code quality of libs

         * _Atomic type spec required by C11 standard, not enforced by gcc up to
           5.2.x: fixed in lock-free queue and stack (required minor changes
           in API)
         * logging modules: implemented changes in data structures
         * added central cmake/ThreadPoolComposer.cmake file for default
           includes etc.; used to define ANALYZE cmake flag, which uses clang to
           perform static analysis
         * use via: cmake -DANALYZE=1 .. && make
         * performed basic linting without other noteable results / fixes

    commit a1f07b7e6aba6504f2f080a0e96ae7fa02118c68
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed May 4 20:42:00 2016 +0200

        Add python script to load a bitstream for all platforms

    commit 8fa7d3c3ee9a8a7786b9ede377385a12f3e6a828
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed May 4 20:41:37 2016 +0200

        Fix bugs in tpc-build-libs

    commit 51bdd40128dd5650f5e2c417d09485bcfc5e9140
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed May 4 20:41:02 2016 +0200

        Add setup script for paths (convenience)

    commit 4f4b898164362b6a3601a93384e8615d05091d8c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed May 4 20:39:27 2016 +0200

        VC709: Fix bug during init (missing dev names)

    commit 6fce97f850eda22a5c71f390d43b43d11e8c6f6a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed May 4 20:38:29 2016 +0200

        VC709 driver: fix missing kfree on error

    commit daceafa94d8b103c48b953e55d3813fea4fed5f4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed May 4 11:10:55 2016 +0200

        Improve tpc_build_libs script

         * additional script that simplifies building the libraries
         * renamed to tpc-build-libs
         * added 'rebuild' param, help text, etc.

    commit 16ce2b835d904e98e85fd4dd1acdebc7625d630e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 29 13:09:42 2016 +0200

        Increase max Vivado mem usage to 15 GiB

         * moved to abstract method of Composer
         * fixed termination of threadpool in Import

    commit 5708e54ccea6f07242585b2bea7b13d1c6b93866
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 29 09:59:31 2016 +0200

        Decrease extreme verbosity of DSE modes

         * Configuration is only logged once by ThreadPoolComposer
         * HLS is only started, if a kernel.description can be found
         * improved some messages regarding missing descriptions and reports

    commit e5a1ec48c8ab4ab3e85d9494a283d4dbd9ce01cc
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 29 06:43:27 2016 +0200

        Fix problems concerning the memory hog

         * Vivado vandalizes the systems during DSE and imports
         * Xilinx has estimates for peak mem usage, but they are crap
         * added primitive wrappers Import and Compose to limit the amount of
           memory stress on our servers, but does not work well (better than
           previously, though)

    commit 6e3c05815576c5bff39996edff4dc09f70cedb2f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 27 17:13:06 2016 +0200

        Improve readability of log messages during DSE

         * logs are difficult to parse, many linebreaks, missing run
           information, etc.
         * implemented LogFormatter class as the central place for log
           formatting of TPC objects
         * improved all messages during DSE

    commit e4c3e7734885355abcade862b68c1c15a7d67dab
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 27 17:09:00 2016 +0200

        Import: limit number of threads according to memory

         * need to avoid swapping: Xilinx estimates up to 7GiB of RAM for a
           vc709 synthesis/PnR
         * wrote MemInfo class to read /proc/meminfo
         * using memory as upper bound for size of thread pool

    commit d50063d7f4cf5243e5c43d7d96adb0f7bcd8fd9f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 27 10:46:33 2016 +0200

        Import: do not skip incompletely imported IP cores

         * core.description file is created immediately, does not indicate
           successful import
         * skip import only export XML is available
         * delete core.description on unsuccessful import

    commit 4a42955325455881736b250f4edfeb38086c4999
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 27 10:45:44 2016 +0200

        HLS: Dump simulation log, fix co-simulation

    commit 4cc789e71f629ebbdde20ba2b4dcd7f0792b4466
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 24 10:27:52 2016 +0200

        Bugfix: Fix logging functions in debug mode

    commit 809cecf5684162183d3fc97bf6de85a0d0e5d75b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Apr 24 10:24:16 2016 +0200

        Perform profiling and improve TPC overhead

         * added memoization for register address resolution function, which
           called platform_address_get_slot_base each and every time
         * removed unnecessary atomic actions in tpc_functions
         * removed several checks from NDEBUG builds
         * replaced some checks by asserts instead of returning error values
         * overall improvements maybe 3-4% on mountdoom

    commit 97bbfe2065c6b95d6fbfb30667301cbc3b2b0977
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Apr 23 20:07:01 2016 +0200

        Remove logging calls entirely in NDEBUG

         * calls to tpc_log and platform_log should vanish completely when
           compiling with NDEBUG set
         * fixed declarations

    commit f974cadc732eb84d9bfc28c3a2e73342694beb81
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Apr 23 10:29:33 2016 +0200

        Bugfix: SAIFs are read too early

    commit f6200f12a99ff25c96f2dca1368ec4ab0ccccf14
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Apr 23 10:04:11 2016 +0200

        Forgot to checkin subcores patch script

    commit 96ffa72c68e89086c99ff9c8319f93992538161f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Apr 23 09:50:26 2016 +0200

        Bugfix EvaluateIP: support IP catalog cores

         * secure IP uses Tcl scripts to provide blackboxes
         * blackboxes are "filled" by Vivado using the appropriate license
           during synth/pnr
         * scripts are required for evaluation with TPC
         * added scripts generated by Vivado HLS to IP core .zip
         * during evaluation, scripts are now extracted and sourced, which
           appears to work
         * bugfix: extraction would extract both VHDL and Verilog sources, if
           available, which caused conflicts; preferring Verilog now, only
           extracting VHDL if Verilog of same name is not available
         * reading SAIFs prior to synthesis now, to increase matching of nets
         * added implemenation checkpoint

    commit 4abb3b6b62c41ac730a226d4bb95119f6f8937cd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 22 18:06:05 2016 +0200

        Zynq: Fix bus freeze bug

         * apparently, the problem was using HP0, HP2 _and_ ACP at the same
           time; StereoSGBM triggered bus freeze repeatably when using one
           master on HPx and one on ACP
         * possible fix: removed ACP port and use only HPx
         * worked for SGBM, but may cost performance (unclear)

    commit d85da9d1e325d39f02ef2b44a79887ffcb178390
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 22 18:05:41 2016 +0200

        zedboard: Fix bug in benchmark file

    commit db5676a385091da20e6e518062f669f70d66178b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 21 06:30:17 2016 +0200

        Refactor tpc-debug, clean up structure

         * split one mega file into several smaller
         * debug-screens subdir contains headers for individual screens

    commit 920a64c8d51f26aa20b6d9295612ad653e14b9c9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 21 06:08:26 2016 +0200

        tpc-debug: Improve screen layouts

    commit 349ae36db8fec699413f484219a7d666d18f770a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 21 06:08:04 2016 +0200

        Install tpc-debug and tpc-benchmark in $TPC_HOME/bin

    commit d75b32974bd4c98cd7dfb824d4f2b2bf1353ddeb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 20 21:56:59 2016 +0200

        Add benchmark data JSON description

         * tpc-benchmark is fit to generate a machine-readable presentation of
           the basic platform benchmark measurements
         * dumps the JSON format file now; either to first argument of call, or
           automatically to the current platform's base directory
         * adapted Platform implementation: now has optional Benchmark, which is
           the model for the Benchmark data
         * old properties `minimalSetupTime` and `interruptLatency` have been
           removed; the former is obsolete, the latter is replaced by the
           Benchmark model
         * adapted throughput heuristic code accordingly
         * added unit tests for Benchmark model
         * added base benchmark data for all three platforms
         * improved performance in tpc-debug and tpc-benchmark: disabled RTTI,
           fixed broken link-time optimization flag

    commit ae9b96fc68e246dbf3e8ca512cce315f68fccc80
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 18:51:06 2016 +0200

        tpc_benchmark: reactivate benchmark tests

    commit fcf885505fea86d91de1b78f2499d72160e4756f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 18:48:33 2016 +0200

        tpc_benchmark: Add TPC lib versions to benchmark.json

    commit e65d50214fd9e8889b07a291c326c213c40cab22
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 18:35:44 2016 +0200

        tpc_build_libs: Bugfix on zynq regarding debug level

    commit 7db527b5d81b3959e1712f1614d86883b74192a8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 18:22:45 2016 +0200

        Implement python script to build libraries

         * can be used to quickly change and re-built driver and libs

    commit c7367329ffcda24814c19aa4bce4ea5060ac7710
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 18:06:46 2016 +0200

        VC709: Fix hotplug script

         * script used relative paths; fixed to anchor at TPC_HOME
         * improved prgoramming script: doubled programming clock

    commit b05b0d9eff8f07b895383c2f1ea23b956a508323
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 18:05:28 2016 +0200

        VC709: Bugfix potential kernel memory leak

         * rare case leak: if copy_to_user fails, a tiny buffer is leaked

    commit ce2bbb3f4ceb9708e870f31577bd450fe1ee2f57
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 18:03:07 2016 +0200

        VC709: Implement Platform API 1.2.1

    commit 733c92d1246d0c7cef724cbaeedf975be0b1de9f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 18:02:07 2016 +0200

        Zynq: Implement Platform API 1.2.1

    commit bcde1be226e5772b5dc43b4b0bfb1d51a7e2993a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 17:56:22 2016 +0200

        Platform API Version 1.2.1

         * added special addresses for interrupt controllers in design, so that
           they can be accessed in a standard way using Platform API

    commit 372d62f1197adae1808f4055f1b21cf3425f92cd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 17:51:48 2016 +0200

        Fix old unit test case for libtpc modules

         * functions: needed status dummy, fixed
         * jobs: fixed minor checks
         * horrible code; still better than nothing

    commit d5e9908584a1240eb1027b8728a42681903958db
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 17:27:30 2016 +0200

        tpc_jobs: bugfix concerning > 100 jobs in flight

    commit 30fe5c6d36274d643493db2ed7ad63b3423302c9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 17:21:29 2016 +0200

        tpc-debug: Implement push-n-poke monitor

    commit c78519bf90c48fadb03c24f6f5b1aa95b039749f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 19 17:16:47 2016 +0200

        Build TPC benchmarking application

         * can measure transfer speeds for different chunk sizes
         * can measure interrupt latencies for different runtimes (and for the
           interval 1us-100ms at random)
         * generates JSON summary that will be parsed by TPC

    commit b400b750f5a215bce12b74134f05e6af5044875e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Apr 18 10:48:56 2016 +0200

        Generate SAIF files during HLS co-simulation

         * SAIFs improve the accuracy of power estimation significantly
         * can be generated during co-simulation without user intervention
         * added to .zip file with IP-XACT
         * fixed some other bugs as well, e.g., top-level name

    commit d82c93dbfa94dfb68d63d4cd82e8d80bd38d752a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Apr 18 09:43:01 2016 +0200

        Clean non-successful runs during DSE

    commit 8fc29aa3492e2bfdeb1d77ca2391f390c1d7b893
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Apr 18 09:42:02 2016 +0200

        Implement clean and cleanAll calls in VivadoComposer

         * clean should remove only bit and user_ip subdirs
         * cleanAll should remove the entire directory

    commit cb236006283943ef49ef9d280bf16a5df50af422
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Apr 16 07:00:46 2016 +0200

        Scala linting: Remove wildcard imports

    commit 22e7a118740eba4a824fb6c792beb8b6c12023d0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Apr 16 06:14:39 2016 +0200

        DSE: Add target to log messages

    commit cae8cc258bae60605c07ecb4c469975f3ff78fd8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 15 19:04:53 2016 +0200

        ZC706: Fancontrol pin should should be false path

         * path to PWM pin should not be considered for timing closure
         * implemented post-synth hook to add false path

    commit e82a801bd8c6125070f6a9c18261cf5161bcbb23
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 15 19:01:59 2016 +0200

        Baseline: Distribute masters on outs in round-robin

         * PE masters should be distributed in round-robing fashion on the
           available masters to maximize throughput

    commit 8b339ffb322cc08c802bced9d770bbe333f55660
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 15 16:50:17 2016 +0200

        Bugfixes for error classification in DSE

         * error regex was wrong, placer error messages were missed
         * bug in classification: all PlacerErrors were OtherErrors and vice
           versa
         * added summary output after each batch
         * reduced memory consumption on log scans

    commit f8903c2a6a598f96612a7793c2e8790a5a7355f0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 14 14:12:18 2016 +0200

        Fix parallel DSE bugs and improve convergence

         * separated DSE thread coordination from actual execution of Vivado
         * Composers wrap the actual tool
         * ComposerLog parses text log, scans for errors and warnings
         * ComposerResult contains a new result value which cleanly
           differentiates different errors (TimingFailure, Timeout, PlacerError,
           OtherError)
         * DSE can prune more aggressively: at first PlacerError, entire
           composition can be removed from design space
         * bugfix: after TimingFailure, all faster variants of the same
           composition can also be removed
         * several minor clean-ups and improvements

    commit 73c6ac5b07ce8fb2363a4ea7068af12ca3d57b4e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 14 07:32:51 2016 +0200

        Fix bug in DSE where 2nd best would be reported

         * winner needs to be updated in each batch, or else the best of the
           batch would be reported instead of the best so far
         * also added additional pruning of the search space: all elements with
           lower H value can be dropped

    commit 610b97973e556416739edf1f88e07e29b36536ac
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 14 06:55:48 2016 +0200

        Improve fairness in multi-platform DSE

         * available processors are now split evenly between the target runs
         * every target will make progress and less superfluous work is done

    commit d052d63d030efdb61ce2f5cb0a9dce7dc48af65c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 13 18:47:21 2016 +0200

        Parallelize design space exploration mode

         * major push: DSE works in parallel!
           batches of #CPUs size are started in parallel; after whole batch is
           finished, new max freqs are computed from the WNS in case of timing
           failures and the resulting design space elements are added; if
           current best successful (if any) is better than best in DSE, search
           is aborted
         * bugfix: a computed new max frequency for a composition should be used
           for pruning the design space; it is unlikely that higher frequencies
           succeed - significant improvement in convergence speed by itself
         * added Value type in Heuristic, reified DesignSpaceElement (makes code
           more readable)
         * change in DS: removed "hack" which used to give all generated
           compositions the same id; this was useful in single-threaded mode to
           overwrite previous attempts, but causes conflicts with multiple
           threads
         * changed composition output dir: now includes frequency suffix; same
           reasoning as above, would cause problems in parallel runs which
           differ only in frequency

    commit b8d62d06e92488def323ec1d2f0ee19dd283d5d4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 13 14:24:59 2016 +0200

        Use new TimingReport to report WNS path in corestats

    commit 5afb3765631eb9ec5060d2b74623b590fca00689
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 13 14:01:33 2016 +0200

        Implement TimingReport model to parse text reports

         * paths with min and max delay are interesting for the DSE and
           evaluation passes
         * implemented formal model which can be parsed from text report
         * added unit test case

    commit 679e32dab48aa64fbb2ab48905a8ef975c6b41f9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 13 10:15:35 2016 +0200

        TPC++ API: Fix typo

    commit 902c8469dd2df9cd204ee5e952198121bb13dbe2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 13 09:42:56 2016 +0200

        TPC: Bunch of minor improvements and changes

         * Area estimation: uses LUTs now instead of Slices (often meaningless)
         * Core stats: more stats, including jobs/s
         * better error messages for parsing errors in Synth report

    commit f39b2130f6d44706ca3a9834a5c2cc01cd906a40
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 13 09:38:13 2016 +0200

        Zynq: Implement python script to build libs

    commit 8cfa9eb6c6b2562a7a4ebb3b166784bc27f5f1b3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 13 09:36:11 2016 +0200

        Zynq: Fix bug in bit_reload

    commit 33251b680e7a3a4f068e4a1f400f8ff022a8fd20
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 13 09:33:18 2016 +0200

        Remove license from IP Report template

    commit 4c098f6bfe3a994fb6f6527f29917abf0af4362d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Apr 11 10:52:02 2016 +0200

        Bugfixes and improvements for Vivado HLS step

         * limited parallel executions to #CPUs/4: Vivado HLS has no means to
           control multi-threading (like Vivado does)
         * fixed naming of IP: kernel name is now used for both display name and
           VLNV name; previously Vivado HLS would use the top-level-function
           name for the latter
         * cores with an existing .zip file are now skipped correctly; allows
           restart of batch runs
         * bugfix: if HLS report is re-used from Vivado HLS, no link is
           generated (lead to bug)

    commit b38346cdb1d1e3515b3e5fe434d1c044e2cf68c1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Apr 11 10:33:36 2016 +0200

        libplatform, libtpc: fix warnings in init

    commit 34aafab48911d23681886b0f3b0a212fe19332ec
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Apr 11 10:32:31 2016 +0200

        TPC++ API: requiring g++ 5 or greater in header

    commit e77f64a99d9db566c377931f8bb9c7a8186da345
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Apr 7 18:58:05 2016 +0200

        Implement basic interactive debugging tool for TPC

         * recent problems with IRQs on Zynq have made it necessary to develop a
           better debugging tool and a place to gather basic functionality test
         * first (ugly!) draft can show kernel map of current bitstream and run
           MT-IRQ stress test via counter instances.

    commit 6f25f9780b14c6ad7caf92e1cd119e18f41205e5
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 6 15:45:30 2016 +0200

        Common: Missing func get_speed_grade

    commit cde6290de996cba6c09cdb795c84b96e047cfe04
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 1 19:19:32 2016 +0200

        Fix hashbangs in broken bash scripts

    commit b0bf8aa0fdfe101fe33f2fc2449015cd902482ba
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 1 19:12:59 2016 +0200

        Fix hashbang in VC709 scripts

    commit 7c5c46f74060de0ada65bb7f040c28a494c6b820
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 1 19:03:12 2016 +0200

        Implement bit_reload.sh for zynq

    commit 220dbe52c3d99c946b4fb8daa2e76b2af2bce169
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 1 19:02:51 2016 +0200

        Rot13: fix release mode warnings

    commit 494394ad37c87dd3ec014c70c4e4aa6fcb91fa31
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 1 19:02:17 2016 +0200

        Update tutorial and readmes

    commit df35c8ec9e7f911ac92afb27c6779ac36b09c996
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 1 16:58:38 2016 +0200

        Bugfix ROT13 TPC application

    commit 9d9c0e64d1b2e94cc45a4e622a49bfb4f577b35c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 1 11:15:24 2016 +0200

        Implement basic setup command in itpc

         * user selects platform, arch and debug mode
         * builds libplatform, libtpc and kernel module

    commit 07cf9286d1104f3c6cd928ff4237da950b84fdab
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 1 11:14:54 2016 +0200

        Don't require Vivado for 'itpc' and 'corestats'

    commit 6f2fb5c34cc75eba91bd1cd49ca5ab677de7cdd6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 31 18:02:31 2016 +0200

        Fix basic_test example

    commit 38a4524052eceb59ad6229107540834e187274ef
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 31 17:55:21 2016 +0200

        Improve timing on zedboard and other -1 parts

         * Zynq slave ports toward host memory are capable of up to 250 MHz, but
           timing usually fails on -1 speed grade parts
         * reduced targets to 158 (-1) and 200 (-2)

    commit b3a6cd691ca0cfc002149ab62a499434931ace4d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 31 10:58:37 2016 +0200

        Fix bug in DSE exploration

         * heuristic value of new entry computed from WNS after timing failure
           was using old frequency
         * when only varying frequency entries with higher freqs are now dropped
           after a timing failure

    commit e6500ff9f3429caaa7f3a58978a94d15f2677985
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 31 10:23:45 2016 +0200

        Update basic_test.cfg

    commit f3282442c8acf7bc35f7075174f1a6abb4c64e8f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 31 10:21:56 2016 +0200

        Bugfixes regarding clocking

    commit 27d61639c5eaf495fa7eee8f5e90d339653ca179
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 31 09:43:09 2016 +0200

        Add release packing script

    commit 507298416ac609b6a4511354991dd13e9488d3f4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 30 11:53:00 2016 +0200

        Add GNU LGPLv3 license header to sources

    commit fda1075024dc833295ad3ad81f323c4eec0fb5a3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 30 10:15:56 2016 +0200

        Use SAIF files to generate more precise power report

         * switching activity (SAIF) files will be extracted from zip
         * file extension should be .saif

    commit e8acd062cebefb72bfe609cf72279bd1d059ee26
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 30 10:07:04 2016 +0200

        Bugfixes in Import, generate power report

    commit ab6b3e139c3e9de76734773d23e229a6057b8401
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 23 16:44:24 2016 +0100

        VC709: Update to three-clocks-Threadpool

         * also fixed a bug in generate

    commit 9e17f6e5703188c5799dcebb5043c1061dfeadd6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 23 14:43:31 2016 +0100

        Bugfix clocking: Use only one MMCM, then PLLs

         * zedboard has only one MMCM, other clocks need to use PLLs
         * re-use of clock lines with same frequency; no additional clock is
           generated (may help Vivado recognize that clocks are actually same)

    commit 8be1bea2d5402d7a1477337b1880e16bb5b97712
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 23 13:15:45 2016 +0100

        zedboard: Update OLED feature for new Zynq base

         * OLED generates its own clock via new common clocking facilities

    commit 93888ff7501a3b8460c00258a7543214b3a8e2f6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 23 13:14:46 2016 +0100

        Zynq base platform: use three-clocks-model

         * using new clock facilities instead of FCLK-based design
         * cross-domain clocking happens at specified locations

    commit 26d294d824ae0d873b2941957af6eec8940ad2eb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 23 13:12:31 2016 +0100

        Enable re-use of external sys clock port

         * multiple clock and reset subsystems should be allowed in a design
           (plugins may build custom clocks, e.g., OLED)
         * re-using existing port, if possible

    commit 4a063334da87a2fb97494c384e070304d2166ad4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 22 19:29:04 2016 +0100

        baseline: Implement three-clocks-model

         * Threadpool now has three input clocks: host, design and memory
         * each comes with separate interconnect and peripheral resets
         * host is the AXILite clock for control accesses from host
         * design is the clock at which the PEs are running
         * memory is the clock toward memory
         * using new multi-clock interconnect trees to implement

    commit 9136d3624dd2b088a0f7964a039a0a7ce9943f0a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 22 18:35:43 2016 +0100

        Build infrastructure for better clocking on Zynqs

         * interconnect trees now have separate master and slave clocks:
           except for the last stage all ic's are driven by the "inner" clock,
           i.e., cross-domain clocking happens on the boundary of the tree
         * implemented new clocking subsystem creation call:
           uses clocking wizard to generate clocks from sys_diff_clock (or
           sys_clock, if sys_diff_clock is not available) and also generates
           resets (incl. AXI periph/interc.) for all of them
         * simplifies design construction with multiple clocks, enables finer
           granularity of supported frequencies
         * will only work on Vivado-defined "boards"; must have sys_clock
           automation available (e.g., not on Nexys4)

    commit 9024e174ff6cb548fe2ff9c0a173de346a7e0703
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 22 13:10:43 2016 +0100

        Fix bug in timing report WNS regex for pos. WNS

    commit 05e787b0ea9423c820a66b80612496dbf4860e38
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 21 15:56:39 2016 +0100

        New command 'import': Bulk import of IP

         * added 'import' command to bulk import IP cores
         * imports specified in CSV file
         * automatically parallelized

    commit 1f861bf397bb0d8acd0e23b07f50152bea065c62
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 21 15:54:51 2016 +0100

        Bugfix: Evaluation power report reports bollocks

         * was using theoretical max. freq
         * updated to "real" freq according to WNS from timing report

    commit b6e64f3a0f8fb9e91b6dff9c4f74fe840500a07c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 21 09:51:24 2016 +0100

        VC709: Improve speed of main bitstream generation.

         * removed superfluous additional runs, re-using existing
         * writing bitstream file takes ~5Min, happened twice
         * launching run only up to route_design, then writing bit manually
         * improved parallelism by using new TPC func to ge number of CPUs

    commit ddb099409b2f5e201d0731d7c537193d1c7db8f0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 21 09:47:40 2016 +0100

        TPC Core Evaluation: Improve speed and accuracy, report power

         * exploration directives removed, surprisingly faster _and_ better
           results for out-of-context synths

    commit b0aa15629afb3ff8fba88a5c5c5176deca09cacf
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 21 09:47:10 2016 +0100

        Minor bugfixes

    commit 9cb5264d1625f89d4caee6f1e69537d6fd51d963
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 21 09:45:52 2016 +0100

        TPC Core Evaluation: Increase timeout, report power

    commit 6506331b74798e89482971332aee7aff44f4a197
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 21 09:45:20 2016 +0100

        corestats: Fix ordering of clocks in report

    commit 86dd6b743c34e19d446243b0d4cac95eece87c4a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 21 09:41:18 2016 +0100

        DSE: read timing report to generate new run

         * if frequency may be varied during DSE, use the following approach
           after a timing closure failed: Extract WNS from timing report, add to
           last target clock period and add repetition of same composition with
           new frequency to current design space (& re-order ds)
         * adding the repetition avoids performance losses due to coarse-grained
           frequency reductions, re-inserting in the ordered design space
           guarantees that it does not preempt a design that is deemed better by
           the heuristic

    commit 805c0979ff1e555ed5ebd772eb1759ef37b82a46
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 15 10:37:03 2016 +0100

        Update platform.descriptions: Better freq spectrum

         * remove limited frequency sets from all Platforms
         * Zynqs will require move to better clocking subsystem

    commit aed41308f5a8059638d25f7fb57222e1bffe5398
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 15 10:33:09 2016 +0100

        VC709: free design clock frequency

         * VC709 designs were rather arbitrarily restricted in terms of the
           available frequencies
         * computing divisor value now instead, can generate clock frequencies
           at much finer granularity, resulting in better performance

    commit 32bf0290a8b30a90afcfed3db80d97a7da835d90
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 15 10:25:01 2016 +0100

        Add average clock cycles to core.description

         * Core now contains attribute averageClockCycles (independent of Platform)
         * new command line arg 'averageClockCycles' can be passed to AddCore
         * HLS step automatically parses co-sim report
         * Heuristic implementation only uses fallback to co-sim report, if no
           value is found in Core, and only uses one cycle assumption if no
           report was found (w/warning)
         * also added unit test

    commit 193c0100054dedf8114a7f4ef81efbd1a1589088
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 15 10:22:53 2016 +0100

        Bugfix: reactivate deep packet mode FIFO

         * deep packed mode FIFO for last stage of msater interconnect trees got
           de-activated accidentally, leading to build failures in VC709 designs

    commit 5286d5161222b726edf447d8cbed7f025d81a1ad
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 14 17:26:33 2016 +0100

        Squashed commit of the following:

        commit ac9d473b8c3e24863d3742b80885a7f15cb9bd5b
        Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
        Date:   Mon Mar 14 17:14:14 2016 +0100

            Improve warnings on missing reports

             * missing co-sim reports now trigger a warning
             * minor fixes and improvements

        commit bdcd796319c889d66376f05423524180347cc725
        Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
        Date:   Fri Mar 11 15:16:35 2016 +0100

            Re-implement design space exploration

             * original DSE code was extremely hackish
             * DesignSpace class cleanly capsules the spanning and enumeration of
               the design space with the given variables
             * uses new Heuristics class for ordering
             * moved ThroughputHeuristic there
             * other heuristics can be implemented in the future (if need be)
             * cleaned up a lot the code, much easier to read now

        commit 3098cca6f65314de44765c144a7398729d2dbf90
        Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
        Date:   Thu Mar 10 18:53:18 2016 +0100

            Refactor TPC code

             * using Target in more places, minor clean-up

        commit 1d56d298bcddc9e1d3253370972f5a8b2eb9c8a3
        Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
        Date:   Thu Mar 10 18:13:08 2016 +0100

            Refactor TPC code

             * implementation of 'alternative cores' feature led to massive overhaul
             * implemented proper abstractions for the reports (Synth/CoSim)
             * Platform/Arch pairs are subsumed as Target (not complete yet)
             * cleaned up several tasks
             * implemented basic functionality for alternatives
             * started to implement the heuristic in a cleanlier fashion
             * reduced Common to much fewer methods; need to remove some more
             * next step is to clean Compose: split huge generate functions

        commit 9b7254119b4fa06b3b5ca6265fa051df5e285081
        Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
        Date:   Wed Mar 9 16:58:03 2016 +0100

            Reduce efforts in evaluation P&R

        commit c48b90d76b74ec4f6dc459d854cfbad79af142fb
        Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
        Date:   Wed Mar 9 14:46:39 2016 +0100

            Checkin missing files for new Command structure

        commit 287172283fe049643ed011574642d3791d6e4f19
        Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
        Date:   Wed Mar 9 14:23:49 2016 +0100

            Clean main scala code

             * removed obsolete methods
             * removed 'Generator' tree and moved GenerateCommon to Common
             * implemented & used proper VLNV class for version strings
             * cleaned Common

        commit 04baa01b8f353023572eb6b8c7c09582de8057fd
        Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
        Date:   Wed Mar 9 13:10:42 2016 +0100

            Refactor TPC commands

             * removed all the main's flying around in the individual commands
             * new structure: Command is base for all TPC commands, provides factory
             * renamed GenerateThreadpool to Compose
             * renamed GenerateHLS to VivadoHighLevelSynthesis
             * removed obsolete 'analyze' and 'evaluate' commands

        commit 741fd113ac4a0356126c79d2e162ab89ec0aa3fe
        Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
        Date:   Wed Mar 9 10:35:44 2016 +0100

            Fix problems in evaluation runs

    commit 4e0fc0c9e4fe385da0dea3a95d602eb87662206f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 25 11:23:16 2016 +0100

        ZC706: Updated interrupt latency

    commit ef426a19d1fc4433f19644e6473712b53a63a6ca
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 25 11:22:37 2016 +0100

        VC709: Removed rpr namespace in libplatform

    commit 14bc2921840d9eda0b3acffa1e91f9e96c18b89f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 11:17:54 2016 +0100

        Implement 'dry run' feature in DSE mode auto

         * it is helpful to perform a dry-run on the automatic design space
           exploration to evaluate the list of designs that would be explored in
           order and see the performance heuristic for each
         * 'dryRun' key takes as value a suffix for CSV files with the DSE lists
         * when set, Vivado is not run at all

    commit 19e0f89dd6d1b692b9ce56749d0413731567b1e4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 11:15:44 2016 +0100

        EvaluateIP: Fix broken return value check

         * return value of Vivado is now properly checked
         * if an error occurred, the temporary files are kept

    commit 17788fe07c55decae364168e634662387507d810
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 11:15:08 2016 +0100

        CoreStatistics: Add absolute counts for area utilization

    commit abd19ec0e5dfdc5135f5b6266ac947c90619b23f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 11:14:23 2016 +0100

        Add Vivado version checks to all commands

    commit e37cd310180d90643ba5f50cfdaefbd9ca31e453
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 10:59:52 2016 +0100

        Implement method to check Vivado version

         * implemented in GenerateCommon
         * doubles as check against missing executable in path

    commit 82a83a3788f8be9a075da811f573a645a935c185
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 10:57:05 2016 +0100

        AddCore: Make execution resilient against errors

         * if one execution failed, all were aborted
         * now exception is reported and others are continued

    commit 3bd5d6138f15a15f6f0c7a05e0ec0a61ef22dcc0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 10:51:45 2016 +0100

        zedboard: Update interrupt latency

    commit 3cdbd2b6050cfc15a80632a96dd477bc796f0aa1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 10:45:11 2016 +0100

        EvaluateIP: Improve area estimations

         * area estimations from out-of-context P&R were off
         * added more aggressive optimization flags
         * design checkpoint should be re-usable

    commit 2c50da689c866e32ff338787fe48dca9f716d302
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 10:43:29 2016 +0100

        baseline: Fix bug concerning PEs with multiple masters

         * PEs with more than one master interface ran into a bug concerning the
           number of slave interfaces at the outward ic trees

    commit d70a39e15fdcbe3f3247e236570babffb083ac1b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 10:18:50 2016 +0100

        Zynq: Rework interrupt handling and sysfs files

         * moved sysfs files to tpc_status dev
         * added new sysfs files: total_ev and pending_ev: total_ev returns the
           total number of received interrupts, pending_ev the number of
           pending, but not acknowledged interrupts for each slot
         * simplified interrupt handler, race condition guards on pending_ev not
           required, since software guarantees exclusive access to slot
         * implemented separate wait queue for each slot, so each queue only
           contains the correct thread during wakeup

    commit bb48d08ac1f2ce1fe05420cd9bc9851aebfb95dd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 10:14:16 2016 +0100

        Zynq: Remove DPI stuff from default build

    commit 236114e13e73ca6b3696b3926602077aeb4a7f58
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 10:13:09 2016 +0100

        Zynq: Fix bug in error propagation in platform_write_ctl_and_wait

         * platform_write_ctl_and_wait ignored errors due to wrong return value
           comparison; fixed

    commit c03558a2e54aab2a967622f3e586fa7507307ec6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 23 10:12:38 2016 +0100

        Zynq: Fix missing logs during platform_init

    commit 69fd4285a5ca5e04a7e60d3fb0823059907ecaef
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 16:01:39 2016 +0100

        Fix broken 'platform-slots' test

         * was using old HW interface, expected first arg in the platform run
           at wrong address (0x18 instead of 0x20)
         * improved error messages when encountering Platform API errors

    commit 148fed29def2b18fd50c96ba1b5387b2cde6f591
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:59:35 2016 +0100

        Platform test iplatform: Add platform_read/write_ctl test

         * implemented speed test for platform_read/write_ctl
         * now using steady walking average for the values, slowly converging to
           geometric mean (can serve as automatic stop condition with a change
           threshold)
         * several minor changes and improvements

    commit 5804783ac53251cd6c2d6a1be9ae05dc1865de2a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:57:36 2016 +0100

        Platform tests: Use static linking and LTO

         * Zynqs benefit hugely from link-time optimization and static linking
         * >6% performance boost on zedboard

    commit ad8a5833928b783d60b26785dad9b71b933fe4e1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:56:24 2016 +0100

        Platform API: Remove 'rpr' namespace in C++ inclusion

         * also increased version number to 1.2

    commit e13c9259ec5fc9c7afe1208e09655569ddb9e01f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:55:52 2016 +0100

        TPC API: increase version to 1.2

    commit 92d435377bd7a58d0ee384effcab02cfb86dc5b8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:53:03 2016 +0100

        Examples: Prefer static linking of libraries

    commit 5b29e5084cc56c5b328823462a20f469d884604d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:50:54 2016 +0100

        benchmark-latency: Update to TPC(++) 1.2

         * updated both versions, though C version is now obsolete
         * added static linking by default, and link-time optimization switch
         * performance boost of >6% on zedboard
         * set defaults to more sensible values

    commit 372abcd5209c87c0907bb311f503821c3e3bc47b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:47:42 2016 +0100

        TPC common: Add func id to log of slot acquisition

    commit 9cad2169e0150f6325605c0b7c83a3559e666770
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:44:45 2016 +0100

        TPC++ API: Make async launches optional

         * measured considerable performance hit for futures on embedded systems
         * returning a future is nice, but should not be the default
         * reverted launch and launch_no_return to previous state
         * new async_launch and async_launch_no_return return futures
         * bugfix: return value did not have correct capture semantics

    commit 7f91cad8b6a8d4b23eac8293f9454d3041b92a4e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:41:20 2016 +0100

        TPC API: Remove superfluous 'rpr' namespace

    commit c9099ab4d414d93fbc1d2fab688fd10e9cadfdbb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:38:37 2016 +0100

        Bugfix static linking symbols for gen_stack.h

         * linking errors due to name conflicts for gs_push and gs_pop
         * gs_push and gs_pop are now static, should be inline-only in any case

    commit 4a46ab8f1e9a69fdda3a15f6d78017faba0e57a0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:17:50 2016 +0100

        Implement 'arrayupdate' kernel

         * 'arrayinit' covers write-only accesses w/bursting
         * 'arraysum' covers read-only accesses w/bursting
         * read+write accesses were missing, now covered by 'arrayupdate'
         * takes array of ints and updates each element by adding 42
         * requires one read + one write in each iteration, no bursting

    commit c4c2f39a80262129efc27d087db321483f428f27
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:14:33 2016 +0100

        Zynq: Debug feature is broken when using patterns

         * annoying: get_nets and get_nets -hier either provide too few, or too
           many matches for many patterns; it is hard to pin-point the nets one
           really wants when using the -hier variant
         * fixed for now; but user needs to take care to specify the patterns
           very precisely, which requires a lot of white box knowledge of the
           design

    commit 3f1ece6c6235382b4fc3e30ddbb472a1b32307a3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:14:10 2016 +0100

        Zynq: Remove superfluous -jobs 8 from synth

    commit f6c3edbdb86cc3b6fa0813f549b898a9c11a44dc
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:11:34 2016 +0100

        Make EvaluateIP dump a re-usable design checkpoint

         * since out-of-context synth has been done already, it would be useful
           to preserve the synthesized netlist for later re-use
         * added commands to Tcl script and new output file in TPC

    commit f1c6f0fa36264c2f7698332d180a30b16526f5d7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:10:13 2016 +0100

        Fix erroneous printing of debug net patterns in Tcl

         * debug nets with wildcards are not properly recognized in Tcl
         * need to use {} instead of "" in list constructor

    commit 4642332b9a4f5d6571c85981e152c95f0ffab0d3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:08:30 2016 +0100

        Re-activate status log messages from Vivado

         * P&R takes too long, some intermittent messages should appear

    commit acc367e827dce797b5e6c58cde76d7647ed29fa9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 22 15:07:08 2016 +0100

        Bugfix tpc::create_debug_core

         * arguments can contain lists, which should be connected to single
           probe; fix correct wiring of these cases

    commit 777820a29d21bbdaa03dfdc9b78fbe80b0db06eb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 18 18:03:10 2016 +0100

        Zynq: constrain GPx nets better

    commit 77a1f9e1b2b7d6db9f3d6ef27d41393db84427e8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 18 17:49:30 2016 +0100

        EvaluateIP: keep util and timing reports

         * moved to output directory instead of temp

    commit 72c99cace925aded29f20c92cd15196a5f25ba67
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 18 17:47:51 2016 +0100

        GenerateCommon: throw exception in vlnvFromZip

         * if 'component.xml' cannot be found in the given .zip, throw a more
           verbose error

    commit 7af7a9f8a2b6203f315807a16f71406658c957b4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 18 17:41:55 2016 +0100

        Implement HLS-based counter PE

         * using System Verilog wait()
         * minimal runtime: 15 cycles (Vivado overhead)
         * upwards of 15 cycles accurate

    commit 3d827cf41c494b3647f643994d67894fef88bf7f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 18 17:40:30 2016 +0100

        baseline: implement full S-AXI wrapping plugin

         * automatically wraps full S-AXI interfaces by prepending Xilinx AXI
           protocol converter
         * reduces wiring overhead in case of pure AXI4lite

    commit 6e0b47c84a71c1fafea6a8c605fe235f1023833e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 18 17:37:25 2016 +0100

        Zynq: Fix bugs in debug feature plugin

         * now adds M_AXI_GP0/1 again, went missing
         * write_ltx now checks if debug is activated

    commit 57ba1adeaa8802763ffef6f92ef6c9ac047ec574
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 18 17:36:15 2016 +0100

        ZC706: Bugfix return values of plugins

    commit c7e3eee2469605a5ef465cb61e7998abf0a677c2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 18 17:33:58 2016 +0100

        Reduce overall log noise

         * reduced chatter during place-and-route
         * removed interrupt controller sensitivity warnings; mismatch is
           intentional

    commit 092874a0bbb2e74af2174f838f038fcd08fd24f5
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 18 17:31:51 2016 +0100

        baseline: add plugins and provide pe-wrapping event

         * plugins as per default in plugins subdir
         * event 'post-pe-create' is used to trigger pe-wrapper plugins
         * plugins are expected to be cleanly stackable
         * bugfix in common to propagate args correctly

    commit 3b6ae7f3b157ec60ff337ad6b1df4e651667a098
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 18 17:29:55 2016 +0100

        Extend Debug feature with user-specified net patterns

         * DebugFeature has new properties: useDefaults, nets
         * both optional, first enables default debug nets, second provides a
           list of patterns for net matching
         * added in main flow, and also updated unit test

    commit 68f588ce3a86d67c13cb964076e5b9b59417b3ea
    Merge: 940bbc6 7b2ccdb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 11 12:52:48 2016 +0100

        Merge branch 'zynq_family_design'

    commit 940bbc6bc034de0f2ab1bb18bdc34675d5996178
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 5 16:43:15 2016 +0000

        zynq_ioctl: Remove old command code

         * all TPC commands are now handled by ioctl on the control file
         * bufferid, alloc and dealloc sysfs files are removed
         * driver version is 1.1

    commit 7b2ccdb510b3c3e02fcf96f96f9561f822f50fa5
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 11 12:50:09 2016 +0100

        Update basic_test to new Zynq names

    commit 909855007994951a0c51b3928dfe2442cb3c3a67
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 11 12:49:04 2016 +0100

        Reduce log output in Vivado logs

    commit f5785fc8e674270734b2e501bd36e90aeca80d77
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 11 12:48:44 2016 +0100

        Move to Scala 2.10.4

    commit 34be8441e6542ce7058dfa2cf3abb42036ced44b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 11 12:47:37 2016 +0100

        Bugfix: Don't abort all run combinations when one fails

    commit d23d719a3a687ca6a6f1340b64cdef3fca9ee063
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 11 12:46:54 2016 +0100

        Bugfix: bd and core directories should default to $TPC_HOME

    commit 68221d82d01ef31f139d5b81c23728bb528319c3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 11 12:44:54 2016 +0100

        Refactor Zynq platforms

         * Zynq base design extracted from latest zedboard design
         * new plugin interface: subdirectories are scanned for Tcl files
         * common lib provides hook-in functions for plugins to be called during run
         * isolated platform-specific stuff for zedboard and zc706 in plugins

    commit 838b590d0ba5f769ef5f2c8be5ff68d8ce1f38e1
    Merge: 3e0b169 b5ed668
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 9 17:53:00 2016 +0100

        Merge branch 'zynq_ioctl'

         * switch Zynq platform to ioctl implementation of all driver calls
         * better performance, fixes bug with Zynq HPx ports

    commit 3e0b16999927b67b8b0b673a7643bf472346a60f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 8 13:32:43 2016 +0100

        Fix copy semantics in basic test.

    commit fe4febb3bfee3ab2230ba26a45ad50df317d001a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 8 12:07:19 2016 +0100

        TPC++ API: implement multi-threaded data transfers

         * new compile-time flag: TPC_COPY_MT
         * if set, API uses futures to perform all data transfers in separate
           threads and collects them prior to launch
         * effect on performance depends both on platform and application, hence
           not activated by default

    commit 45e61d2f1172f59c482e009044f10df2c0bf2d3f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 8 11:02:37 2016 +0100

        TPC++ API: Implement missing output-only copy semantics

         * launch argument use for input-only and inout arguments can be
           expressed via the type system (const vs. non-const)
         * output-only cannot be expressed via type system, thus generating
           useless data transfers with the C++ API
         * implemented new generic type OutOnly<T> to wrap output-only arguments
           and implement their copy semantics: allocate -> use -> copy-back
           -> free, w/o intermediate copy-to
         * C++ API now has same expressiveness as C API

    commit ba3a1e530a2dfab0bcb9873ed1f90a379822f488
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 8 10:20:06 2016 +0100

        TPC++ API: Fix launch with return move semantics

    commit 64972556358152794ad8f8514abf919032a92b3d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 8 10:18:10 2016 +0100

        Platform VC709: Fix invalid read accesses (mem bug)

    commit 92d52d46ce229193f66c464e99a38cca305ef745
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 8 10:16:38 2016 +0100

        Platform zedboard: fix debug nets for HPx/ACP ports

    commit ef397fba725c59d9400f767fad6f66dd24d87a61
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 8 10:14:10 2016 +0100

        Implement task to gather IP core statistics

         * it would be nice to collect the evaluation reports in spreadsheet
           files automatically
         * new command 'corestats' produces a CSV file for each Plat+Arch combo

    commit fe6e13ab89defdf9c094c05a28ad600b864e72ab
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 5 16:38:02 2016 +0100

        Implement a basic memory interface test

         * basic test uses bitstream comprised of kernels 'arrayinit'
           (write-only), 'arraysum' (read-only) and 'arrayupdate' (read-write)
         * accompanying test uses TPC++ to check top-level functionality
         * also added TPC config and compositions

    commit 668b25588c414feb0771889e9abafb2e1303e753
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 4 17:07:45 2016 +0100

        Cleanup TPC status memory after init

    commit 96f71f34dc1f4c5066a8d179202e6d474d3dbcb0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 4 17:07:02 2016 +0100

        Fix dev memory leak in TPC++ API auto launches

    commit 976af823e77d06aba007fd9581a2a7c2e9743c0f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 3 16:57:45 2016 +0100

        Missing escapes in GETTINGSTARTED.md

    commit c2cf61c2235a54405b308401800c1d3b4c9156bc
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 3 16:54:47 2016 +0100

        Add a "Getting Started" mini-guide

    commit 8f8ac0547731695a9e33ddd97361170d60c32a39
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 3 16:54:25 2016 +0100

        Prepare a short README.md for the project

    commit 3661cca059e57d1d71099ac3e919b51b3469ef94
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 3 16:28:09 2016 +0100

        Fix incorrect core IDs when generating via HLS

    commit 76ab13b773a26a68af4703798f2a87e41855da3b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 3 16:24:42 2016 +0100

        VC709: fix permissions bug on device files

         * udev rules seem to be broken; no time to investigage
         * simply chown'ing the files to the calling user (workaround)

    commit 52accc6b1f1f030237c488b97412f074c2e46077
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 3 14:15:22 2016 +0100

        VC709: fix bug in address map

    commit 59367a6712ceb5026dbd08fb245a120caf7c9aeb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 3 13:32:58 2016 +0100

        TPC++ API 1.2

         * removed rpr namespace
         * moved device id to class instance member (instead of type)
         * launch methods return futures
         * non-critical code uses exceptions for error handling
         * correct copy semantics for const/non-const args
         * using static_assert for type traits instead of assert
         * using is_trivially_copyable instead of pod type trait
         * added constness to most methods

    commit cbf7c635eba30f2cfcde64e0c0f63b177ae22f56
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 18:06:58 2016 +0100

        Implement test application for basic_test bitstreams

         * uhoh, this is really ugly code, but works for now
         * checks arraysum, arrayinit and warraw for functionality of the memory

    commit 63650cbc71fb8e461dc093b98d98749cf7f44201
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 16:34:35 2016 +0100

        Add auto-wrapping of full AXI3/4 slaves

         * 'baseline' now wraps PEs with full AXI3/4 slave interfaces in a subgroup
           with a protocol converter to AXILite in front
         * saves dozens of wire at each connection, relaxes the design

    commit 2852bddf7678db01224bd2de57cc902602aa4d5d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 16:26:47 2016 +0100

        Fix version check for use in Vivado HLS

         * common lib is sourced in HLS, which does not have version command
         * check is skipped when no version command is not available

    commit 674d266fffddbede6b978f6c644555922146384e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 16:26:09 2016 +0100

        Add evaluation step to HLS template

    commit 64dd4226bd76aa120455d13ec01cb22d33652f8c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 16:25:14 2016 +0100

        Move common lib sourcing to design.master.template

    commit fca85b8ed624ee1ab23b75f1619916deeffb50dc
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 16:22:11 2016 +0100

        Clean user_ip subdirectory in projects prior to run

    commit 816744b648db9f3a71f68d3ce219ae5c92ce95de
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 16:06:10 2016 +0100

        Fix unfiltered HLS runs in dependent execution

         * bug: dependent HLS runs were not filtered, i.e., run for each Platform
           and Architecture, instead only the combination of the main run

    commit 8a49a4fad2013ef57b7a4f6fd97c85f1e03568d4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 16:01:52 2016 +0100

        Fix broken evaluation for HLS generated kernels

         * evaluation does not work if IP uses encrypted sub-IP (e.g., Vivado
           HLS with float/doubles) due to cumbersome instantiation process
         * reverted to using HLS evaluation results if HLS is used
         * no fix for custom IP cores: instantiation of sub-IPs too messy and
           involved; will not fix (-> don't use encrypted IP)

    commit 0eb3d1eaafb33090a2dee7f381664265f7b8ff51
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 15:53:23 2016 +0100

        Refactor and streamline zedboard Architecture

         * cleanly grouped modules
         * simplified interconnections (using new IC trees)
         * improved debug feature: ILA code can now handle absent M-AXIs
         * minor bugfix: OLED reset now sync'ed to FCLK1 (relaxes design)
         * several minor improvements and bugfixes

    commit 2a8871d127533870c53c4f1049dadf65f2498763
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 15:50:54 2016 +0100

        Fix 'warraw' kernel description

    commit 44d3a491d3c4e5032bc75e63e8eebdff90661bd4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 10:47:59 2016 +0100

        Add 2015.2 Vivado version freeze to common lib

         * version is checked in common lib now, no upward compat

    commit b7f2650671b05a4962c41dbdae9545b346b78a97
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 10:46:58 2016 +0100

        Add Xilinx AXI Protocol Converter to common lib

         * added instantiation routine in common with defaults AXI->AXILite

    commit 782705e0891b3f37c1685d78d0316ab078722661
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 2 10:44:48 2016 +0100

        Fix erroneous reset connections in IC tree

         * resets in IC tree special case "bypass" were wired incorrectly
         * critical: designs unlikely to work

    commit a2417706f9b652f29eaf226b21a28eb1e34aeaa7
    Merge: 6a0b213 4f64be6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 26 18:40:21 2016 +0100

        Merge branch 'baseline_mgroups'

        Pull dev branch for optimized 'baseline' arch into master: Improves
        input/output interconnect tree generation (general method); adapts
        number of output ports to platform (reduce overhead on VC709).

    commit 4f64be61d6568d548014431b622c40895dba158a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 26 18:34:00 2016 +0100

        Implement platform call to get bitwidths for masters

         * platform::max_masters returns a list of positive integers: each
           represents a slave port with the max. number of masters that can be
           connected; used by baseline architecture to create master ports
         * bugfix in baseline: infinite loop on max masters
         * implemented new call in all three platforms

    commit 6a0b213646466819cfadd1f60da50b0f737c6c15
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 22 16:05:47 2016 +0100

        Implement interactive TPC console

         * new command: 'itpc' starts interactive console
         * also added new shell script 'itpc' to start directly
         * user can list currently available kernels, cores
         * user can add existing IPXACT core interactively
         * user can build a complete bitstream configuration and start Vivado

    commit 0b3a245db9753f1ff8c9aa3de176f06f610dc2d9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 22 14:33:42 2016 +0100

        Remove "LogFile =" output at start

    commit d8926a983e4b24ead1697a21549e151cdb3cc7b3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 22 14:12:33 2016 +0100

        Make GenerateHLS generate core.descriptions

         * cores are evaluated via AddCore now, descs are generated
         * removed evaluation from HLS script (will be done by AddCore)
         * adapted findCoreDesc to run HLS if none is found (as previously with
           kernel.descriptions)
         * flow works again automatically

    commit 1ed28ea9cf01a178cae3c3dc35b9d92af91bf96d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 22 13:51:42 2016 +0100

        Fix minor bugs in AddCore

         * issue exception when .zip is missing or non-existent
         * fix link creation: skip when linked is same as link

    commit dbc6b9a646530c6db59753f5b62d38e6cd585fdd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 22 13:10:22 2016 +0100

        Implement bash script 'tpc' to run TPC

    commit 6e1e9d81ad2e9e588a0075f205f216204df59734
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 22 12:53:22 2016 +0100

        Switch default TPC_MODE to 'bit'

    commit a5c0afa43c228265240e4c6fc983b4047615a5a9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 15 18:22:28 2016 +0100

        Switch GenerateThreadpool to use core.descriptions

         * uses core.description instead of kernel.descriptions now
         * re-organized custom ip: now in project_dir/user_ip
         * worked on DSE implementations, code is still ugly (needs more work)

    commit 5a77b9d7986111c566a8e5e2c7d0472c08b363e4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 14 17:07:27 2016 +0100

        Implement core.description files

         * major new feature: core.description files
         * contain name, version and TPC ID for a given .zip
         * used to integrate existing IPXACT IP cores in the TPC flow
         * two new TPC commands:
           addcore zipFile <ZIP> id <ID> adds an IP core as kernel w/id
           evaluate <ZIP> <PERIOD> <PART> <REPORT> produces an evaluation report
           for the IP core in <ZIP>
         * user IP catalog is built on-the-fly, similarly to the mechanisms for
           the other description files: the 'core' dir (configurable) contains
           the usable IP cores, including those added via addcore
         * need to make GenerateThreadpool search core.descriptions first and
           only run GenerateHLS when none suitable can be found

    commit a16712b3c4fd505a89901bc3fd9bab2517e97645
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 14 10:56:04 2016 +0100

        Add new 'Core' description class

         * describes ready-to-use IP cores
         * will be produced by HLS step, or manually in case of custom IPs

    commit 2cc8da41db7ff0ff6b59dade6438d2c99f2fcc34
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 17 18:42:38 2015 +0100

        Implement tree builder in common, use in baseline

         * create_interconnect_tree builds AXI Interconnect tree: cascades
           interconnects to accomodate N masters/slaves (1 port on the other
           side)
         * baseline uses this to simplify the master/slave generation; also better
           suited for general purposes (e.g., MIG cores don't have the same
           restrictions as Zynq HPx/ACP ports)
         * idea is to have an ArchitectureFeature which configures this;
           however, since this is mostly determined by the Platform, it is not
           clear how to pass these values at the moment

    commit 68ffd1d360a6c41a488fe1efe29fa90e07efa34a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 15 13:29:10 2015 +0100

        Use Vivado Sim as HLS default simulator instead of ModelSim

    commit 673d81c19e52ce05f438f8c246218c94c1990246
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 7 10:55:52 2015 +0100

        Remove check for COMPILED_SIMLIB in bitstream gen

    commit 14c76552520b744beabe72d6de24e3ccc508b874
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 10 19:11:16 2015 +0100

        Add license file (LGPLv3)

    commit 6f99c0a3f6cebd222e1b949c5d49f4b43a0dc06d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 10 18:36:00 2015 +0100

        Implement "Debug" PlatformFeature for zedboard

         * setup HP0, HP2 and ACP slaves, GP0, GP1 masters for ILA monitoring
         * also track interrupt lines at PS, but not below in the design
         * note: increases synth time significantly

    commit 12a8e0ebacd1f2c7de4a6222d72de56ae82bf72b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 10 18:33:48 2015 +0100

        Add PlatformFeature "Debug"

         * Debug feature configures ILA debug cores in the bitstream
         * data depth and pipeline stages can be configured
         * Platform implementation passes a list of nets to monitor
         * added unit test for the basic syntax

    commit 61a538f947edaf7cd8767e239cfec7b34a2e6890
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 9 11:14:47 2015 +0100

        Fix TPC unit test cases

    commit 6ec5faa72806d5a20dc5e56c2d863d7430ccf0be
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 9 11:01:37 2015 +0100

        Remove obsolete example kernel 'add'

    commit e98843a478cb1aae9a3fbeeb25d3cdeeab6bbe8a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 9 10:58:33 2015 +0100

        Reduce verbosity of TPC log output

    commit eeb27ce296fba8137f250e94693628d875491ed4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 9 10:52:22 2015 +0100

        Implement ROT13 cipher implementation for TPC

         * ROT13/Caesar cipher: shift uppercase latin letters by 13
         * implementation as hardware kernel in TPC
         * testdata: Shakespeare's "All's well, that ends well"

    commit eb2985185b87fed0023c327d9d5564249f1bc1fe
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 9 10:48:44 2015 +0100

        Remove Chisel stuff from main branch to chisel branch

    commit 7cdad97113511a301f0677b1d07f5555025da1bf
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 9 10:12:41 2015 +0100

        Add interactive Platform API test

         * uses ncurses GUI
         * same as recent low-level test for Zynq: alloc/free, copy-to/copy-from
         * both tests run until keypress

    commit f096da76aa2276287af6ec1cb4e23666fbc19a9b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 9 10:09:14 2015 +0100

        Update documentation

         * started to include work from recent deliverables
         * basically, a lot will have to be rewritten

    commit aa881ca28746220ddc1309a7bcc93935d2b2d9dc
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 9 10:06:54 2015 +0100

        Exclude derived files in doc

    commit 7a2dd6832968c625f1dc43c7321a92eea3e9d11c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 4 14:52:03 2015 +0100

        Fix bug concerning symbolic links of libs

    commit 98d14cf28ee056700ee87d0ad45656584f3f368e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 4 14:36:19 2015 +0100

        Fix bug regarding hexadecimal format for composition hashes

    commit e8756b3c515210289a7f3118600b6f04177d0d84
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 4 14:35:41 2015 +0100

        Use highest supported frequency for HLS, instead of lowest

    commit 36d3415beb55ab26356fef1686ae238c4a3cb3d9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Oct 30 13:17:07 2015 +0100

        Improve header files wrt HSR comments

    commit e1bdcf6e4fa0d41fe628a81ffdfa2b072511ab27
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 27 10:47:54 2015 +0100

        Updates benchmark-mem example

         * careful: currently only the C++ version really works

    commit b00b0ffedcabfd5e5f3e5c684a83dc07b72a0573
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 26 19:09:10 2015 +0100

        Fixes missing libatomic linkage on armv71

    commit b5ed66899bd78dcff57436b517a2859f5026fe6c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 26 19:05:13 2015 +0100

        Implements optional support for the ioctl driver interface

    commit 98af94fdc629041d866eae15de8c105eb36bac46
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 26 14:15:18 2015 +0100

        Adds udev support for memory device files

    commit a9e0f5d1e6f8d0f57d79f5953fce35921be6f24a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 26 12:14:40 2015 +0100

        Fixes bugs in ioctl implementations

         * no more passing kernel virtual addresses to user space (!)
         * errors and warnings are still klogged in release mode
         * removed several ENTEREXIT level messages (noise)
         * implementations seem to work correctly now

    commit cf103fb653354fbaf3b77034230929a1d9fda323
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 26 12:09:54 2015 +0100

        Reimplements ioctl test based on ncurses

         * two tests: alloc-free and copyto-copyfree
         * alloc-free only allocates and releases memory
         * copyto-copyfree uses 2-in-1 commands to perform transfers
         * tests run open-ended (until user interaction)

    commit 27e61b2c967dee55e57aefd19fbca0b2ed80244c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Oct 24 17:41:37 2015 +0200

        Provides basic implementation of the ioctls (not working)

    commit a0cd95b40756a8ce9d453fdd26303b29b1d5e6e6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sat Oct 24 11:32:25 2015 +0200

        Adds basic ioctl implementation

         * goal is to eliminate as many syscalls as possible
         * current commands: alloc, free, copyto, copyfrom, copyfree
         * copyfree is copyfrom and free in one command
         * copyto is meant to allocate if necessary, effectively removing alloc
           and free calls for most common cases
         * ioctl allows to pass more than 64bit, thus the id and dma_addr_t can
           be passed to user space in one syscall

    commit d5f321fb2e3cf26beca9f7d371fef4c6c81eae56
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 17:09:56 2015 +0200

        Adds timestamp and thread id to logs

         * log messages now contain timestamp (via clock_gettime) and thread id
           (via syscall gettid) to correlate the messages
         * added better logging at several places over libtpc
         * added better logging in Zynq platform
         * added start and exit messages for Zynq and baseline

    commit a3a5e1d97428db42acd90eb6ee75384bbd94e2f0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 14:14:38 2015 +0200

        Fixes g++ warnings in platform_logging.h

    commit c017352e05ca51363ff8cc62f40a62eb2ead7d35
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 14:13:58 2015 +0200

        Updates VC709 platform

    commit 803f8c4a5a2f2bbd71f8516e4bead13db51ca7d4
    Merge: f5b94a9 0151a99
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 13:55:43 2015 +0200

        Merge remote-tracking branch 'origin/dc_irq_reload'

    commit f5b94a9807b4961b20c044b178ab148a1270b755
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 11:49:41 2015 +0200

        Added threaded logging (libplatform)

         * added the same mechanism as for libtpc
         * cleaned up the CMakeLists.txt files
         * added automatic link to last built libs
         * moved gen_X datastructures to global common
         * re-organized DPI libs into separate CMake project "dpi"
         * cleaned up Platform errors and logging, too

    commit 38577fe00c627a4f44424f5e85736306ae0f5a5d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 09:03:46 2015 +0200

        Adds udev rules for Zynq devices

    commit ff8f95002e66c4d9421eb16b68645997ae21b208
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 09:00:50 2015 +0200

        Adds the 'precision_counter' Verilog kernel

         * cycle accurate delay kernel in Verilog

    commit 0ece00ec2e49f66ff93c0550114ee0a754dce7eb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 08:58:50 2015 +0200

        Adds TPC++ API 1.1 header

    commit ac6327692521bf3756fbe025b584efbe99335284
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 08:57:57 2015 +0200

        Added cmake toolchain def for crosstool compiler

    commit 27e2a4a48359425cee74e8a5e06dc1ed69d90b05
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 08:48:11 2015 +0200

        Updates .gitignore

    commit 0b288ae8d3446cf46af29b89abf918fc325d9226
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 08:47:46 2015 +0200

        Adds missing test files for inline compositions

    commit 95ccb13927766cc40ca9a1425507f079c5c9c457
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 08:39:40 2015 +0200

        Updates examples/arraysum to TPC API 1.1

    commit 14ada99e2077070a5f03e375a04b68de24b4d2db
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 22 08:36:08 2015 +0200

        Updates platform/tests to PAPI 1.1

    commit 7b139f1f2bd78477e11e576af52cf589cdc7fc59
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 21 13:17:04 2015 +0200

        Adds throttled logging in a separate thread (libtpc)

         * tpc_log only enqueues in lock-free log queue (no direct output)
         * libtpc now hides internals more cleanly (e.g., logging level)
         * tpc_log is always called (no macro elimination), but overhead is
           neglible
         * messages are pre-allocated on lock-free stack, but allocated on need
         * queue is emptied by separate log thread, which is throttled
           (currently: 10 logs / 100ms)
         * log format has changed a little bit
         * bad: vsnprintf must still be performed by caller (no other solution)
         * cleaned up header, tpc_logging.h is now the correct header to use
           (no more tpc_logging_levels.h)

    commit 50a469aa6c5ad84117245a77e4f699a4a9a74765
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 21 17:28:41 2015 +0200

        Shortens log text even more

    commit fbc583d22f536e01ad0372556c0969ee3db1eb80
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 21 16:57:24 2015 +0200

        Simplifies logging benchmark to reduce length of output

    commit 98b9a7b5373d78cb3ebe73eb2868b6a51ed0e4da
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 21 16:51:51 2015 +0200

        Fixes bug in tpc_strerror

    commit 3df44f0ce8239909b4b6c2e4dd271e3014ed8b2d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 21 13:35:43 2015 +0200

        Uses appropriate high-precision clock instead of gettimeofday

    commit bf8de04afb9dbe22930d247e2e15b61b18ef51da
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 20 10:56:31 2015 +0200

        Adds logging benchmark to measure performance

         * logs large random messages on several threads
         * measures overall throughput
         * current results are a little bit strange:
            DEBUG=-1:  223214 /  27901 logs/s
            DEBUG= 0: 1052630 / 131578 logs/s
            RELEASE :  781250 /  97656 logs/s
           possibly due to contention on atomics?
         * logging reduces performance by ~4.7x - not so terrible, actually

    commit 0151a99ee06c3cbd448c21828311adc1e0553e62
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Mon Oct 19 17:32:16 2015 +0200

        Moved magic id check to driver code

    commit 59c8b34dcb8f83581fc1e8878a31f9d530feeb82
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Mon Oct 19 17:18:16 2015 +0200

        Wrong name mangeling

    commit 5a50c0f08d158fe1a94a3dc65664abef24631b41
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Mon Oct 19 17:04:28 2015 +0200

        Implementation of special base addresses

    commit 2dcfd80c6307e786c093875d28d18001f4d76b36
    Merge: 4284c0b 8f6bf3f
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Mon Oct 19 16:54:01 2015 +0200

        Manual merge of confilct

    commit 8f6bf3fb089035f485482496daf703ae927d95bd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 19 13:39:08 2015 +0200

        Fixes Platform API calls in VC709 Platform

    commit 61f3fcb85f8dd9c3d80d0769d56ad4f02af1d46f
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Mon Oct 12 18:15:56 2015 +0200

        Enhanced version of script

    commit e362dc0d1273e79a29b61ee9071e650c43af403d
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Tue Oct 6 16:03:45 2015 +0200

        First version of hotplug-script..pathes might not be correct

    commit 153e5a0377fc0231a3665d7bdf26c10e4b228fd4
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Tue Oct 6 16:01:29 2015 +0200

        Now driver allocates 1 user char-device for every Xilinx Intc

    commit 4b284139ffdb4790b93292f11b17a5f2f552d8ae
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Tue Oct 6 15:59:32 2015 +0200

        Dynamic loading of irq related char-devices

    commit 73627df46ffedb0d49d6eb11b416963ce2dcab46
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 14 16:42:56 2015 +0200

        Upgrades both TPC and Platform API to 1.1

         * version checks at runtime to match header + lib
         * added well-defined flag types in (almost) all calls
         * several minor improvements all over the place
         * several incompatible changes in signatures
         * updated all platforms and architectures

    commit 1ad46f991a5c723f02a0ef2fa6c88caa217fa609
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 14 16:31:14 2015 +0200

        Fixes bug in Composition

         * only filename of compo files should be used as part of path

    commit 4284c0b1df18d8a1b970529f62279f8843cdcb42
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Mon Oct 12 18:15:56 2015 +0200

        Enhanced version of script

    commit 7cf05c7de9adf09fc9dfa33b84b213547bee6eb3
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Tue Oct 6 16:03:45 2015 +0200

        First version of hotplug-script..pathes might not be correct

    commit 52488d215ff6b5d3fa1218cdcf78bda9dd50974b
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Tue Oct 6 16:01:29 2015 +0200

        Now driver allocates 1 user char-device for every Xilinx Intc

    commit a2aa0e2a560cbd9995e27ea06353ad2e6bed1b15
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Tue Oct 6 15:59:32 2015 +0200

        Dynamic loading of irq related char-devices

    commit 1b692acf3dbd4c09a07abe30f26847adebbc8c8c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 6 15:39:11 2015 +0200

        Fixes typo in design.master.tcl.template

    commit 2df636f7c4baf5dcc6036a32ea1274818d684c4f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 6 15:38:08 2015 +0200

        Fixes duplicate IP warnings for Vivado

         * eliminated useless copies of IP defs
         * less than ideal for out-of-flow kernels (need to fix sometime)

    commit 87787799e8f2c70caeeb8d4046e3f212ad97fa50
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 6 14:07:14 2015 +0200

        Patches newer gcc warnings in Zynq LKM

    commit b50d107e36b4c9b237c41e607dbde220f2ccf70d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 5 14:56:36 2015 +0200

        Fixes static library build for 'baseline'

    commit 4da040495e0e89da319261506db2c3e8d127ca64
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 5 14:56:17 2015 +0200

        Fixes build error in Arch logging

    commit a6bef2ac19acb4e5712e54ce0967f684ed24df5e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 5 14:55:20 2015 +0200

        Fixes missing init check in platform_slots

    commit ab3c5aca5b12c3f27289d5c7ed0a47fba7bf9fbf
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 5 14:53:29 2015 +0200

        Improves Zynq platform

         * fixes build error in logging
         * improves logging during init (filenames)
         * CMake: gathers DPI-related stuff in optional target 'dpi'

    commit 9bcda2d4e919316c6f713d0ece6df68b1b12520f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Oct 2 15:39:55 2015 +0200

        Extends vc709 platform to 128 slots

    commit 09b121dd23aa7659255952c5df2f55b480f14c9b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 30 18:28:56 2015 +0200

        Extends zynq base to 128 PEs + improvements

         * clean up in the #defines - zynq_platform.h as central point
         * ctl addr checks in single function
         * support for up to 4 interrupt controllers

    commit e2ba99358c6f8d7d6be00bbe8cf610499f6984f4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 30 18:27:39 2015 +0200

        Extends zedboard platform to 128 PEs

    commit 2a4c0f55c1fb3f6d828d5e2f480820a11654b73f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 30 18:26:34 2015 +0200

        Extends 'platform-slots' test program to 128 PEs

    commit 4590687e599d5bb31242000758368e34c151fe17
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 30 18:25:55 2015 +0200

        Extends baseline Architecture to 128 PEs

    commit e051a23c9803b864a070ab418225d555cc95f316
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 29 16:30:20 2015 +0200

        Extends TPC Status Core to 128 slots max

    commit 8d5a395f8757b7e45087dec524ecd2258ce57d20
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Sep 28 14:03:30 2015 +0200

        Removes RPATH from TPC and Platform libs

    commit e4cc677ba0d358e8607c2fc27a8df5abac0a9c96
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Sep 28 13:56:50 2015 +0200

        Fixes bugs concerning inline compositions

         * 'id' property replaces composition file name for paths
         * hash on composition in inline case, prefixed by '0x'
         * descPath is now hidden to avoid further use

    commit e8d680065f3cfdb38b280535da349818fff7ec7b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 25 11:10:28 2015 +0200

        Adds inline composition property to Configurations

    commit 809fff0672ab81758412632e5f1982c176b7076c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 22 16:42:56 2015 +0200

        Enables -O3 for Zynq module

    commit 51957bcdb59b9bc802271491e29d8031264ce0f2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 22 16:42:14 2015 +0200

        Improves status core address handling

    commit a3e46239400a84e9be58d6b288f0a7710452cad7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 22 16:40:06 2015 +0200

        Improves TPC logging for status core

    commit 69d31e39aebf1eb890931f3b91ca4679fcad7f95
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 22 16:39:17 2015 +0200

        Fixes bug in tpc_functions.c

         * need to check tpc_init return value before initializing the INTCs

    commit 210ab7a9b89ef3a52d7eee9aa8ca802133b1c689
    Merge: e146c65 30719e2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 22 16:06:05 2015 +0200

        Merge branch 'date-2016'

    commit 30719e27a51b1c3fe534205df0f85f8b4d57b46a
    Merge: 92b5d47 eac1ed4
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 22 15:53:01 2015 +0200

        Merge branch 'date-2016' of https://bitbucket.org/jkorinth/rcu into date-2016

    commit 92b5d47eb64d2278d327bec2a04c97975efcde25
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 22 15:50:42 2015 +0200

        Re-enables 64 slots on zedboard

    commit e146c65e5998781e0d1f3c99d8857b50974a98bc
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 22 15:40:35 2015 +0200

        Fixes kernel.description for 'arraysum'

    commit 8980cb885858dbf8c4e21e578366542f977e5c40
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 22 15:40:08 2015 +0200

        Fixes kernel.description for 'arrayinit'

    commit eac1ed4fe60ce6677af885a23338b29784e67c4c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 18 18:21:22 2015 +0200

        Last minute changes DATE'16

         * changed config script
         * bugfix in GenerateThreadpool
         * platform/zynq: removed unusable frequencies

    commit 9dd7aaf73f5f59150ca58377748fb61ca48fe6ac
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 18 18:13:01 2015 +0200

        kernel/date_sobel: improved timers, 1024 jobs, smaller sim

    commit 708728dbdab442418102ce583c3b751df242cf76
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 18 18:11:15 2015 +0200

        platform/zynq: upgrades to 2015 synth/impl

         * zedboard: only usable frequencies

    commit 6af008b646345e542d6631d6d3d7b7135da0116f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Sep 14 10:10:04 2015 +0200

        Fixes GenerateThreadpool, re-enables Vivado execution

    commit 58add0f4cdb8224e4625edcb69e8b154fbf40e42
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Sep 14 10:03:22 2015 +0200

        kernel/date_sobel

         * new real-world test program based on Sobel kernel for eval
         * reduced image size to 128x128
         * enabled full implementation (check_bounds)

    commit 3fc95ffb3cf8a9fc8fa5a9249658caaf3a525dee
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Sep 14 10:01:24 2015 +0200

        Platforms

         * more frequencies for zedboard
         * InterruptLatency for zedboard, zynq, vc709

    commit 755a2a78c3582caaba5b79e849bc207fdc19d91b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Sep 14 10:00:12 2015 +0200

        Maximizes debug output

    commit 7b4d78eb5f463ecb5f436187dacfec98aba189e5
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Sep 14 09:58:08 2015 +0200

        Fixes area estimation for GenerateThreadpool

         * area estimation based only on Slice LUTs (found forum entry
           explaining this in detail)
         * added isFeasible to AreaEstimate to check resource bounds
         * modified DSE mode to use additional checks on compositions

    commit 7ef271028c31e166631764585f0fa4a9fd9af853
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Sep 14 09:56:31 2015 +0200

        Improves generate_configs, better forking

    commit fa2d01e18fd2b3e800f3b543199c288b581b71de
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sat Sep 12 10:58:11 2015 +0200

        GenerateThreadpool: added explicit logfile support

         * Configuration: new property 'logFile' - path to logfile
         * logfile output will not use terminal colors (easier to read than
           tee'd output)
         * 'logFile' is optional
         * integrated in PrettyPrinter and ColorConsoleAppender

    commit b44d870f25773a1aec2850b21e6fb0155ed9e946
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 8 19:07:29 2015 +0200

        DATE'16: added script to generate configurations

    commit 15da7f5b932433c0713a06fab92946c3bf54d978
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 8 19:02:34 2015 +0200

        examples: extra flag for FF requirement

    commit bcf29cdac21d1db9f57254de90e8d800cc02136e
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 8 18:56:57 2015 +0200

        TPC: automatic DSE

         * added new automatic design space exploration ("full")
         * design space is spanned via max freq + max area and then evaluated
           based on a simple throughput metric
         * TPC automatically attempts bitstream generation in order of metric,
           until working config/freq pair is found
         * takes long, but seems very useful

    commit b54ecfccde3b14a45d4a083746d5880a15ad4c72
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 8 18:55:45 2015 +0200

        TPC: misc stuff

         * using new auto freq in HLS generate
         * extended pretty print for config
         * moved several shared methods from AnalyzeComposition to GenerateCommon

    commit f21c3d925c142566f552ec500d502fd85873bba4
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 8 18:52:46 2015 +0200

        TPC: Platforms zedboard, zynq, vc709

         * added utilization report which summarizes only the PEs

    commit 20df2f1101723022a972ca47bd94c9282b58384d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 8 18:51:10 2015 +0200

        TPC: Configuration

         * added new property: DesignSpaceExploration (None, Freq, Full)
         * can trigger DSE in GenerateThreadpool

    commit 86e8c628e47aff47fbc8e964a272dbe4070102ba
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 8 18:48:23 2015 +0200

        TPC: Platform

         * new mandatory property: SlotCount
         * new optional properties: InterruptLatency, MinimalStartLatency
         * fixed testcases accordingly

    commit d8335f5ca3fa65de6fb1f1810bf647470e24a6ca
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 8 18:40:06 2015 +0200

        TPC: removed DSPs from max area utilization calc

    commit 8bbbb20a2befb5dbc75dcb5b8956e996a954cb34
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 4 14:43:00 2015 +0200

        common/common.tcl: fixed get_design_frequency

    commit 2ebb8d9090cf83b2ba06707e5b8d01a9cd06e080
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 4 14:40:06 2015 +0200

        ConfigurationBuilder: default directories

         * default directories for platform, arch and kernel are now based in
           the TPC root, instead of relative to the description file

    commit 1e9053de31ac6c50d5e16462fde8f6b126bec361
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 4 14:37:18 2015 +0200

        TPC: automatic frequency feature

         * new feature: when TPC_FREQ=auto or not set, TPC will now
           automatically iterate over all "supportedFrequencies" until a working
           design can be built (or list is exhausted)
         * deactivated output from Vivado/Vivado HLS processes; instead giving a
           message pointing to the exact location of the logfile
         * several improvements for the batch mode (e.g., global HLS phase)

    commit 646e59709eeffdf68007d538e5e435e90123dea9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 4 14:32:00 2015 +0200

        GenerateCommon: added homeDir property

    commit 912ed6557c45b32bd98e02df6606733c73b72da1
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 4 14:30:21 2015 +0200

        analyze: checking overal clock frequency

    commit e6d1bea3e2f510f23a9cf3b03dd0ef888ea9bb54
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 4 08:37:36 2015 +0200

        Platform: new field 'SupportedFrequencies'

    commit 6c2f682354c1c24b001bb66fd2fea48061913b0c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 4 07:52:51 2015 +0200

        kernel/date_sobel: new Sobel kernel for DATE'15

    commit cbe7a4a15227331120a6a1002d8064c08be494ac
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 28 10:07:43 2015 +0200

        GenerateThreadpool: -notrace switch for imports

    commit 4a78817629cee6b4d4366afb44c7b0434e6aef6b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 28 10:05:58 2015 +0200

        platform/zynq: removed some debug output

    commit c2bfc7be4de2b71d383c5738a49f4ee7bd8b1b19
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 28 10:04:45 2015 +0200

        platform/zedboard:

         * deactivated 'sim' generate mode with message
         * removed some debug output

    commit 3e68018b94f61c8895759c1a044efa5da7e49ffa
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 28 10:03:49 2015 +0200

        TPC: improved master templates

         * HLS: simulation with optimization
         * TPC: -notrace switch on includes

    commit 50251ef42cfa0f13531cf0f15307ed76642b2cbb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 28 09:50:23 2015 +0200

        examples/benchmark-latency

         * rewrote as C++ version
         * easier to read and maintain now

    commit fef93a58012626d00cc5398e86ea9a7078d3b77e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 28 09:48:18 2015 +0200

        examples/benchmark-mem++

         * rewrote benchmark; uses larger block of random data
         * block chunks are cycled to make it less cache-friendly
         * reduces throughput significantly (at least for VC709)

    commit 7efcaea250dabd7ff839eac6807bd175c6623ae3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 21 14:18:48 2015 +0200

        TPC API: added function to retrieve job arg

    commit 87f8014b81f8ae6bd109c515b24c1e352c9ef1b7
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Aug 19 17:52:24 2015 +0200

        TPC: added TPC_HOME checks; improved error messages

    commit 90d75b1bfc4f549ccfcb948db7fbdeaefd502695
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 17 18:37:05 2015 +0200

        platform/zynq: module

         * added device file for status to support proper mmapping
         * increased timeout to 3 x 10s
         * 'release' target removes _all_ logging / kprints

    commit c34af5c97b5abc3d1597ccb28111df092bf502c3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 17 18:28:25 2015 +0200

        platform/vc709

         * 0x0050_0000 is not in the user-accessible space; hence had to move
           the status core _behind_ user cores to 0x0250_0000

    commit c8241b0c29ad78ec889adf6212f02a048d1d4465
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 17 18:27:33 2015 +0200

        platform/common: NDEBUG disables _all_ logging

    commit 869fc389cbf1caa9234c9a941d428b7524eade20
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 17 18:26:03 2015 +0200

        arch/common

         * NDEBUG disables _all_ logging (including errors)
         * bugfix in functions: need to NULL unused slots
         * status: log contained superfluous newlines

    commit 3e9a28a9d290889ab059dc06c0817d3fee3f7947
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 14 19:27:45 2015 +0200

        platform/vc709: bugfix in optional cache wiring

    commit 613deffe0fcdb8e5a2fe454c090a2b97a8bed0db
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 14 16:05:56 2015 +0200

        TPC: config console args bugfix for overrides

    commit c63cdb1b00a8c33c324ebde86f41c5ea51a03edf
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 14 15:00:25 2015 +0200

        GenerateThreadpool/HLS: fixed timeouts

         * scala timeouts did not kill the spawned processes
         * many attempts to fix that, but to no avail
         * had to resort to 'timeout' UNIX utility

    commit d9dd31251325beac385ff066949edda7420e8dcb
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 14 14:44:15 2015 +0200

        platform/vc709: no sim support, aborting wrong generate runs

    commit 09d0aa4474a66174d02e7e0b54c83b94b49350cd
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 14 09:43:54 2015 +0200

        kernel/countdown: ID = 14

    commit 8a22f1b58c4ef1bd4c7684f87d2c40b3d7e031f3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 14 09:42:18 2015 +0200

        platform/vc709: separated DDR / design clocks

         * support for variable target frequencies via DDR clock gen
         * design is driven by separate clock now
         * rebuilt many connections accordingly

    commit 58557afa835069a3f4efa63786854427350ef8e2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Aug 13 13:13:22 2015 +0200

        kernel/sudoku

         * optimized safe method; better fit for FPGA
         * optimized HLS directives, improvement by ~3.5x

    commit dd4c5a017c28f257ba9a30c641d6dcb3f8b2666f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Aug 13 13:10:46 2015 +0200

        common/common.tcl: bugfix in TPC status

         * major bug: ids were always assigned to slot 0

    commit 894f16c950a258e0ed9eeefdd2ca83d5f86d4c40
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Aug 12 14:37:16 2015 +0200

        common/common.tcl, platform/vc709

         * common.tcl: added new methods to simplify feature queries
         * common.tcl: TPC status core automatically populated
         * common.tcl: bugfixes
         * vc709: added TPC status core at 0x0050_0000

    commit ef2216d80e609462f773efc55f9639e6dc09d708
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Aug 12 11:16:19 2015 +0200

        Architectures: TPC Status core

         * added common source code for new TPC status core usage
         * tpc_functions code now relies on tpc_status instead of old
           environment variable TPC_COMPOSITION
         * checks for magic number to identify TPC bitstreams at start
         * new logging level + corresponding error code

    commit 802f00b1ad753e460e1cd61f467af994b0a3e5ce
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Aug 12 11:13:01 2015 +0200

        TPC: mandatory kernel id

         * added mandatory Id field in kernel descriptions
         * used to populate corresponding dict in Tcl, which can then be used by
           Platforms to populate the new TPC status core
         * updated Kernel-related regression tests accordingly

    commit c0f9709c13e7d2bc22f4e12c9dfaa5453705c0f4
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Aug 12 10:21:22 2015 +0200

        Platform API: platform_address_get_special_base

         * added new Platform API call to query address of fixed infrastructure
           cores, such as the new status core
         * implemented in Zynq (HW+Sim): 0x7777_0000
         * implemented in VC709 (HW): 0x0050_0000

    commit 282cc9aa6290235b2fd15ee433cf0bb899fef259
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Aug 11 18:11:38 2015 +0200

        platform/zedboard: integrated status core

    commit 51488582c37c69c978269ce9388dffd13005b3e6
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Aug 11 17:59:13 2015 +0200

        platform/zynq: integrated status core

    commit bff31a5456c25ce343af79b38b97a064d0cafc0d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Aug 11 17:55:42 2015 +0200

        TPC Status IP Core: initial version

         * simple AXIlite register file: 0x0 has magic number
         * other addresses contain kernel id
         * nothing else yet, possibly perf counters later

    commit c467437c537a60d12c9caee7ec267fbe78898132
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Aug 11 08:50:52 2015 +0200

        arch: switch to manual AXILite register map layout

         * automatic address layout by Vivado HLS makes it difficult to predict
           the AXILite address of a given kernel argument; manual layout was
           possible, but used to crash in earlier version (2013-14.x)
         * switched to manual layout via directives (works now): 0x20 is first
           arg (for baseline), 0x10 offset for each at the moment, 0x10 is
           return (or nothing if kernel is void)
         * kernel.description: unified "Arguments", each arg with name and
           passing convention (default: by value); JSON format made that change
           very easy => order of argument can now be preserved
         * adapted libtpc for baseline accordingly
         * adapted current kernel.description files

    commit 3e5281105c5a389517932341cd059f1dbcc5fa79
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 10 16:45:55 2015 +0200

        platform/vc709: added CMake build

    commit 398a8b94d7c4ae141dbe65afd8a5805211ae628a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 10 16:44:42 2015 +0200

        GenerateThreadpool: fixed kernel and zip finding, simulation

    commit 36e687b224660e357884a5521b392842d5576a38
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 10 16:43:57 2015 +0200

        analyze: added kernel target frequency check and warning

    commit 6e06cfa15766c1e461229286fbe9182fdd97709a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 10 16:42:49 2015 +0200

        arch/baseline

         * bugfix: structs require data pack directive, added to refarg
         * demoted required CMake to 2.6 (from 2.7)

    commit 0c202bbd2ae52571b39698010380bda2fd72ae04
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 10 16:41:39 2015 +0200

        arch/common

         * fixed bug in function IRQ setup (would trigger IRQ at start)
         * scheduler: added some debug messages

    commit 2fb6e886648b764a9f1e9d7becad191efe5c0fce
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 10 16:39:09 2015 +0200

        platform/zynq

         * re-enabled simulation (harness, testbench, API) - works again
         * bugfix in platform DPI client lib
         * updated CMake (downgraded required version to 2.6)

    commit bc458482fca948f27a56fa5db782373def0c2439
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 10 16:37:17 2015 +0200

        Platform API: fixed platform_res_t width problem

    commit f152f795077b3c226981303ed87d4a68800b5721
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Aug 9 17:39:52 2015 +0200

        Features: regression tests

         * added basic regression tests for Configurations with Features
         * currently only PlatformFeatures are tested, but ArchitectureFeatures
           should work identically at the moment

    commit bc984165defcfcfb8650112e4725950c189f47a2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Aug 9 17:03:50 2015 +0200

        TPC: added some missing inline doc

    commit cf2f1e976352e31799fa4ff26eed17ae44bc8c49
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Aug 9 16:12:31 2015 +0200

        platform/vc709: Cache, LED features

         * new feature: Cache configures L2 (currently Xilinx System Cache)
         * supported cache sizes: 32K, 64K, 128K, 256K, 512K
         * supported associativities: 2, 4
         * new feature: LED enables/disables VC709 status LED connection

    commit 1cb16894c5d113cea3c653f80d4033ad68685dae
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Aug 9 16:12:06 2015 +0200

        common/common.tcl: support for arch/platform features

    commit f1ba153a9a303528b2b4cf7926a27369677ec1a6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Aug 9 14:37:40 2015 +0200

        Removed arch 'chisel-basic': will restart on branch

    commit a37f30f290ba0ea8ba7f4d2a7035e9b414a19e2f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Aug 9 14:17:14 2015 +0200

        JSON: minor bugfixes in sbt test

    commit e5ef5252cd9218ac1db03cc2444a88bad9af4173
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Aug 9 14:00:16 2015 +0200

        JSON: forgot to check in test files

    commit c499c33d02456563dfebc1c937a8d24669a756ad
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Aug 9 13:56:39 2015 +0200

        JSON: updated some more description files

    commit 41ef10d9188f257dab77c23aed340c16a137b9a7
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Aug 9 13:51:19 2015 +0200

        JSON Support

         * added full JSON support: all configuration files moved to JSON
           format, with parsing validation, refactorings and clean-up.
         * rewrote Description classes entirely: package descriptions
         * removed legacy code
         * re-enabled ScalaTest - sbt test provides automatic regression testing
           for the JSON files
         * examples given in json-examples (used in sbt test)

    commit 9d7b9742f1e6def1315511af8ae0072051a57e78
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 31 20:22:48 2015 +0200

        Description files: migrated to JSON format

         * better fit for REPARA
         * useful for new 'features': need to be configured via structured data,
           JSON provides a good notation for this
         * using JSON package from Play Framework (took some time to setup and
           understand, but is quite elegant now)
         * easier and more thorough validation
         * DOES NOT WORK YET: need to check & unify file name expansions

    commit cf1b77ea1c5ec2ae1f5236cc87a46f5a993a9519
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 31 19:59:53 2015 +0200

        removed deprecated Scala code

    commit 1a69a615c7a241cb432c594e22b2b802ad852796
    Merge: 67ab467 2f6f01c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 31 09:36:48 2015 +0200

        Merge branch 'master' of https://bitbucket.org/jkorinth/rcu

    commit 67ab467a0c488563f8daf8846df98b3a3ea3b473
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 31 09:36:10 2015 +0200

        platforms + analyze: added target utilization for estimation

    commit 2f6f01c1f803c07e17add4dc780e2e24fe049d01
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 18:10:39 2015 +0200

        examples/benchmark-mem: bugfix in time calc fr R+W

    commit 7e9701c85a6549fdb6ecf9b8182bcdc82b971f40
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 18:10:19 2015 +0200

        examples: minor fixes / updates

    commit 0e44d8e3181738ae135bab32aafd3ee7e5e8cce7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 17:54:24 2015 +0200

        arch/baseline: bugfix in irq reset; increased to 64 slots

    commit 8bbb17d3b177f4c4da3e0582e55493675d9fdb96
    Author: David de la Chevallerie <dc@merry.esa.informatik.tu-darmstadt.de>
    Date:   Thu Jul 30 17:00:05 2015 +0200

        Added support for larger memory requests and reading/writing multiple registers at one

    commit adb56b22f5cda0f022493f676451ad9f4cd5d8cf
    Merge: 76b3c77 80e18c6
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 16:07:44 2015 +0200

        Merge branch 'master' of https://bitbucket.org/jkorinth/rcu

    commit 76b3c77d76944dabce3e5b50af623c0d0898b7d3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 16:06:49 2015 +0200

        common/ip/GP_LED: added missing constraints file

    commit 213e27adfd08dfd88b5b4ea532aa805643d0ad94
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 16:06:00 2015 +0200

        platform/vc709

         * added LED core to flash lightielights
         * fixed minor bugs in Tcl

    commit e5bd736d9ed1ebed0886f59d106bd50fefa2d4af
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 16:04:19 2015 +0200

        arch/baseline: bugfix in user ip naming

    commit 80e18c65e48d08cd1bd468edaa560ca2c7c598ac
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 15:47:14 2015 +0200

        platform/vc709: libplatform logging bugfix

    commit eea5c33763fc23313e02738c6ee7254dbfe30b17
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 11:51:21 2015 +0200

        tpc_functions: ack'ing existing interrupts

    commit 443d2e298d733f03b0d8907b2d980c69b143d603
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 11:50:27 2015 +0200

        arch/baseline: platform_logging warnings suppressed

    commit fe30203dff379b9e26e11dcac13598549c304b7c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 11:48:33 2015 +0200

        Platform API

         * several changes for compatibility with C++
         * logging implementation still sub-par, needs rework
         * some bugs fixed concerning namespaces
         * new logging level DMA

    commit 7dc546d44d2dfd43424b88b5d3511cb1b0adb2dd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 11:45:14 2015 +0200

        platform/tests: updated for use with VC709

    commit 5d66b156d6513dda76011e059705a2285ea66445
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 30 11:26:37 2015 +0200

        platform/VC709: kernel module, initial version (DC)

    commit b0cd84b079c8bb3e83a3c2dccaea8d38a1155109
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jul 29 14:42:29 2015 +0200

        platform/vc709: VC709 platform Tcl (first working)

    commit 6bd6f8b63c60981dac7373bba5857c66f47a3620
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jul 29 14:39:13 2015 +0200

        common: updated PCIe interrupt controller (DC)

    commit 7ba637e886df5fe69cf5be7eebb217e4e5493210
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jul 29 14:38:23 2015 +0200

        arch/baseline: fixed naming & irq ordering of IPs

    commit 19c5eb1c7003f717d709afb642591a58dd36a717
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 24 13:38:13 2015 +0200

        platform/vc709

         * added packet FIFOs for mem ICs and toward PCIe (crucial for perf)
         * fixed XDC insertion for the DMA engine (hackish!)
         * added 256KB L2-Cache between MIG and masters (including DMA)

    commit 0fb70334d201704bb38e72af003187ca1ec790e8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 23 18:06:46 2015 +0200

        arch/baseline

         * bugfix: 'variable' instead of 'global'
         * shouldn't have worked at all, strange

    commit ff92ac5a2793ab6aba211cd33bf7a0d334545da8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 23 18:00:29 2015 +0200

        platform/vc709

         * new custom IP: mm_to_lite - strips a full AXI-MM master signal to
           AXILite; better than full conversion, since bursts etc. are ignored
         * should work for accesses from the CPU, which should not be able to
           burst, and eases timing closure
         * inserted between PCIe and user logic

    commit 8e1b1fd9581c038fa12ab7586bec6c7784289388
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 23 11:24:23 2015 +0200

        examples/benchmark-mem: CMake build

    commit 46d93ef71f4355a25c57a8bbe1510d9b34ab9ab6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 23 11:17:32 2015 +0200

        examples/benchmark-alloc-dealloc: CMake build

    commit bd032a226e3749016540a53880a90a149fd0bd7e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 23 11:10:32 2015 +0200

        examples/arraysum: CMake build

    commit 7cdf7f149377f3700d256e371e29c6b87a24e597
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 23 11:09:33 2015 +0200

        examples/arrayinit: CMake build

    commit 8a4cec86e0153c362c4ee9ccde681f324f6ce8fd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 23 11:08:27 2015 +0200

        examples/warraw: CMake build

    commit 9c09952b5d3753d7778a134fb4a3322a468adcb3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jul 23 10:34:20 2015 +0200

        Major Tcl refactoring

         * now using namespaces (tpc::, arch::, platform::)
         * all IP instantiation moved to common.tcl
         * fixed all occurrences in existing Platform scripts and Scala code

    commit 886da9d9ff9fb225084b29683f64977b33737642
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jul 22 13:50:48 2015 +0200

        platform/zynq

         * merged improvements from zedboard

    commit 36c61b20afc7446ecda60e9e4842c19e0a63eaab
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jul 22 13:48:56 2015 +0200

        kernel/sobel: LegUp sobel example (naive impl)

    commit f9f426125f69f60c9e1a6e3f301800ac186fdf42
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jul 22 10:56:02 2015 +0200

        platform/VC709: fixed address map

    commit 41e7a1492816875d4a06b098a5ce857d3568afe7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jul 21 10:25:09 2015 +0200

        platform/vc709

         * updated IP cores for 2015.2
         * updated (unnecessary) board preset

    commit cd2b917e9fb65ed0fce7f4db91b9b74114624a0b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Jul 20 17:30:37 2015 +0200

        platform/zynq: libplatforms support for 64 slots

    commit cc7cb10ff82ba92c922f0aa65a4c5c61c165fd0d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Jul 20 16:01:46 2015 +0200

        Platform: board preset property

         * implemented board preset as Platform property; env var only fallback
         * mandatory key in 'BoardPreset' in platform.descriptions
         * added defaults for zynq, zedboard Platforms

    commit ca19a4447933a787085c59ba60885b496d648746
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Jul 20 14:16:08 2015 +0200

        platform/zedboard

         * common.tcl: re-enabled regslices in ICs + regslices in baseline mem
         * bugfix: timing closure easier with OLED @10 MHz
         * bugfix: address mapping of interrupt controllers re-enabled

    commit fd34dea71c6d4f1efff3d9b19d36f1deb512698d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 17 16:26:35 2015 +0200

        arch/baseline

         * extended baseline design: now supports 64 cores
         * M00_AXI, MO1_AXI, M02_AXI are ports of Threadpool
         * M00_AXI: 1-32 masters, M01_AXI: 1-24 masters, M02_AXI: 1-8 masters
         * this helps matching HP0, HP1 and ACP resp.
         * masters are distributed evenly across the interfaces to maximize
           utilization of the hard IP
         * address mapping had to be rewritten, not 100% functional
         * EXPERIMENTAL - further tests outstanding

    commit f842338049b1295645b433e91989bc8d0bcd543f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 17 16:21:42 2015 +0200

        platform/zedboard

         * bugfix: HP0/HP2 must be set to 64bit mode, or reads from HLS AXI-M
           interfaces have read errors on the second half of a 64bit word; the
           first half of the word appeared twice, e.g. when reading 0x4, leading
           to very subtle errors (took me ages and ILA to find out)
         * also had to deactivate M-side regslices in interconnects; apparently,
           activating them on both sides could lead to erroneous reads
         * improvement: FCLK1 frequency is now determined automatically based on
           FCLK0, the first frequency f with 1 <= f <= 10 MHz which is a divisor
           of FCLK0 is taken; note that the PLLs may not be able to generate
           this f, so users discretion is advised

    commit 548804ccd7c4ddbe2de358ef6b8346405906899a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 17 16:05:52 2015 +0200

        analyze: improved optimization speed & correctness

    commit 1627b3cbe8fbda8139327383693a8906aab12fb1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 17 14:34:50 2015 +0200

        TPC: new command 'analyze'

         * added analysis pass for Compositions: generates IP cores, estimates
           FPGA utilization and attempts to reach a utilization estimate between
           60-65%.
         * relative weight of kernels stays the same (approx.)
         * should probably be used automatically in the future

    commit 472f21b26499d31d07c50302fb7901795f979afe
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 17 14:33:08 2015 +0200

        GenerateHLS: using correct PART now

    commit 05a88133a5596df7e8e72dd64d64243537756907
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Jul 13 15:53:43 2015 +0200

        zedboard_oled: fixed parameters for FCLK1 @ 12.5MHz

    commit 00b08e7ab0140aaee1d1e8fb421412a09ebff76c
    Merge: 6ab8c20 e08b77d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jul 13 15:47:08 2015 +0200

        Merge branch 'zedboard_oled' of https://bitbucket.org/jkorinth/rcu

    commit 6ab8c2010da4e3444059fa9191aa0572d0b0ff38
    Merge: e1a8032 2a4f869
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jul 13 15:41:29 2015 +0200

        Merge branch 'master' of https://bitbucket.org/jkorinth/rcu

    commit e1a803240bee78666ab863bfde1ac16d94dee79a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jul 13 15:38:56 2015 +0200

        examples/benchmark-latency

         * new benchmark to plot latencies of job completion
         * TPC API and direct Platform API for comparison
         * configurable interval, sampling points, iterations

    commit e08b77df11a315e744f924e8996627be36a05141
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jul 13 09:09:05 2015 +0200

        zedboard_oled: made C_DELAY_1MS visible

    commit a76c7d79065ed29bb82559aa005e4b9d6ab82750
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 10 16:29:55 2015 +0200

        zedboard_oled: added synchronizer to ease cross-domain clocking

    commit f1a647f173d47535f9da353a6e9d4238a3347581
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 10 14:47:40 2015 +0200

        zedboard_oled: replaced old version with better, smaller implementation

    commit c080ec06e22865a5d92096efc8211abc5766306f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jul 10 14:47:17 2015 +0200

        zedboard_oled: updated old version

    commit ce413fe20d1275abebed3fcf80efc6da8225309d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jun 16 18:28:59 2015 +0200

        zedboard_oled

         * added oled_ctrl instance to design
         * fixed constraints
         * automatic connection of interrupt lines to inputs

    commit 2a4f8694dc450538b74141130b42ea8a32420c4e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jun 16 14:17:24 2015 +0200

        new IP core for OLED controller on zedboard

         * performance counters + visual representation

    commit 634540254297e3b7af993128666591f74a97c059
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jun 11 11:04:12 2015 +0200

        Description.scala

         * added INFO output: filename of description

    commit b8c9da24497516d0d482c4849b8f402598ca4d96
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jun 11 10:58:07 2015 +0200

        platform/vc709

         * fixed clocks: dual_dma s_axi_aclk should be PCIe clock, not the DDR
           clock; re-wrote connection of clocks and resets
         * increased msi_vector size in PCIe bridge to 8
         * added constant zero tie-offs for unused IRQ lines

    commit 3be9d6c8bcb5d60141668aa9acf515b70e92127d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jun 11 10:55:40 2015 +0200

        common/common.tcl

         * createInterconnect: most conservative setting for register slices
           (outer and auto) used by default
         * createConstant: added factory method for xlconstants

    commit 17df61392e7abfa6900fcbe8440d66e9eaa1dd16
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jun 11 10:53:36 2015 +0200

        common/ip/pcie_intr_ctrl

         * bugfix: off-by-one in IRQ_WIDTH loops

    commit c527cd9b74d106c674129e0fd4971432b39cdeb2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jun 2 19:30:06 2015 +0200

        kernel/sudoku: fixed MT code, async launches

    commit f2ba370ed135002615a70405d2f86cd3e6c7f7b0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jun 2 19:28:43 2015 +0200

        arch/baseline: TPC API implementation

         * added 'Functions' level
         * added some debug info for functions module

    commit 02406ef806a7d68364f0a72f9a742850916a491a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jun 2 19:27:44 2015 +0200

        arch/baseline: export of masters fixed

    commit e0b64f4e9febf34de1167a27dcedcaf7576616eb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jun 2 19:26:53 2015 +0200

        platform/zedboard: fixed platform design

    commit b7a1699f2339db0be12552e21ba16611aeefa7ca
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jun 2 19:26:02 2015 +0200

        platform/zynq: bugfix + stuff for L2 flush

    commit 892b22bc4c8a5ca0df11b058977e491420ee6cea
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jun 2 12:39:06 2015 +0200

        examples/sudoku: added missing directives file

    commit 0c46470adbc4c2b565f1647d9d5d1a2ba892a334
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jun 1 17:30:58 2015 +0200

        kernel/sudoku: improved version using local BRAM

    commit 1d91bae1c8d38d51c0118b00e829a3ce2f80d06c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jun 1 17:29:15 2015 +0200

        examples: fixed CMakeLists.txt for benchmark-cd and memcheck

    commit 998f1be91e27a028505f920e9811020985ca8780
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jun 1 17:26:48 2015 +0200

        sim_setup.sh fixed

    commit 5e7606f8a49940c57b1336f23d9c140de86ef6f9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jun 1 17:25:16 2015 +0200

        common/ip: new custom IP dir

         * dual-clocked DMA core (32/64bit)
         * GP_LED: led indicators for VC709 PCIe connection
         * pcie_intr_ctrl: MSI interrupt controller for VC709

    commit a73ae6f9299bd16812eb288920eb43bc2ad8e528
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jun 1 17:23:36 2015 +0200

        Platform zynq

         * now using HP0, HP2, HP1 for Threadpool (in this order)
         * easier to change host connection
         * several smaller updates and improvements

    commit 4d936153679002bb69e86f442139f2f40d5943a9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jun 1 17:17:32 2015 +0200

        Platform API: added some address functions, comments

    commit 32d0127050853c1f8327af2784995259b2e61820
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jun 1 17:17:01 2015 +0200

        new platform: zedboard

    commit fdeb8d9b08fd9ef24561c776d83432ade225265d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jun 1 17:15:25 2015 +0200

        baseline

         * added some logging
         * removed memory management (-> Platform API)
         * using hierarchical module "Threadpool" for more elegant design
         * replaced hard-coded magic constants by proper Platform API lookups

    commit 32d6ff4158791fcddb320b1809d8258708469e03
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jun 1 17:12:47 2015 +0200

        TPC common

         * basic logging facilities
         * logging in scheduler + some improvements
         * removed interrupt code from TPC (-> Platform API)

    commit aaa2ed0f55e7f8044cf7454eca5b88ba71a2645d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jun 1 17:10:34 2015 +0200

        VC709: first working draft for VC709 designs

    commit 47c8a06598cfb4ba421049d00f86d2cc777ebf5b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 28 18:06:30 2015 +0200

        arch/common: bugfixed version of gen_fixed_size_pool

    commit 5d20b42fc143cf846d938c34cb47d92002f9cacf
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 28 18:04:27 2015 +0200

        platform/zynq: Tcl improvements

         * fixed name of bitstream
         * generalized connection mechanism: now using GP0, ACP, GP1 in this
           order to connect masters
         * unified env vars to LIBPLATFORM_SERVERLIB

    commit 3c64e954072a13976a73801fb9a014c98a3fc8b8
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Apr 28 18:01:40 2015 +0200

        platform/zynq

         * removed old wait_for_irq routines (replaced by _event)
         * improved logging
         * fixed race condition in harness

    commit f176c6532dba247b4d7967e296a84303fa7ddcb3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 24 16:23:18 2015 +0200

        platform/common: fixed errors in platform_strerror

    commit 2e80868c456e81a5fafa4442dcab18e8cd829120
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 22 15:16:29 2015 +0200

        Fixed some path-related bugs.

    commit 6cc4a97e36a2b7f864071782015d18b0f6d0188b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 22 12:12:46 2015 +0200

        ZC706: fancontrol bugfix

    commit 41eba0e6483a1bdb9527ef3f899609771687bfab
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 22 12:03:40 2015 +0200

        platform_strerrors: now inline

    commit dd3564d519ab56ff31ebf201d8ae8faf41aff14b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 22 12:00:18 2015 +0200

        Fixed resolvers for ANTLR4, removed automatic dep building.

    commit 63d5a608c239ef051da60a086e3929e01eb25686
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 22 11:53:40 2015 +0200

        Removed MachSuite from repo.

    commit d69c0543a72fb353b8e6ab8ddc7d3ad5bfb45a4c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 17 17:22:57 2015 +0200

        kernel/countdown: simple counter

    commit f7ef8e3be16cd6203b3a42b6ec316fd492805831
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 17 17:21:05 2015 +0200

        GenerateThreadpool: bugfix IP_REPO_PATH

    commit 1f6351e5de771c1b8f2081e79726ca7810a7324c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Apr 17 16:41:24 2015 +0200

        examples/machsuite-harness

         * implemented all 15 working benchmarks
         * separate executable for each benchmark
         * added bin/arch tree layout

    commit 0dd643733614616bf412f407281ed6c2c8e7346a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 8 15:29:49 2015 +0200

        platform/zynq/module: new tests subdir, stress alloc test

    commit daa15f3d9b30df9f977c519cd251cb168a8e8bff
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 8 15:25:03 2015 +0200

        platform/zynq: removed pseudo-perfcounter

    commit d9c94c490147900964ff2d390d5402cbca0917ce
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 8 11:32:45 2015 +0200

        platform/zynq/module: improvements in load/unload scripts

    commit c465d07a405ba2cf976965b0adda1b1cbc2982fb
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 8 11:30:36 2015 +0200

        platform/zynq/module

         * IRQ bugfix: setting correct irq number in internal array for 2nd
           controller
         * fixed bug concerning check for highest bit (signed/unsigned)

    commit 665e11049a5b94a171d2f50f79a892c35998d7c2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 8 11:27:41 2015 +0200

        platform/zynq: added missing INTC init

    commit 6d82de2ae3021adee1009516c945a8ec58f8af0c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Apr 8 11:26:49 2015 +0200

        platform/tests/platform_slots: bugfix in cycle number

    commit 90b790767d8fd8a50e1718112cf24c9504b701d1
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 18:05:26 2015 +0100

        examples/machsuite-harness

         * generic harness for MachSuite kernels
         * some plotting tools etc.

    commit 85cfea3825d8bde4b1aec1335e40ae329ee6c5f0
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 18:04:36 2015 +0100

        examples/memcheck

         * improved build
         * bugfix: first output line fixed

    commit a792a2bced49339831ca891ad2a1687e11faef76
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 18:03:21 2015 +0100

        examples/benchmark-cd

         * built by CMake
         * general frequency detection: TPC_FREQ can be used for sim

    commit e83c0ebe29198ef712eb8e687aa26dc47960a2f6
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 18:02:06 2015 +0100

        examples/examples.cmake: improved build

    commit c9695b017a7f0e758bc2e6bd428ae307a626f537
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 18:00:07 2015 +0100

        common/common.tcl: fixed PS7 properties

    commit de88b6df52db4212aa721b0d3b88071fdf0749ff
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 17:57:35 2015 +0100

        GenerateThreadpool

         * replaced uses of deprecated getMode with tpc_get_generate_mode

    commit be45c0295700ade188a499dc1e515d85a4264599
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 17:56:44 2015 +0100

        Bugfix: Cross compilation toolchain file.

    commit c00b958dfc01343539e4e5bbfdd648b436d9b5ad
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 17:55:38 2015 +0100

        arch/common, arch/baseline

         * proper logging mechanism for TPC
         * started to improve logging of TPC API implementation
         * improved build

    commit bd47dd465b79d4b90a8a797a4266425263f0ab45
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 17:53:36 2015 +0100

        platform/zynq/module: irq handling bugfix

    commit c3bfb433cdd143f00e4cb6b12aea9dc93d8ab122
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 17:51:03 2015 +0100

        platform/zynq

         * DPI libs: major overhaul, better logging, bugfixes en masse
         * removed unnecessary locking, most locking is done in SV now
         * simulation is now working again

    commit 49ed76c0339a406ea61d7bfb0a9ca061bc82392e
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 17:48:03 2015 +0100

        platform/zynq

         * bugfix: simulation IRQ handler is now protected via semaphore in SV
         * improvement: semaphore for GP0/1 split into read and write
         * several minor improvements and bugfixes

    commit 3e0e7c128cb9dff06214ed82dd9618f57583fd5b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 17:45:33 2015 +0100

        platform/tests/platform_slots: using iterations

    commit 22f27a17e64412e09bee24f260d2a814ae144dd3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 17:40:15 2015 +0100

        platform/common

         * cleaned up extern symbols (esp. logging)
         * moved platform_strerror implementation to header

    commit 6582abfd703ec0d39b9a4c0a6610e9dd96e9bedf
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 27 17:30:43 2015 +0100

        platform/tests

         * extracted some common routines into common.h
         * platform-slots: new test which triggers countdown instances in all 48
           slots to test basic functionality; has implicit dependency on
           baseline architecture, should be cleaned a bit eventually, but is
           useful for basic tests at the moment
         * fixed build process, eliminated some warnings

    commit 63ad6c669d90e6cad55d904975515f718be78cc2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 24 14:58:08 2015 +0100

        platform/tests

         * platform_stress_alloc: added actual write/compare mode which gets
           data from /dev/random and performs actual transfers instead of
           sleeping for random time

    commit a08729aa2fb61022dcd4cee0e1f31de295606289
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 24 14:56:58 2015 +0100

        platform/zynq/module

         * bugfix in memory allocation

    commit 5e8c17901919b5be7a7d692c1993a619bbcb2061
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 24 14:52:13 2015 +0100

        platform/zynq (ZC706):

         * added fan control circuitry: 4-bit counter, uppermost bit generates
           PWM for SM_FAN_PWM (pin AB12); reduces fan RPM by approx. half =>
           extreme improvement to working conditions :)

    commit 1e0c5f4f523bd150ddd4e6bc12d7a885366ba145
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 24 14:36:16 2015 +0100

        common/common.tcl: new IP - binary counter, reg slice

    commit 2337467f1827b48e7dece63b6fd03778bc0643de
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 19 18:56:34 2015 +0100

        updated kernel.descriptions

    commit 7b5c4ea6680978a192ad13246f73782370ff8d48
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 19 18:55:02 2015 +0100

        scala-code

         * improved error handling in GenerateHLS
         * bugfix kernel names in GenerateThreadpool

    commit 054d1486cb366bdbcc0b0170cfcd0de53bbcf9a1
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 19 18:52:43 2015 +0100

        examples/benchmark-cd: decreased max time

    commit f96d2a753b1280685560b8b74d5e26ff60d5ba5b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 19 18:51:05 2015 +0100

        examples/memcheck

         * st-version: increased buffer sizes in test
         * mt-version: configurable number of threads & iterations

    commit bcc4c851112387748234319b214c615b80ce918f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 19 18:50:38 2015 +0100

        examples: move to cmake

    commit c8d42713b5513b9d455631b248c7e5a382edaac2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 19 18:47:31 2015 +0100

        arch

         * baseline: static lib compilation, multiple archs
         * tpc_jobs: hidden init_job

    commit 6b89333457b6f3c5add6cba4b6a1259c704d7618
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 19 18:44:35 2015 +0100

        Platform API

         * improved error messages
         * consistent use of size_t for byte lengths

    commit 774ab1dcb39447f465e41b401954ae33205e42fa
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 19 18:41:14 2015 +0100

        platform/zynq

         * unified and improved logging in libplatform
         * unified and improved interfaces for lib functions
         * fixed build process to include error messages

    commit 6476eee3eb79d23ca9b13e5ee1551974a3492761
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 19 18:36:41 2015 +0100

        platform/zynq/module

         * logging_level is now writable for group
         * dealloc now returns proper result to indicate double free's
         * using ssize_t consistently in alloc/dealloc now
         * zynq_fops: reduced log

    commit f44f868befd6d4aa4d0682e37fa7fbfd791be18e
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 19 18:33:40 2015 +0100

        Platform API

         * added subdir 'tests': generic Platform API tests
         * added 'platform-stress-alloc': multi-threaded test to stress the
           alloc/dealloc mechanism

    commit bf6315200783958f7ccdfc2be6374af5a9989ee7
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 16 12:13:05 2015 +0100

        examples/memcheck: moved to cmake

    commit 63b457804d3692837e0cc43b7722015f5f7508d5
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 16 11:06:19 2015 +0100

        arch/baseline: cross compilation

    commit 5ce751151144d58d8a4f9e397f5c9961274f3439
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 16 11:03:33 2015 +0100

        platform/zynq: cmake cross compilation

    commit 2b176342998b73b99c6fd43979b5ab344464a5f3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 16 10:18:38 2015 +0100

        platform/zynq

         * static and dynamic libraries
         * fixed errors for NDEBUG release version

    commit 646b9db79b3bfe2a20aa880c6fc75d2d8def814d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 16 10:17:42 2015 +0100

        arch/baseline: now using cmake

    commit bc2a6bc05927bd9caf297848412491312b26ca51
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 16 10:17:17 2015 +0100

        arch/baseline

         * static and dynamic libraries (getting out of hand)

    commit 29c24db0a720c812615499a0c98979b6d031b846
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 13 16:33:45 2015 +0100

        Platform API

         * dealloc now returns a platform_res_t
         * fixed bugs in alloc/dealloc types (used size_t instead of ssize_t)
         * improved debug outputs

    commit 5817189b5de369e7861353ff80ca870c1516c22b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 13 16:31:24 2015 +0100

        platform/zynq/module

         * additional debug output

    commit 120b3ccbaa6d128fdcfa5243f0957c34f0554e17
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 13 16:30:06 2015 +0100

        platform/zynq/module

         * bugfixes in gen_fixed_size_pool: race conditions fixed

    commit c6c50e4f3aa67b490594f70e11c57f91e813dda3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 11 19:29:33 2015 +0100

        arch/common/tpc_scheduler: error checking

    commit 94bc93c894217f4da40a40350d9d1b2755ea8c14
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 11 19:29:12 2015 +0100

        arch/baseline

         * added profiling flags to lib

    commit c37997306515db6b051859ff05a3556b190919e4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 11 19:26:02 2015 +0100

        platform/zynq

         * bugfix in zynq.tcl: INTCs are now correctly wired

    commit 07e2277606542b788629504b2edbab936040912f
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 11 19:25:31 2015 +0100

        platform/zynq

         * profiling flags for libs
         * cleanup

    commit 490ec6f606ad892ecd2d311e049e3e6fbc3a59cb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 11 18:58:29 2015 +0100

        platform/zynq/module

         * replaced deprecated __sync_... calls by new __atomic_... calls
         * changed pending_ev from bitmask to array of ints to reduce collisions
         * fixed several bugs in interrupt handling (race conditions)
         * improved sleeping mechanism
         * added time measurements for zynq_device_wait, output on exit

    commit 3d74467cbacea2ca4d891b509576a96997feed41
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 11 18:43:09 2015 +0100

        examples/benchmark-cd: current measurements

    commit f833e2f0dde3a76ecead0d6263c02d74276136a2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Mar 11 18:41:41 2015 +0100

        examples/benchmark-cd

         * new benchmark: based on countdown kernel; illustrates speedups gained
           by blocking launches in multiple threads
         * plot compares actual speedup of pthreads with usleep to TPC launches

    commit d7ddefe81985c9a98980df84a55a1dad95759f5d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 10 19:08:52 2015 +0100

        arch/common

         * moved jobs queue to gen_fixed_size_pool
         * removed debug output in scheduler

    commit ca5f82c37d9a0ecd86ca91d58c11f4a2580b3784
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 10 18:12:44 2015 +0100

        examples/benchmark-alloc-dealloc

         * new benchmark: speed of alloc/free in TPC API implementation
         * comparison to malloc/free

    commit d3651942ca1f223600d4d229d19d2040e434b810
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 10 18:10:30 2015 +0100

        examples/benchmark-mem

         * added comparison to virtual memory (depressing!)
         * updated gnuplot script accordingly

    commit 4c4f3097d6bb0a52396f4c9c63e29f3dde3a2364
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 10 18:09:12 2015 +0100

        examples/arraysum

         * updated to new common Makefiles
         * arraysum-example-mt: uses only on thread per core
         * fixed mem leak

    commit 79b36fd9481757272f2c49960ca6569b0beb0ee7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 9 13:28:50 2015 +0100

        platform/zynq/module

         * bugfix in zynq_fops: deactivated caching on mmap'ed dma bufs

    commit 74cb5b82ebb853707f9d0bc4b944e57d77ed7cd9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 9 13:27:19 2015 +0100

        examples/warraw

         * updated to new common Makefiles
         * warraw-example-mt: uses only one core per thread now
         * fixed memory leaks (missing tpc_device_free calls)

    commit 385908e9203522f05964f891441d91f3a92d2496
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 9 13:09:10 2015 +0100

        examples/arrayinit

         * updated to new common Makefiles
         * arrayinit-example-mt: only uses one thread per core now
         * fixed missing tpc_device_free's

    commit 65e58948398044e20a68876123707936c6213c77
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 6 15:37:24 2015 +0100

        sim_setup.sh: updated to arch subdirs lib/

    commit e765afb7ef4fa82b6d7d2a3dfc32f932fd426c1b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 6 15:21:52 2015 +0100

        examples/memcheck

         * updated to new common Makefiles
         * add-example-mt: uses only one thread per core

    commit ca599628039ac13aecdf2e34ac77604bfa361c8e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 6 15:17:28 2015 +0100

        examples/add:

         * updated to new common Makefiles
         * increased number of runs
         * add-example-mt: use only on thread per core

    commit 1a197037a9c3d6df0698f0590d86c5b7b8c8e1c1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 6 14:53:12 2015 +0100

        benchmark-mem

         * added new baseline: memcpy in virtual memory instead of copying to
           device memory to evaluate overhead
         * current overhead at ZC706: ~2x
         * makeplot.sh takes filename argument to produce diagram autom.
         * updated Makefile to use new common Makefiles

    commit 55a1d9bf7aa2901559a6ac69cb9fc8adfcd8c631
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 6 14:51:00 2015 +0100

        examples: common Makefiles with lib targets etc.

    commit 413743d311ccb9812225eb32be0465093b05a150
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 6 14:46:22 2015 +0100

        arch/baseline

         * lib/ has now subdirectories for different architectures
         * scheduler ack's interrupt (should probably be moved elsewhere soon)
         * adapted tpc_device_alloc/dealloc to work directly with DMA addrs

    commit 465625e6f74041eb7ae45e283b2add6a1778f999
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 6 14:43:50 2015 +0100

        platform/zynq

         * lib/ now has subdirs for different architectures
         * first working implementation based on LKM

    commit 8fdf91dd3832365146f799e373418b04a2d13913
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Mar 6 14:40:28 2015 +0100

        platform/zynq/module

         * alloc now returns DMA address instead of ID
         * new file 'bufferid' allows userland to convert to ID (O(n))
         * several methods changed to accomplish that

    commit 8a97a0950f72c0f3223ca96d17b53ba0f60058b8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Mar 5 14:46:51 2015 +0100

        platform/zynq/module

         * first working version: implemented wait_queue for interrupts
         * new 'wait' device file which can be written with a slot_id to wait
           for the corresponding interrupt
         * removed old alloc/dealloc program

    commit 6860a6d52151d82d2b76a4e6e5ba588cd3149634
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Mar 3 16:13:25 2015 +0100

        platform/zynq/module

         * basic support for IRQs
         * refactoring; improvements and bugfixes

    commit d07f6aa4c39a5f7eeb3e890155d593dd5a420780
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Mar 2 16:26:13 2015 +0100

        examples/benchmark-mem

         * new example: memory access micro-benchmark
         * transfers 1GiB of data via chunks ranging from 4KiB to 64MiB
         * uses one thread per processor, afap
         * gnuplot script to evaluate

    commit bf8f50510a226b1b503c3a8ee5e5beedf56ad134
    Merge: 6798742 4203d2c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 27 18:03:32 2015 +0100

        Merge branch 'master' of https://bitbucket.org/jkorinth/rcu

    commit 679874201d6c7e3ad86fc847684085fc91e3fad2
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 27 17:54:49 2015 +0100

        Initial version of zynq device driver.

         * only alloc/dealloc supported at the moment
         * based on DMA buffers allocated via dma_alloc_coherent
         * buffer id's used as platform_mem_addr_t
         * user interface: sysfs files alloc/dealloc + individual char device
           for each buffer (at the moment 1024)
         * user can mmap the buffers; used in Platform API
         * had to add platform_alloc, platform_dealloc to Platform API, TPC API
           uses them as implementations for tpc_device_alloc/dealloc now
         * backported simulation lib, seems to work
         * tested on ZC706 with memcheck, memcheck-mt and memcheck-mt-ff

    commit ac38d7daa47f900fcc251de15909605303b5cddb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 27 18:00:05 2015 +0100

        GenerateOptions: toAbsolutePath bugfix

    commit 4203d2ce27faa02c73f5a235beb0b7e05a8e1540
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 27 17:54:49 2015 +0100

        Initial version of zynq device driver.

         * only alloc/dealloc supported at the moment
         * based on DMA buffers allocated via dma_alloc_coherent
         * buffer id's used as platform_mem_addr_t
         * user interface: sysfs files alloc/dealloc + individual char device
           for each buffer (at the moment 1024)
         * user can mmap the buffers; used in Platform API
         * had to add platform_alloc, platform_dealloc to Platform API, TPC API
           uses them as implementations for tpc_device_alloc/dealloc now
         * backported simulation lib, seems to work
         * tested on ZC706 with memcheck, memcheck-mt and memcheck-mt-ff

    commit 05fe3b8f7992e2374e8a8f9c63833396a0e37c12
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Feb 11 08:42:22 2015 +0100

        release file list for D5.1

    commit 29313661c4661ea2a7d9627f57d57aa8dde1a5b6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 17:53:36 2015 +0100

        BitstreamDescription.scala: fixed error in deprecated tag

    commit d2f07f4ff2c20e776523b5331140552e80366d65
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 16:53:02 2015 +0100

        platform/zynq

         * added code to automatically start the simulation

    commit c75f5382a9c98080dfc9eef848acb473301783d7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 16:51:55 2015 +0100

        GenerateThreadpool:

         * added launching of Vivado
         * removed some debug output

    commit d80552fb442683dcba456f0d991f871d7eaea680
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 16:06:59 2015 +0100

        GenerateThreadpool: bugfix.

    commit feb49ea6b5b58d662c4fdc41bedfd7657d000209
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 15:46:55 2015 +0100

        src: added zerolog config for threadpoolcomposer

    commit 06dc9f377cfb1bd2fc2a5f737ed48b3210d2f928
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 15:46:25 2015 +0100

        src/main/scala/threadpoolcomposer: D5.1 polish.

    commit afb35776bce31eec5e23837997dff99da8c69508
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 14:57:54 2015 +0100

        src: cleanup.

    commit 84bd7cf0d2a013b3488926691d51e1df96543c3c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 14:40:25 2015 +0100

        arch/baseline: D5.1 polish.

    commit 9e8c66c385c107dee8ba9d2bb75f156f28e7370b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 14:19:51 2015 +0100

        arch/common: D5.1 polish.

    commit 84798b6b5a138006ce77653ed1847438663e3bc9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 13:22:27 2015 +0100

        TPC API

         * updated main header: added flags to several calls for future
           extension and DSP support
         * Platform API update

    commit e2ea7f54431c3c66cae1708587d19a606978a991
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 13:19:23 2015 +0100

        platform/common: D5.1 polish.

    commit f7125e4e31d6b53834a9c84667a25edfefc56799
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 13:18:58 2015 +0100

        zynq/platform: D5.1 polish.

    commit 5dab68e98afdfe41f60df9e81af2ac05e0c32dda
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 12:54:55 2015 +0100

        Platform API: main header C++ compatibility

    commit b0912e98e646d811f6f13a2acf03e62cfa9fb1bc
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 12:53:00 2015 +0100

        platform/zynq: Platform API update

    commit 4ff95827b0bb63822b04e41531476c1a1ce1d542
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 11:53:02 2015 +0100

        kernel/warraw: D5.1 polish.

    commit d670ea8c398736d29f03674d564584ae9dd6cb38
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 11:49:10 2015 +0100

        kernel/arraysum: D5.1 polish.

    commit 1782df137d2b453a776abe9a390a912cc134714d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 11:47:29 2015 +0100

        kernel/arrayinit: D5.1 polish

    commit 1a0159945c470fbacba8b95629baafe0b1bce6fa
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 11:45:07 2015 +0100

        kernel/add: D5.1 polish

    commit 184507f0906c0706998058f17652ab41dc4f6fa8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 11:40:30 2015 +0100

        TPC_HOME/common: update

         * HLS now replaces logo
         * inline doc for common.tcl

    commit de9e9d453081529e2e8d584b1ca488a32cccaa6c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 10:06:30 2015 +0100

        examples/README.md: update.

    commit c45b2ba12a5ad85f8903043a36272ed355173b0c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 10:06:11 2015 +0100

        examples/warraw: D5.1 polish.

    commit 866e792e5ad7263ab79b9be4a028dfe083858986
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 09:49:32 2015 +0100

        examples/arrayinit: D5.1 polish.

    commit bc145faf85182797486466a009479afedc49a5c7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 09:33:23 2015 +0100

        examples/arraysum: D5.1 polish.

    commit 1e72cf262a382a835b29c16eb58bddf417973701
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 09:08:07 2015 +0100

        examples/add: D5.1 polish

    commit 1e88b3550c073f9c21e6ed5c7d315d1dcf5cd4e5
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 08:49:29 2015 +0100

        examples/memcheck: update & D5.1 polish.

    commit c223760fc0f2862c2940ca490d8edcd2455c356d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 08:01:26 2015 +0100

        examples: added README.md

    commit bc3bf6f6426b64fbcbd004fa1a263c99a4574585
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Feb 10 07:47:23 2015 +0100

        kernel/arraysum: polish

    commit 391cec5cd3df742ad1dffd03c36f00f5ae13b6fc
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 9 19:23:01 2015 +0100

        examples/readwrite1: update

    commit 148db0fb7544c5ecc4a5e89a38430b6f347d2bd3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 9 19:21:16 2015 +0100

        examples/writer: update

    commit f0472f9adba2e0b257c322161481cce821631aab
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 9 19:19:34 2015 +0100

        examples/reader: update

    commit c5f1c5e2e08766bdd9d5a3a3e45ed427d59d21ef
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 9 19:19:04 2015 +0100

        examples/add: update

    commit b402900476dad2b28ec818855fa8177234e96087
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 9 18:29:49 2015 +0100

        kernel/readwrite1

         * renamed: warraw
         * D5.1: polish

    commit 608890c2bfcb3cd29ac479f028ee0101cba4850e
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 9 17:59:38 2015 +0100

        kernel/writer

         * renamed: arrayinit (AK's suggestion)
         * D5.1: polish

    commit ba5c232bc3ae4e1592a43d0ee3fc30016a618dcf
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 9 17:44:21 2015 +0100

        kernel/reader:

         * renamed: arraysum (AK's suggestion)
         * polish for D5.1

    commit 63fcb4748e2729dc7c3b648f0d069ce3dcbac526
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 9 17:24:38 2015 +0100

        kernel/add: polish.

    commit 310df14be7ea2b048b2d98acd6eeec72f6e5d8e2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 9 16:40:56 2015 +0100

        Simulation: added sim_setup.sh for example configuration.

    commit 32967599f6d91d381824a489b6fcf41420b7d0c9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 6 18:11:07 2015 +0100

        doc: next update, first draft of "Implementation" chapters finished.

    commit 31770fc06a99758d601f2318db787f15b227e76b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 6 11:25:40 2015 +0100

        doc: worked on Architecture implementation chapter

    commit eca6ea7544427264d2a2fb2bf83d5b8e3137f0d3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 6 09:01:59 2015 +0100

        GenerateHLS: moved main Tcl template to general common

    commit 8cd8ea0694f4a3be0b4d3c300849524f03055e4b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 6 09:01:36 2015 +0100

        common.tcl: fixed hardcoded defaults by tpc_... calls

    commit 42dc88aaeefd008ee8e06aeb484a849faacb7c9f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Feb 6 09:01:12 2015 +0100

        build.sbt: fixed C lib dependencies

    commit 0baa2e6d911b197c91a4700831965a5d7d9d96c7
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Fri Feb 6 08:52:30 2015 +0100

        doc: next update.

    commit b1d38d017f280d6877f629ebdda561e4eb4bd358
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Feb 5 19:09:29 2015 +0100

        Documentation: incomplete initial draft.

    commit 8181e2da24f49353de007b81ff622fa092468555
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 2 11:06:04 2015 +0100

        moved to package de.tu_darmstadt.cs.esa.threadpoolcomposer

    commit b94201d3acf7e8f2995f71b604a40231cf8d8297
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 2 10:36:23 2015 +0100

        removed obsolete 'driver'

    commit 93ad55f8236fb4c6ea577ad0e48d4d8037502e6c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 2 10:33:48 2015 +0100

        removed obsolete 'hwswcosim'

    commit 2e4ae7efad5ac5a31683bc38156f01c54c7d1f9f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 2 10:32:50 2015 +0100

        removed old 'fpga-api'

    commit 0a615174b54bbd6c4d42c970470c25f231bd46fe
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 2 10:31:07 2015 +0100

        tpc_api.h: fixed typo TPC_COPY_BLOCKINGS

    commit bde5f9cabe61d4b8e0b7daa95466898a7e3db265
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Feb 2 10:30:26 2015 +0100

        arch/baseline: fixed symbolic link

    commit 575d27667f04cdd245a2e561ddb2118bd99d091a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 30 18:20:34 2015 +0100

        examples/add: new example

    commit 4d28b3990962abd7c4f5b9c1574a0ffa8b555b44
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 30 17:45:58 2015 +0100

        platform_client.h: fixed missing stdint include

    commit c84fe451c2998c4a72f2c3e7f7c8fb61d6e26ed2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 30 17:43:08 2015 +0100

        build.sbt: added sbt tasks 'hls' and 'threadpool' as wrappers

    commit 56e2de411bab5f37376165ef6c7716871fd84af7
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 30 17:42:39 2015 +0100

        KernelDescription: bugfix for testbenchSources

    commit 13d4d6d747a38fe2f5d0d61240fd10cbf73f2180
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 30 17:41:28 2015 +0100

        GenerateThreadpool

         * extracting IP to project directory now, fixes double IP warnings
         * nicer output

    commit 438a7ed0063ec42191e24559f0616cb58d23c742
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 30 17:35:06 2015 +0100

        arch/baseline: bugfix in Makefile

    commit 26a4333a6aec58383ae7ad063be032a5746de9fc
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 30 17:34:18 2015 +0100

        arch/common: added new unit tests in 'check' framework

    commit 903c8f54a3e7f26faebed876cd51f10a72dffec7
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 30 17:33:25 2015 +0100

        arch/common: removed old test code

    commit 678d64479a0089975354b7deaafe7a66aaeb2aad
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 29 09:07:55 2015 +0100

        GenerateOptions: configFile support

    commit a0fcb2aadc9dd062e731ea523bb3f6fe69377631
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jan 26 16:18:41 2015 +0100

        platform/zynq

         * renamed RCU_DPI_SERVER_LIB to PLATFORM_DPI_SERVER_LIB
         * also renamed several other env vars to common prefix PLATFORM_DPI
         * setting current run in 'bit' mode

    commit 844597cdb73aac35a83f935e3fff817e05864c1e
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jan 26 16:15:53 2015 +0100

        tpc_functions: TPC_LOADOUT -> TPC_COMPOSITION

    commit 21ef630daffdc92511c725087741820d496bec6b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Jan 25 13:50:05 2015 +0100

        platform/zynq: set current run to show stats

    commit 7931378194b5a772f52c8ef2d78b8e7dac086f39
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Jan 25 13:49:17 2015 +0100

        common.tcl: tpc_get_design_period API call

    commit 407f3b8d133e3755a196bec93a9b184399ed2e49
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Jan 25 13:46:34 2015 +0100

        GenerateThreadpool

         * automatically triggers HLS builds for dependencies instead of
           raising an exception
         * exception will only be thrown, if for some reason core .zip is still
           missing after HLS step

    commit 2e72cc30cd5fa63aeb146c083a9cec35b4296b9c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Jan 25 13:44:36 2015 +0100

        GenerateOptions

         * bugfix: if kernel description for a name cannot be found, all
           available kd files are instantiated and their names are scanned;
           this will find modified names, e.g., "spmv-crs".

    commit 627dfae98d0f8777aa08431b9c5cb25f37183f50
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sun Jan 25 13:42:12 2015 +0100

        GenerateHLS

         * PERIOD now determined by TPC API method
         * made co-simulation optional (depends on whether tbsrcs were given)

    commit aeacc17c6188db499e974a230bb257765ef21d91
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 23 10:03:59 2015 +0100

        baseline.tcl: bugfix in mem ic wiring

    commit ad63f5b6b8a94fb02dff9ab2d9d10730afec8d73
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 23 10:01:13 2015 +0100

        GenerateThreadpool: bugfix

         * added some checks regarding multiple/missing zips for composition
         * cleaned-up code a little, fixed association

    commit 25f9a2b5742e819ae0dd98a67907dff5766f5ca4
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 20 17:10:35 2015 +0100

        new example: readwrite1, ST/MT working (reeeeelly slow)

    commit c49cdc9ac1af5e102a4d0d7caa2e6c2eca59a9e6
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 20 15:56:32 2015 +0100

        examples/writer

         * writer example working for ST and MT
         * unfortunate: if kernel has no return value, first param reg is 0x10
           instead of 0x18; it is not possible to make Vivado HLS 2014.3
           generate the base register at the correct address, therefore I had to
           adapt the writer code

    commit ec34b6f3c08e3ed27f4226e58c9cd514d31d2cbb
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 20 14:14:07 2015 +0100

        zynq/baseline: improved IRQ handling

         * moved architecture-specific 'bottom part' of IRQ handler to callback
           mechanism: client platform lib now has platform_register_irq_callback
           function, which can register up to 10 callbacks. callbacks are fired
           by platform client lib automatically _after_ return from
           platform_write_ctl_and_wait.
         * common.tcl: since IRQ of HLS cores gets ack'ed _after_ IntC, it was
           necessary to switch from level-sensitive to edge-sensitive interrupts
         * implemented rudimentary handler in platform client lib (zynq)

    commit 6b65db1f649bd0f581c83fded61170b2bf0a5c65
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 20 12:59:35 2015 +0100

        examples/memcheck: ported to refactored APIs

    commit 472f510848a1a37554d0ae8056a3b62ff244d076
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 20 12:57:57 2015 +0100

        examples/reader:

         * moved to refactored APIs (TPC)
         * bugfix: colossaly stupid bug in memory allocation caused bug in MT
         * MT now works

    commit 3afb2162a7ef1b4fb148187a99329b79b97ae436
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 20 12:50:01 2015 +0100

        GenerateThreadpool: bugfixes

    commit e4258a7300c458377de47d95ab7a1256e7cca9e9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 20 12:49:18 2015 +0100

        common.tcl: new TPC functions

    commit 88e93e1a12bc264881305e19ccfc374097ed29ed
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 20 12:47:02 2015 +0100

        common/scheduler: fixed write_and_wait call

    commit 58a111b08f0e59f15895902b994b14360eed7afa
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 20 12:44:48 2015 +0100

        common/functions: added support for 48 functions

    commit 34de9178b00b46d5f1862237d5fd853ae76c8ed2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 20 12:43:43 2015 +0100

        baseline/common: added IAR reg to address map API

    commit 0ba1c6a7f74e267a16fdc56344e9db82bef91c90
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 20 12:40:21 2015 +0100

        platform/zynq

         * support for 48 cores, 2 IntC's
         * moved interrupt controller init here
         * fixed platform_write_ctl_and_wait: event number as param
         * replaced import template needles by tpc_... calls
         * successful simulation for 48 readers

    commit 05b84ed34929226db42264dfff91740e45436e4f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jan 19 15:55:19 2015 +0100

        Refactoring (Ib)

         * renamed PlatformTclTemplate -> TclLibrary; adapted Zynq
           platform.description accordingly
         * renamed DesignTclTemplate -> TclLibrary; adapted baseline
           architecture accordingly
         * changed Description classes as well
         * addded GenerateThreadpool: generates complete Tcl script
         * Simulation not working again yet

    commit 25d5916c1db85b43582cca70be65b0aaead11770
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Jan 19 15:18:43 2015 +0100

        Refactoring (Ib)

         * support for 48 cores in Zynq (2nd IntC, HP0-2)
         * address map change: IntCs now start at 0x81800000 (connected via GP1)
         * error in FCCM Paper: GP2/3 don't exist! Host connection to HLS cores
           via GP0 exclusively, two-level IC hierarchy as before
         * improved modularization:
           Arch/Platform/TPC now separated, well-defined calls at each
           interface; TPC (common.tcl) moved to /common, Arch/Platform
           implemented as pure Tcl libs (no more templating)

    commit 3bf625a24d8f0ff079261028e48f6a4efc551172
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 16 14:06:52 2015 +0100

        platform: refactoring

         * 'data' space and all funcs renamed to 'ctl'

    commit 57d7622a274de20d066b8daacd5e1f5fc561e7c2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 16 13:53:26 2015 +0100

        baseline: FPGA API -> TPC API

    commit 4f05c6460b84930b1fb715c5191800fe1d22b13b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 16 13:49:56 2015 +0100

        Refactoring: FPGA API -> TPC API

    commit 6c6d893d81021a2e8e9dbb86a711a6598710d89b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 16 13:30:58 2015 +0100

        Refactoring

         * "Loadout" == "Composition" in bitstream.description
         * "SimpleArgs" -> "ValueArgs"
         * "PointerArgs" -> "ReferenceArgs"

    commit 09c0331ad5b14c263b7ed6fb0e954c1810195c53
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 31 17:31:47 2014 +0100

        platform/zynq

         * fixed interrupts: generic 'events' in platform API can be triggered
           and waited-on via API tasks now; semantics of the events are in the
           platform API, event number simply passed to ..._and_wait.
         * works fine now; SV threads can sleep while others make progress
         * added platform_irq_handler platform API call: ack's interrupts and
           triggers corresponding events to wake up the original SV-thread.
         * open: code to ack interrupts should reside in FPGA API, needs a
           mechanism to pass control upward (not yet implemented)
         * added semaphore-based locking in SV API; need to check if
           platform API locking is now superfluous!
         * reader example still does not work; results are wrong, no idea why
         * several minor improvements, e.g., signedness in SV API args

    commit 04be30706310d2987c123fa0d525d2e439fa5b4e
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 31 17:26:02 2014 +0100

        common/common.tcl: bugfix in createInterconnect (missing regslices)

    commit 6241f86ddba2d256b3c4006352e9bed611c8f1d3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 30 16:58:28 2014 +0100

        examples/memcheck

         * improved MT version: detailed AXI addresses in wrong data output
         * more verbose / improved messages

    commit fedc3d85ba9039b082dcd09a85f2b4c3829bff95
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 30 16:54:49 2014 +0100

        platform/zynq: MT bugfix

         * unfortunate: AXI BFM tasks are not reentrant; locking necessary
         * locking mem access r/w independently, but across sockets
         * fixed problems in memcheck_mt
         * added env vars PLATFORM_SERVER_DPI_LOG and PLATFORM_CLIENT_DPI_LOG:
           if set, platform debug output will be written to these filenames
         * fixed many race conditions, improved atomics code, e.g. transactions

    commit 329990620f4d1dff075faf77a6942ea6ec1dabbc
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 29 19:49:45 2014 +0100

        examples/memcheck

         * MT version: added thread id to all outputs

    commit 0a096bd4cc68a136e2cdfd0e8e413541e4668800
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 29 19:48:41 2014 +0100

        arch/common: functions

         * bugfix: functions array was not properly initialized

    commit bdb2773209a0422b1869fc06de6f989dfac32698
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 29 19:47:38 2014 +0100

        arch/baseline: changed mem master ID width to 6 bit (hard IP value)

    commit aaeed1c2742037160b29f6104615f9038ed165f5
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 29 19:45:35 2014 +0100

        platform/zynq

         * moved transaction id higher up; must be provided by platform lib now
           instead of being requested from SV level
         * moved number of sockets into single header file; added SV API call to
           determine number of threads
         * experimented with transaction ids, but to no avail, still doesn't
           work

    commit 9e20699d166c0ecb8e318203c7d2cbda5ecdcf15
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 23 13:06:49 2014 +0100

        examples/memcheck: added multi-threaded version

    commit 574382281960ebb4ff83442005b748b4d1cf78de
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 23 12:59:57 2014 +0100

        platform/zynq: multi-threading

         * rewrote basic mechanism of simulator interaction:
           command parsing has been switched to non-blocking mode to allow
           simulator execution model to work; after reset, simulator opens N
           socket connections via calls into the library. afterward, a task is
           called every clock to poll for new commands; if the socket is still
           busy (multi-cycle operations such as platform_read_mem), parse_cmd_nb
           is skipped, otherwise a new command is executed in a blocking manner
           (as before), but in the context of a SystemVerilog thread spawned by
           fork..join_none. This seems to work ok, trouble is with the IDs,
           transactions seem to get jumbled and mangled.
         * also added platform call for transaction ids
         * not working yet, see memcheck_mt example (single thread works)
         * N must be configured in three places: client, server and SV - this is
           clearly a fix-me

    commit 4076d6d02582304ea3b8154e8198458bc8f5eacd
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 23 12:56:41 2014 +0100

        arch/baseline: changed ID with of mem master

    commit ae326422b73d93036f19241ec0115c3e703c40af
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 22 17:44:19 2014 +0100

        FPGA API: rewrote jobs interface

    commit e355439f09436568ec17d28888b05df4aa489d05
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 19 17:06:29 2014 +0100

        platform/zynq: added big-lock-of-doom

    commit f571e3bdc3cad347e361bb41f9ff5b0fcb41449a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 19 17:04:30 2014 +0100

        example/reader: multi-threaded verison (Pthread)

    commit d3b48f5bfcac1ef852848be4e7b39dff10e9b9cc
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 19 10:04:12 2014 +0100

        platform/zynq

         * renamed env vars: PLATFORM_DPI_SERVER_DEBUG,
           PLATFORM_DPI_CLIENT_DEBUG
         * changed debug output accordingly (removed 'rcu')
         * improved style and inline doc
         * replaced debug output macros by funcs (almost)

    commit 8b80fa829b934d0d3f7e8ed12adaa90782597918
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 18 18:47:09 2014 +0100

        platform/zynq: improved style and layout in Zynq simulator code.

    commit 99868ddea83d485d526a1eaa69873d9cba221f15
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 18 18:41:31 2014 +0100

        platform/zynq: removed old client

    commit 516525e9a659cf29655ecc809afcbed531312b0f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 18 18:39:45 2014 +0100

        platform/zynq: platform_client.c inline doc and style

    commit 90da4e6b285f8d512a59cb93bf4053982f1d4e90
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 18 18:19:13 2014 +0100

        platform_client.h: inline doc and comments

    commit e6b180b482d86a1ccb589034670430d76b2fbe96
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 18 17:49:35 2014 +0100

        arch: cleaned up fpga_address_map helper

    commit 67ca49417c139edd61052175ac5da6e1c63122ff
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 18 17:35:19 2014 +0100

        platform: renamed CMD constants

    commit 255aac5a3207e145e2c4295ffb4f3c57f528c492
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 18 16:40:50 2014 +0100

        new example: reader

         * based on FPGA API
         * single-threaded test of reader kernel, successful!

    commit db4eb7a1eea27014300b489345804e9ffb805ec4
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 18 16:39:57 2014 +0100

        Added 'bd' to gitignore.

    commit 51aebd315ecdb9b31e23ac46fa24dd7a6ca0b88a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 18 16:33:40 2014 +0100

        architecture

         * baseline: setup_system initializes system by activating all
           interrupts etc.
         * baseline: design change AXI4Lite mem master -> AXI3M (bursts)
         * common architecture implementations (internal use):
           functions - function struct for scheduler + helpers
           jobs - job struct + helpers
           scheduler - basic scheduler header
         * scheduler implementation for Zynq: correctly ack's irqs etc.:wq

    commit a1a091fcdf5228f6e47fbcb5613acf86596308d6
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 18 16:24:16 2014 +0100

        platform/baseline

         * Zynq: implemented correct setup of system (i.e., enabling of
           interrupt lines etc.)
         * Zynq: simulator implementations of platform_read/write_data
         * Zynq: simulator implementation of platform_wait_for_irq
         * Zynq: simulator implementation of platform_write_data_and_wait; can
           be used to write into an AXI address and wait for a bitmask to occur
           at a different location, eliminates one round-trip to software for
           IRQ handling
         * Zynq: basic simulator implementation complete!

    commit 9c628d1ef335e8cce329adbbf54482866b274d8e
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 18 07:57:11 2014 +0100

        Bugfixes, minor changes

         * ArchitectureDescription: typo in default pointer arg template
         * Generate: moved svh's to platform instead of architecture

    commit 0f6d553fabd2f8cccdabe5d8a67b5d040256236b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 17 18:51:43 2014 +0100

        arch/baseline

         * continued implementation of FPGA API: job launching implemented
         * refined separation of common code and arch-dep code

    commit 8df29ad0d16d165de055074b79a5e96d63a2d005
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 16 18:13:16 2014 +0100

        arch/baseline: FPGA API implementation

         * continued prototypical implementation of FPGA API for baseline
         * env var sets loadout (preliminary, until we have own IP core)
         * started to implement function structs for the scheduler

    commit f5d43e6b02edeaa42a5cf9a2e7a8b8726b70b375
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 16 16:15:42 2014 +0100

        memcheck

         * basic memcheck test case to exercise memory access

    commit 7f75852319aa1a33de7be52424ca04ed8444b77b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 16 16:12:46 2014 +0100

        platform/zynq

         * platform stop can only be called in simulator environment; will
           therefore now issue an result-agnostic message (though the
           parameter stays for backward comp)

    commit 95eaafeb764ddb18f5b33147a7d611dd4c3d5b99
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 16 15:15:02 2014 +0100

        platform/zynq: added symbolic link libplatform.so

    commit 224462b0e7ae43307f6fc526e513b694baa93603
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 16 15:10:32 2014 +0100

        arch/baseline: FPGA API

    commit 99265d9e94b6dc017c80a93e22e2cc573d4eaf82
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 16 14:50:58 2014 +0100

        arch/baseline

         * switched memory master to AXI3 full to enable bursts

    commit 61177ecd37f510af69d43b353a962ea67fb1b010
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 16 14:48:00 2014 +0100

        Zynq: Simulator platform

         * prototypical implementation (still incomplete!)
         * implemented bursting on memory master

    commit bf52f7b79fa36a5f5acbe6a803f0487960b3c52a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 16 08:49:40 2014 +0100

        Started implementation of Platform API & FPGA API.

         * first for baseline simulation
         * extended platform API (renamed from RCU API) to match FPGA API with
           error codes, strerror etc.
         * current implementation incomplete, but data transfer works (no burst)

    commit aa5b2e937e4344b12d649aaffeb860bb052b8c64
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 12 10:38:37 2014 +0100

        zynq: updated platform to new Template and GenerateX

    commit 45890c88aa12e63d24de672ead51ab2c90857d97
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 12 10:37:07 2014 +0100

        baseline: updated to new Template and GenerateX

    commit 4d16a8e90ea350242f2d5169457e239a487fbc2c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 12 10:33:24 2014 +0100

        Major refactoring of Description and GenerateX

         * refactoring to separate arch and platform
         * added use of new bitstream/platform.description
         * rebuilt/simplified several parts of the generators
         * simulation does not yet fully work again: a simulator can be started,
           but there is no automation for the client (yet); still need to figure
           out how to describe testcases appropriately

    commit a4a2084a60aea5516b169f3995fd95cf64e965c9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 12 10:29:10 2014 +0100

        GenerateDesign, GeneratePlatform

         * added two new generators, which produce design.tcl and platform.tcl
           scripts for a given bitstream+arch+platform configuration
         * separation of concerns (platform vs. arch)
         * unified Tcls for Simulation and Bitstream, mode selected by env var

    commit 2a5400ca6eeb88295075062fe064337f91a420ff
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Dec 12 10:26:21 2014 +0100

        Template

         * convenience method to write interpolated file
         * changed DEFAULT_NEEDLE to require double-@ (fixes problems with
           interpolation in Verilog files, e.g., always @(posedge clk) @input..

    commit 9f625987efebf5a7cecba32258b9b9147f26f411
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 9 11:19:04 2014 +0100

        GenerateCommon: VLNV extraction from .zip

    commit 45dc4e8b4c929315038ee2652885bdb1ed12153a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Dec 9 11:17:13 2014 +0100

        Removed Zynq Simulator platform (will be part of Zynq).

    commit 9b59bf4109f85eebd683d66a66ae491297fb6347
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Dec 4 14:49:39 2014 +0100

        Template

         * rewrote and simplified the template logic and related stuff
         * Maps can now directly be pushed into template to provide needles
           automatically; Descriptions are Maps, which is useful
         * GenerateOptions rewritten, in separate file now
         * more streamlining

    commit 8c817976008c7235dfedf0c019678d6f45e202d7
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 3 17:39:59 2014 +0100

        PlatformDescription

         * initial implementation of file format
         * added two basic platform descriptions for Zynq and Zynq-based sim

    commit 46ad93cbee50a0d634d9d0a6594f81efd64cfd73
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 3 17:29:24 2014 +0100

        BitstreamDescription: initial version

    commit b325c6f4a4878eea00e97664c15b01633a3e1e1f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 3 17:28:03 2014 +0100

        GenerateSim

         * extracted Tcl procs to 'common.tcl'
         * started separation of design and platform
         * bugfixes
         * Description now always returns a value, but warns in logger if
           value was not found

    commit c88948adb98eca39cf27ac9667e144a8d1473140
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 3 16:06:21 2014 +0100

        KernelDescription

         * now based on Description, moved to separate file
         * bugfixes in Description
         * works at the moment

    commit 31b681ff01dc1ee4968c64ad60faae06c541700f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 3 12:59:15 2014 +0100

        ArchitectureDescription: move to new base class

         * is now based on Description and in separate file
         * minor changes related to move in GenerateSim
         * GenerateSim still works (for now)

    commit 07816b144b09c859c8c463e9c8c8c69abbe28ea2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 3 12:57:25 2014 +0100

        Description: generic base class for description files

    commit caad2f768534e653f7a2d2b2c9fb7760c828a464
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Dec 3 09:25:18 2014 +0100

        FPGA API:

         * added rudimentary 'job' struct which can take arguments for kernels
         * added minimal, array-based lists of such structs
         * some inline helpers to ease implementation of FPGA API
         * minimal test for job q's also included in common (probably temporary)

    commit 860b2cd9638e9bc04bb15abf2b8386b52f421925
    Merge: e9121d1 5d377d8
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 1 19:36:07 2014 +0100

        Merge branch 'master' of https://bitbucket.org/jkorinth/rcu

    commit e9121d126f2d5ad3817df5204a8f225a2b8dd66e
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 1 19:33:30 2014 +0100

        FPGA API:

         * added 'common' src dir for shared code
         * implemented error messages and codes (fpga_errors.h)
         * added second doxygen conf for 'full' documentation
         * added Makefile for building documentation
         * changed some signatures in FPGA API: instead of returning a pointer,
           pointer-to-pointer param and return fpga_res_t, which can give an
           error code indicating what went wrong

    commit 13884b8a8a2b1de05666e9d270e81c6abace63bd
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 1 18:24:51 2014 +0100

        FPGA API: first draft for header

         * as discussed with FastFlow people
         * extended with flags for non-blocking launches (later)
         * added strerror method
         * will add 'common' sources shared by architectures, e.g., strerror

    commit 452b5b5e20e6c5eeb60e2768c5a89a9aed7ea7c9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 1 17:43:13 2014 +0100

        MachSuite/common: removed old input/output file generation

    commit 982dfb9c0a6f5b4cc30f339fbf2e30abbe7fbab8
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 1 17:41:58 2014 +0100

        arraystruct: removed old tb-code (new sim does not work, though)

    commit 329d17cd4f632ad618e2cdd43bcedc14a8945eb9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Dec 1 17:39:12 2014 +0100

        MachSuite/aes: removed old tb-code

    commit 5d377d8fe8d5f0cfaf8337fea305939cb43cc5d1
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Fri Nov 21 10:03:13 2014 +0100

        Timer.hpp: Mac OS X support

    commit 4246c0fb3d38687a15052e161de0c8f395c7be94
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 18:27:22 2014 +0100

        Cleanup: removed refs to old stuff

    commit da64ad3b7195150426dad4cb8169433b35f3c1f2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 18:16:40 2014 +0100

        GenerateBitstream:

         * bugfix: base addresses were broken
         * deactivated broken checkTiming

    commit 801eccdba20d0a87bbff3b4866005bf7afe25c6d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 18:16:20 2014 +0100

        Cleanup: deleted old Chisel stuff.

    commit f58d434ba2c06f5c94eba2452388c3d8e7aec485
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 13:29:48 2014 +0100

        add: bugfix missing common.c in sources

    commit 41e469b716e9686d435d508edde0a9e7f1a5a6f6
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 13:04:12 2014 +0100

        GenerateHLS: bugfix for missing common include path

    commit d22b03120865f96339972603833a2f73110a6250
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:47:09 2014 +0100

        generic client: no bases addresses necessary

    commit d27e69382d78f603b3375150711cce8aba589e28
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:41:04 2014 +0100

        new testcase: add

         * minimal core to gauge size of arch overheads

    commit 77a3c3fbe665c948c923231bf7103157bc876d7f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:16:46 2014 +0100

        GenerateSim:

         * switched to new generic RCU sim client
         * rewrote simulation execution: both client and server need to be
           started in parallel; several timeouts implemented, also killing of
           the other process in case one finished prematurely (not sure if it
           works correctly, but it does seem to kill the processes on celebdil)
         * deactivated Vivado trace output (not much use with proc's anyway)

    commit 7ab5023059c37ab315bb4608fc6b1992e45ca5d7
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:14:51 2014 +0100

        GenerateCommon:

         * bugfix in splitting code; spaces before and after = now required
           (rationale: need to accomodate params like -std=gnu99)
         * added path property to retrieve original description file path

    commit 469237b5d990275a26e3bac34462f1c1f988e092
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:14:05 2014 +0100

        MachSuite/viterbi: removed old tb

    commit eca3df3d484c0fe4804610473a60acd21e49988b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:11:30 2014 +0100

        writer: updated to new generic client

    commit b4d6144c4da041fedcf9908f405049aadcf25f6f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:10:09 2014 +0100

        reader: updated to new client, added few dummies

    commit 4c365f4194353eb71b704d270323814383dd2d1a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:08:41 2014 +0100

        reader: several bugfixes, updated to new generic client

    commit b85027ef67b87c327eeeba8a66e4688c08588ec4
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:05:57 2014 +0100

        spmv/crs: removed old tb

    commit 305b4085afd0e8224049e8393658fd4e4478512d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:05:17 2014 +0100

        sort/merge: new input data and removed old tb

    commit 6924921c84b7220d929722a5835fc836686d1e76
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:04:30 2014 +0100

        stencil: removed old testbench code

    commit 377c8f5a45484bef7e9bea98a96311298e8161c9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:03:42 2014 +0100

        gemm/blocked: removed old testbench code

    commit 09409228678b1bcd7aa8dc6400f9b96cdd2cf59b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 12:02:02 2014 +0100

        stencil3d: new kernel.description attributes for simple args

    commit 5e4ade448127d4e50aa2d94fb9aa47b2474008c8
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 11:57:36 2014 +0100

        hwswcosim:

         * server: added timeout for connection (non-blocking socket)
         * removed some debug output
         * moved all debug output to stdout instead of stderr

    commit 21610fcd0dd0b5e85204730cca5f39bd13cf47e8
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 20 11:55:46 2014 +0100

        generic client: bugfixes

    commit 6916e516497e1bd27337f6673a32e8adf854e5c0
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 18 20:03:24 2014 +0100

        kernel/common: RCU DPI client

         * DBG output now on stdout instead of stderr

    commit 3ccba5deec09fb7d3586a57202245824b3a68913
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 18 19:09:26 2014 +0100

        kernel/common: generic RCU DPI client (first draft)

    commit 502cee91de8573991b8710e3b684abcefa5cff30
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 18 19:00:18 2014 +0100

        hwswcosim: new client functions to set simple args (32/64bit)

    commit 49beda451e18f9e9a9395bfe245c1aad0be84541
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 18 18:58:03 2014 +0100

        GenerateHLS, baseline:

         * new OFFSET needle in simple arg template: re-orders args in register
           file generated by Vivado HLS
         * reset all simulations to ModelSim

    commit 2957c51f27d952fead9ebfa5f26de064a75fa19a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 18 18:53:27 2014 +0100

        new benchmark: inout1

         * exercises all input and output paths in new generic RCU DPI client:
           has multiple simple args, pointer args and return value of varying
           sizes
         * does nothing useful

    commit 06cac7bb76f03a92d6b1055a587eb56e534642b2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 18 08:05:05 2014 +0100

        GenerateBitstream: fixes in template needle population

    commit 96db459ecedd44112c6040b3bbd90ea04177de59
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 18 08:03:03 2014 +0100

        GenerateSim:

         * deactivated debug output on AXI master
         * bugfix: simulation includes now correctly represented by template
           needles again

    commit b97ad8c2abb6bdee42bf87ccb0c06dc564bcc3a8
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 18 08:01:46 2014 +0100

        hwswcosim: ack of launch delayed until completion

    commit f9318070d6e6464ea46f867df994c082f06f0921
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sat Nov 15 16:00:17 2014 +0100

        hwswcosim: fixed dbg messages in client and server libs

    commit 47b86794ad12c3591a6aa73001fdc661636787e2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sat Nov 15 15:54:06 2014 +0100

        hwswcosim:

          * changed all tasks to 'automatic'

    commit aeca7cd5e3306e07a185d868b73a9bd9848ebd42
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sat Nov 15 15:46:52 2014 +0100

        hwswcosim:

         * bugfix: wrong address calc in set_base
         * extended several types from char to int for the sake of
           maintainability (several bugs concerning wrong sizes of data on one
           of the ends of comm already occurred)
         * also extended types in internal SystemVerilog tasks

    commit d6d17b4db06940452ffefc7b8d306ec3a05c413d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 14 18:15:19 2014 +0100

        arch: baseline

         * major update: using new 2014.3 s_axilite and m_axi interface modes
         * using new 2014.3 slave offset register for m_axi's
         * separated s_axi bundles: A0_ctl contains ctrl + params, AXILiteS the
           base address registers for the masters in order of appearance in sig
         * completely re-wrote sim.tcl.template:
           number of procs create two hierarchies of AXI interconnects, toward
           IP cores and from IP cores toward memory; required number is computed
           automatically based on the target IP's masters and slaves, warnings
           are issued if capacities are exceeded.
           also added a AXI BFM master to control PS memory in 'sim' mode, since
           none of the Zynq BFMs methods to use memory seemed to work properly.

    commit bd4db10b48d257d19141d9d29899902a439106bd
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 14 18:09:20 2014 +0100

        GenerateX:

         * bitstream generation mode is now called 'bit', analogous to 'sim'
         * bitstream project name is now 'bit', also analogous to 'sim'
         * added missing VERSION needle in HLS
         * bugfix: empty preload files list
         * Vivado execution mode now 'batch': proper return of error code

    commit d0903a04505c4af810a3534e8f21c4a0cb7d23a3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 14 18:04:14 2014 +0100

        hwswcosim:

         * new calls: rcu_read_data, rcu_write_data; read/write from/to AXI
           address space visible at PS masters (necessary to access registers
           of IP, read/write_kernel_reg was not sufficient)
         * several improvements and bugfixes, e.g., named parameters fixed some
           misassociations of parameters, better messages

    commit c66fde7869883484175426d543b7946a2e4bd604
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 11 16:03:54 2014 +0100

        hwswcosim:

         * new calls: rcu_read_mem, rcu_write_mem (implemented and tested)
         * bugfixes: return values in case of errors
         * some splint fixes
         * new (preliminary) tests in client.c

    commit af2d3bd5e829cfc2be5ad1f2c4f3c18161b793ae
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 10 18:48:50 2014 +0100

        GenerateSim / baseline:

          * generated testbench 'tb.sv' with SystemVerilog suffix
          * baseline uses hwswcosim includes for harness and API
          * harness: user code is deactivated (external program)

    commit ffb1be8338a2a61ed546a8fbeb77ad38e20fe426
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 10 18:27:04 2014 +0100

        hwswcosim:

         * added wait_cycles call
         * moved includes to .svh ending

    commit 6638bcccc914d00021a6b90f85ff623d387ee53c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 10 16:26:50 2014 +0100

        Added call: rcu_get_time to get simulation time

    commit 7df59c80638e87a2e9b4bb899afa0c22c70d7db7
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Nov 7 11:00:24 2014 +0100

        hwswcosim: initial

         * first draft of client and server libs for communication with sim
         * based on socket IPC
         * trivial protocol, verified with 'reader' example
         * real integration outstanding

    commit 6921b9cbe4d5018cdd67edf20f595858601f34ed
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Nov 6 11:37:35 2014 +0100

        GenerateBitstream: initial version

    commit 7099b31c7432aef76f063c8047d811d6e19d47eb
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 5 17:41:10 2014 +0100

        GenerateSim: bugfix

          * simulate would execute all steps, regardless of previous outcomes

    commit efbfdb88ddaf6b2efaad3fbf91301896219d8a01
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 5 15:40:37 2014 +0100

        GenerateHLS: unbox "Boxed error" exceptions in futures

    commit 2bc511fd719941a6f8f366c1d376696ef97547e0
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 5 15:39:38 2014 +0100

        MachSuite: sort/radix

    commit 3658771c6a38eb439f3dfc6f02444e2162139496
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 5 15:38:05 2014 +0100

        MachSuite: md/grid

    commit df11c62cb2b59dd9e625b96c24489ec96b277391
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 5 15:35:41 2014 +0100

        MachSuite: sort/merge

    commit a6028f0305d00f76224ac0c96d3422b0c87b28c4
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 5 14:45:33 2014 +0100

        Kernel: sudoku

         * using non-ambiguous Sudoku as input (other was broken)
         * added read-after-write dependencies in loop
         * added complete inlining directive

    commit 4d6730ab340fb30d0dd105bf49dafbf9f694ed36
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 5 14:44:44 2014 +0100

        GenerateHLS: increased timeout to 8 hours

    commit f04055aa2478cb3eb1f7721df4aea9d72c455bb6
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 5 12:36:28 2014 +0100

        MachSuite: nw

    commit d4dcd223fb3a99c07b5cd0457a4e0ecb49686f2c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Nov 5 10:10:01 2014 +0100

        Baseline: switched to precompile IP catalog at COMPILED_SIMLIB env var

    commit 6fae93eed37e12650251de412742bd7490d4f704
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 4 19:35:12 2014 +0100

        Generate: major update

         * added GenerateBitstream (with extended sim.tcl.template) for Zynq
         * unified GenerateHLS, GenerateSim, GenerateBitstream
         * much improvement in the code, output
         * complete redesign of output directory structure:
           each kernel now has a subdir, with one subdir for each arch;
           below that there are separate dirs for hls, sim, bit and ipcore
         * separate logs for each ModelSim step (compile, elaborate, simulate)

    commit a179a40b8191182bc387ae082b7beddae9a4c975
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 4 19:34:28 2014 +0100

        arraystruct: bugfixes

    commit d5f5928b3b2f18113534160cdeeef41904f6966b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 4 19:33:24 2014 +0100

        Verilog Test-API: fixed read_mem

    commit 8e4420a9fe240e2f6b540debd624851c989a223e
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 4 10:20:09 2014 +0100

        Template: safer needles enclosed in @NEEDLE@

         * fixes some build problems with partial substitution etc.
         * updated 'baseline' arch accordingly

    commit 8b2d928ec175a72629ea4cc922a3a957f8a252a3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Nov 4 10:19:13 2014 +0100

        MachSuite: viterbi - bugfix in kernel.description

    commit ee7d5e0a897827e95d448d3111b2b29123bf9aa2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 3 19:50:07 2014 +0100

        MachSuite: fft/strided - bugfix in tb-code.v

    commit 3db593624170380d327221a4ebfa851fa9a84596
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 3 19:41:30 2014 +0100

        arch/baseline: dirty hack

         * excluded fft/strided from Vivado HLS cosim; solution would be to
           perform compile_simlib in sim directory (works manually), but this
           is the hack to check Jenkins

    commit 1646940ea3cd2d6cdc2577095ea24ff451cb8cfe
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 3 19:01:35 2014 +0100

        GenerateCommon: dirty hack

         * Jenkins cannot handle subdirs in kernel name; hack: use __ for /

    commit 665131be8da4b4b5f6e6d81c1c932be344124590
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 3 18:46:07 2014 +0100

        Generate:

         * first cleanup pass over Generate classes
         * at least some inline documentation
         * nicer error messages

    commit c5b93b21fd9c97be36c917cd4965b403a677c498
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 3 15:53:31 2014 +0100

        GenerateCommon: bugfix

    commit 2f44c20e634e1d66766a8909aa46916e050293b3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 3 15:43:18 2014 +0100

        MachSuite: viterbi

         * changed simulator to Vivado Simulator (ModelSim does not work)

    commit 26348e82045920bf2790fb94651cedf42498c739
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 3 11:43:08 2014 +0100

        GenerateHLS: copy instead of symlink, Jenkins cannot handle.

    commit cbfa7ce282dcc04caf62d4eea8b69f686490c057
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 3 10:44:05 2014 +0100

        GenerateHLS: reactivated console output

    commit 15aa0621303f60c69318cbc15f6d81e12092a2e4
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 3 10:36:41 2014 +0100

        GenerateSim: Reactivated console output.

    commit cd9beb4ff2fd3bebc7a1ce36963c14a02b702d6d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 3 10:31:26 2014 +0100

        GenerateSim: Deactivated sim execution (separate job)

    commit 4af07597d9592cbff8e3e0f30adfa69ecb3adddb
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Nov 3 09:27:27 2014 +0100

        Generate: support for env vars ARCHITECTURE and KERNEL

    commit 1010f8198d106af29d6ae8b0ef7e2dcbfa6b6ae0
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sat Nov 1 10:30:18 2014 +0100

        kernel/sudoku: Bugfix #2

    commit 48b1741889ebcf09ff098996582f1fca45123e52
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sat Nov 1 10:20:06 2014 +0100

        kernel/sudoku: ModelSim bugfix in tb-code.v

    commit 18a2b767135fcd09987da62c6a79f92819516843
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Oct 31 18:53:17 2014 +0100

        ModelSim change: fixed GenerateSim

    commit c3909828e25c67735f36a41a44e4c8462b9f5cf4
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Oct 31 18:51:16 2014 +0100

        ModelSim port: upgraded kernel tb code

    commit 865e6dcb89ffe91bff792ae3a8bbbab5ad107d78
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Oct 31 18:29:16 2014 +0100

        Ported to ModelSim simulation.

    commit f06576f9dbfc894726da3e39f41b65f7b6ad63e9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 29 18:46:12 2014 +0100

        GenerateSim: exit on error

    commit dc04fb8e07bb58d1ca28d4d7459d956fa0a9a11f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 29 18:45:35 2014 +0100

        GenerateHLS: exit on error

    commit fb66880d67773970d79ef5a167ba5640d580705b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 29 18:40:40 2014 +0100

        Generate:

         * moved testbench generation to GenerateSim
         * bugfixes in KernelDescription

    commit 2962c80f072b298062c809f3a0ea7c5f6b2c3a5b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 29 18:38:25 2014 +0100

        MachSuite: viterbi

    commit 5c058e477ca72ce2059dc84355da725ef0f4ef61
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 29 17:42:02 2014 +0100

        SBT: scalastyle

    commit b81846c2a6a5b335bb1e18989fbc043bd0bc63cf
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 28 17:10:38 2014 +0100

        MachSuite: spmv/ellpack

         * minor changes in Makefile, still last two words of result wrong

    commit 6e4affd87e6a948d95bcd0713e918dfd0cf586d5
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 28 17:07:12 2014 +0100

        MachSuite: spmv/crs

         * fixed some bugs, still last two words of result wrong

    commit d410ea0aef00e4134e4181d55681f4b9a51baf8c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 28 16:26:31 2014 +0100

        MachSuite: bfs/bulk

         * worked on the benchmark, but results are still wrong (cosim ok)

    commit 945bae56a54f425dca1e37bb2722f4c6155134a9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 28 14:26:13 2014 +0100

        MachSuite: fft/transpose

         * not correct; seems to be rounding errors, but not sure

    commit 909be2195794422bd40d8570cd623fefe5b3b1f1
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 28 13:15:43 2014 +0100

        MachSuite: gemm/ncubed

    commit b27ad19c4ec2f9bd7cdb0610fdad48bae38ef933
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 28 13:13:46 2014 +0100

        MachSuite: gemm/blocked

    commit a3afe26250be2992d4fadaa151463676d4413772
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 28 11:30:41 2014 +0100

        MachSuite: md/knn

         * not working; might be rounding errors, could be something else

    commit 106a06069f6f54603ba7aacea770faf1dec971d3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 27 19:13:57 2014 +0100

        MachSuite: kmp/kmp

    commit 2dc06f42324e760efb7e846f86d7edb674080e71
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 27 18:57:02 2014 +0100

        MachSuite: fft/strided

         * testbench check: bugfix in range

    commit 31304b0e5db6975cc165121c4e36cce74b8deca0
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 27 18:55:05 2014 +0100

        MachSuite: spmv/ellpack

    commit 6cfe4bf0832caa47739314b0d834b3bbf0fda366
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 27 18:54:02 2014 +0100

        MachSuite: spmv/crs

    commit d9326b07c115aed9bab72b66f974cd831671b645
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 27 18:28:43 2014 +0100

        MachSuite: md/knn

         * not fully functional; instance must be reduced to 1 by hand

    commit f194b61910fc86acd227c1b93b93f29c1df6babe
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 27 15:51:42 2014 +0100

        MachSuite: stencil/stencil2d

    commit e55f543281a704c2c262823340a8b39284bfbecd
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 27 13:09:47 2014 +0100

        MachSuite: stencil/stencil3d

          * fully working!

    commit 76018c5d8a783ff979bc7e9c8272fcfd3e18e20a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sat Oct 25 17:36:13 2014 +0200

        MachSuite: fft/strided

         * added exception to arch hls.tcl: memcmp does not even work in C sim

    commit 7bf99c2adb774f6dc96c64f319023ac5c54aa44e
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sat Oct 25 15:33:56 2014 +0200

        Sudoku: fixed grid printing

    commit 940e439435f6c48bf5dd2cb69a0c25a23b1d3af5
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Sat Oct 25 15:33:15 2014 +0200

        GenerateCommon:

         * name now primarily determined in kernel.description

    commit 9d4c97aa45478fa0babddfd290f37d5e1b1671d9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Oct 24 18:40:34 2014 +0200

        Kernel: Sudoku Solver

    commit cb3c2d27013f0fc60679abb3831d0eb8f375abfc
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Oct 24 18:39:34 2014 +0200

        GenerateHLS: support for CFLAGS

    commit 01e076ae0109156ac0f184761fad1ff760aed0e2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 23 14:27:14 2014 +0200

        MachSuite: bfs/bulk

    commit 712c08ba4807f61c34ef634b84a7bebf9e392b3b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 23 11:50:46 2014 +0200

        MachSuite: custom testcase

         * arraystruct: testcase with an array of structs in the interface
         * based on non-functional BFS/bulk test case, checks accesses of
           varying bit width

    commit 9fb0826761266f30540be23cdeae532c2c05a40e
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 23 11:49:45 2014 +0200

        MachSuite integration:

         * fixed preload_ddr.txt and check_ddr.txt generation
         * reactivated memchk test

    commit 50f1f83c0a973f88bec658ac3fe8926a828d7919
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 23 11:32:24 2014 +0200

        GenerateHLS:

         * added support for 'OtherDirectives'
         * replaced some explicit newlines by Properties.lineSeparator

    commit 4c323018c3c6fa20eddccadd261a9e73eeac1fb5
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Oct 15 06:31:40 2014 +0200

        MachSuite: implemented aes

         * first multi-master IP core, had to change many things for baseline
         * now support for explicit base addresses for each master interface
         * not yet: automatic calculation of base addresses for instances
         * bugfixes in Tcl for simulation design: very first master (and very
           first master _only_) has to be automated differently than all others
         * adopted base addresses for existing kernels

    commit 6ad059d237ff380216dd08163e15156d42a3c87c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 13 13:26:26 2014 +0200

        MachSuite:

         * modified main harness to generate input data in sim format
         * started to port first benchmark 'aes'
         * not working yet

    commit ce4fa0dbf146ce366e884ce59e8e133e0f9f704d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 13 13:26:09 2014 +0200

        Bugfixing

    commit 092764cf0e15bf5397f38d62aeefff2de1abbea0
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 13 09:39:26 2014 +0200

        Scalastyle: fixed some warnings/errors

    commit bfe01422e9e27f6e53276b4aa6b9c6b7469bea5e
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Oct 10 18:03:20 2014 +0200

        Overview: first draft

    commit d19eeb49dfcf7cd92c5745571b5898330e927be3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Oct 10 17:43:45 2014 +0200

        Bugfixed test cases.

    commit 5f1b2dabe5c490a93be22a78226b43f9224512aa
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 9 17:46:17 2014 +0200

        Chisel stuff:

         * removed clock and reset signals from M-/S-AXI interfaces
         * fixed reset value problem in register file
         * removed outputs from AXI_BusMasterAdapter

    commit 45b00775cf6adc14bc6a57d68f84d442ec383594
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 9 17:45:48 2014 +0200

        Cleaned up build.sbt

    commit a788048b2625700325e59fe75d442359f5314c3d
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 9 17:44:29 2014 +0200

        baseline architecture: bugfixed Verilog include files

    commit efee53adf01772a1ad17bb5fec8e22d648516fdf
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 9 17:36:22 2014 +0200

        Generate process:

         * new architecture: chisel-basic
         * support for additional steps in flow, e.g., the Chisel pass
         * improved output, removed unnecessary copies of files
         * full support for chisel-basic, all three tests pass
         * no parallel building for GenerateHLS, though: Scala's reflection API
           is not thread safe under 2.10 (2.11+ it is claimed to be, but
           currently not supported by Chisel), which causes race conditions in
           the code - sequential execution for now
         * repackaging IP core script
         * bugfixing, improvements (especially test-api in chisel basic)

    commit b0bf8129173b27937c5461e53f014247bb145de2
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 7 18:39:23 2014 +0200

        Bugfixing, additional testcases

         * added writer and readwrite1 test cases, readwrite1 is currently not
           working due to coherency problems
         * some bugfixes in the generators
         * added additional test API call to implement read from memory

    commit 58d648df35d25620ae3694e1c85aa5416dc8200f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 7 17:20:23 2014 +0200

        Generate: finished Simulation task

         * GenerateSim: now works (currently only for reader)
         * added new classes for kernel and arch descriptions: provide helpers
           to get correct paths and centralize defaults for optional values
         * rewrote GenerateSim/GenerateHLS to use those new descriptions
         * bonus effect: extended architecture description for free (files!)
         * general cleanup (we salute you)

    commit fd81ff62c78c07bd7e91065a7e991b4c1c67a3be
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Oct 7 13:09:40 2014 +0200

        build.sbt: fixed feature warnings

    commit 920fb6653ca3562875ea9794e6f94ab78d34d229
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Mon Oct 6 19:44:56 2014 +0200

        GenerateSim:

         * sbt based generation of simulations is now working for the first
           example 'reader'
         * introduced several new templates in arch/
         * developed Verilog test-api.vh include to write testbenches against
         * also added test-harness.vh for a basic harness (BFM simulation only)

    commit 0af336165183a1c64bfbb0dbfacc516f2932bbe4
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 2 18:07:09 2014 +0200

        New build system for IP Cores:

         * more general and concurrent build system based on Scala/SBT
         * architectures define directives, templates etc.
         * kernels define only the kernel itself, i.e., args, top-func,...
         * both are described by the simplest text files KEY = VALUE format
         * compilation via Vivado HLS fully automatic & in parallel
         * generates zip files for all combinations of kernel and arch

    commit 518f29b27bad63d309826e64c03a582801d6c9c0
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 2 11:25:00 2014 +0200

        Fixed Makefile for readwrite1, parallel now ok.

    commit 3b9395aa9a3fc6d7348c2c2d206460451cffdeab
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 2 10:13:20 2014 +0200

        Removed old test setup in test subdir.

    commit 5b43b7371e9055a41865b7b515b933d6134581cd
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Oct 2 10:12:07 2014 +0200

        Testcase: working toward automation

         * automatic simulation and check using Vivado
         * first version, not yet working, readwrite1 check more advanced

    commit fdbebf710a697cc54b238c617f89eb22e029b7c3
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 24 18:08:50 2014 +0200

        WrapperGenerator: online compilation using reflection

         * cool new feature: evaluating generated Chisel code directly without
           moving to .scala file first via reflection API
         * module name is now incomprehensible, but does not affect testing
         * closer to one-step compilation

    commit b97c6cb543a70e432a21592e2f5d6a240ec1e353
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 24 18:07:49 2014 +0200

        Bugfix: overwriting existing Vivado project.

    commit 9016525c706b273bd461d8bb6bb4de2b071553f9
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 24 18:07:02 2014 +0200

        Template: added direct String output.

    commit 98d1a3078c1c3bba148710d9654917082836a48c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 24 15:12:58 2014 +0200

        Added zip archive generation to BFM script.

    commit 2b72040a8af7b71789466c12fce83ee087f604fb
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 24 11:34:25 2014 +0200

        AXI_BusMasterAdapter

         * all three testcase should work now: reader, writer, readwrite1
         * some streamlining of the process is still due

    commit 0f4d069da0c93315ce4c9fd2ce9408285a733f97
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 23 19:21:49 2014 +0200

        New testcase: writer

    commit fdb809168957d76d09532189ceaa0da20abeac82
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 23 19:19:52 2014 +0200

        WrapperGenerator

         * new directory structure in gencores/NAME (created by
           WrapperGenerator)
         * added testbench code substitution and benchmark code files
         * new mechanism to copy preload_ddr.txt files to the output dir
         * copies original Verilog file to output dir as well

    commit 43733021f48585c3e3b804b3de9f452e81fad8ef
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 23 19:17:24 2014 +0200

        AXI_BusMasterAdapter

         * simplified state machine: only one state now, truly parallel accesses
           are not really possible with ap_bus, since it assumes in-order
         * fixed problem with readwrite1: a new read request is issued by HLS
           cores in the cycle immediately following the read; unfortunately, the
           address is only valid in that single cycle as well. had to introduce
           a register indicating such waiting read request and allow updating of
           araddr in all states - seems to have fixed it for now

    commit 52441f6fcd92431f68c6b32b664bb16ade4561fb
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 23 19:16:55 2014 +0200

        Templates: improved/fixed template code

    commit b3c601b94e614862592445ee9f44be6493bd2336
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 23 19:16:03 2014 +0200

        reader: generates preload_ddr.txt mem file for sim

    commit 70178f1574c91961c66b3b3ab0021408baf97a9c
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 23 19:14:33 2014 +0200

        Bugfix: Template replaces literally now

    commit cce271cc92cc0cb817a99a25c3cb7634a4baf84a
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 23 19:13:53 2014 +0200

        New test: readwrite1; added testbench code for reader

    commit 7fd44b1e6aebe68136833fb93eb92a48b5e55a7f
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Fri Sep 19 18:36:59 2014 +0200

        WrapperGenerator: massive overhaul

         * auto-mapping regular input/output ports of given module: i/o ports of
           the wrapped module are automatically wired into the register file, a
           map of the register file is dumped during generation (no file export)
         * register file now has minimal size for wrapped module
         * templates have been overhauled to accomplish the auto wrapping
         * several other changes were necessary to the interface definitions etc
         * cosmetic update on some files (2-space indent ...)

    commit 11af56877c69a25b0eedf01518d47e1cfb7a592b
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Sep 18 17:27:50 2014 +0200

        WrapperGenerator:

         * added micro templating class to generate files
         * moved templates into src hierarchy
         * changed names of some files
         * renamed Main into WrapperGenerator, simplified

    commit ecd2d5cbd9e9ea6aa2f365e313993dd08c17ff16
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 17 16:25:57 2014 +0200

        Added Vivado Tcl script to setup testbench project with Zynq BFM.

    commit 24dfb7f9e67896cbfcd22e7abf71bbf46e528df6
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 17 16:24:14 2014 +0200

        AXI_BusMasterAdapter: fixed incorrect AXI behavior on some signals

    commit 3aeb40d0147276c990a49052c56e24546099b5fd
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 17 16:22:33 2014 +0200

        AXILite_RegisterFile

         * fixed reset glitches for several signals
         * fixed other incorrect AXI behavior

    commit e3f5cf71cd5d437506a41d428635e05a134ddc46
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Wed Sep 17 16:21:26 2014 +0200

        Added generation of Zynq BFM testbench.

    commit 2cdaf83bb23731f483cc522053b18688c5370558
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 16 13:29:34 2014 +0200

        First working version of wrapper generation.

    commit f9d6b9f06bfe5644d96117197b24968dd0209c7c
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Tue Sep 16 10:04:56 2014 +0200

        Work in progress.

    commit aa2d8cea023646f2c6b738c98021b7dc6a1f9d9c
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Mon Sep 15 18:34:12 2014 +0200

        Worked on Wrapper generation, automatization.

    commit 0931df01aa29392705fcf1c0287b482c88068ee3
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Mon Sep 15 16:57:11 2014 +0200

        Reorganized Scala sources; started to implement wrapper generation.

    commit 85f76f66ba0ff0f66f816702ed25e0b16217b400
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Fri Sep 12 19:30:23 2014 +0200

        Interface detection now working correctly.

         * bugfix: now direction and width are also checked
         * bugfix: interfaces with variables are now correctly detected AND the
           code is not a pain-in-the-ass to look at
         * improved Module interface
         * updated and extended unit tests

    commit cc85cbcef339b06046b91e9b33e1d3ee141941e2
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Fri Sep 12 19:30:03 2014 +0200

        Removed old test Verilogs.

    commit 4f0217cae45dc9c377ea4a2b91ea4a1238811b71
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Thu Sep 11 18:35:15 2014 +0200

        Worked on interface detection; not yet working. :(

    commit e9e89707fd62d2e5eebfa46fe0495ce1aaadf2a5
    Author: Jens Korinth <jkorinth@gmx.net>
    Date:   Thu Sep 11 10:37:55 2014 +0200

        Rewrote parser using ANTLR4.

         * dumped old approach, used existing ANTLR4 Verilog 2001 grammar with
           minor fixes (macros, Vivado annotations)
         * basic detector for interfaces in parsed modules working, but does not
           recognize variable names yet

    commit db21d4bb8b87c1b55f473783993e988df91639a0
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 9 19:42:37 2014 +0200

        Updated driver for Sudoku example.

    commit f5fe53b9ac1fda31f75bf6da91ae8c298dc4cdb4
    Author: Jens Korinth <korinth@esa.cs.tu-darmstadt.de>
    Date:   Tue Sep 9 19:40:37 2014 +0200

        Added test/ with new test cases and autowrapper.

    commit dee727c3e75a2903d0d91a042c158bc09a8bc183
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 8 18:36:30 2014 +0200

        IRQ mechanism, FSM bugfix

         * FSM would never leave s_done; now moves to s_idle when 0 is written
           to reg #0
         * cmd register shows "2" when s_done
         * IRQ mechanism: ap_done stays high while s_done

    commit 704e4d7d302d29d1d2444fb705e6d4d4e2249d0a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Aug 8 18:35:58 2014 +0200

        Added driver code and example program for Sudoku.

    commit 23c50c8a2ca593cf2c0c5d4d36508b2ab6256291
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Aug 7 14:31:44 2014 +0200

        AP_BlackBox

         * added AP_BlackBox class to wrap Vivado HLS kernels using the
           AXILite_BusMasterAdapter and an AXILite_RegisterFile
         * changed AXILite_Registerfile logic to be generated by a singleton
           method; this allows easy re-use without resorting to inheritance
           (which does not fully work in Chisel right now)
         * adapted the testbench for Sudoku accordingly

    commit 6c721e8188bf12961722b855bd8c167efbe7c8e8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Aug 4 15:37:40 2014 +0200

        Initial commit.

         * AXILite Register File: accessible via AXILite Slave interface,
           configurable size
         * AXILite Master adapter for ap_bus interface generated by Vivado HLS
           (no bursts, not optimized)
         * two examples: SimpleMaster only performs reads, Sudoku solves Sudoku
           puzzles on an array (read and write)

a831b501

09 May, 2017 1 commit
- Initial commit · 742717e7
  Jens Korinth authored May 09, 2017
  
  742717e7